| .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| .. sectionauthor:: Udit Kumar <u-kumar1@ti.com> |
| |
| J7200 Platforms |
| =============== |
| |
| Introduction: |
| ------------- |
| The J7200 family of SoCs are part of K3 Multicore SoC architecture platform |
| targeting automotive applications. They are designed as a low power, high |
| performance and highly integrated device architecture, adding significant |
| enhancement on processing power, graphics capability, video and imaging |
| processing, virtualization and coherent memory support. |
| |
| The device is partitioned into three functional domains, each containing |
| specific processing cores and peripherals: |
| |
| 1. Wake-up (WKUP) domain: |
| * Device Management and Security Controller (DMSC) |
| |
| 2. Microcontroller (MCU) domain: |
| * Dual Core ARM Cortex-R5F processor |
| |
| 3. MAIN domain: |
| * Dual core 64-bit ARM Cortex-A72 |
| |
| More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1 |
| |
| Boot Flow: |
| ---------- |
| Below is the pictorial representation of boot flow: |
| |
| .. code-block:: text |
| |
| +------------------------------------------------------------------------+-----------------------+ |
| | DMSC | MCU R5 | A72 | MAIN R5/C7x | |
| +------------------------------------------------------------------------+-----------------------+ |
| | +--------+ | | | | |
| | | Reset | | | | | |
| | +--------+ | | | | |
| | : | | | | |
| | +--------+ | +-----------+ | | | |
| | | *ROM* |----------|-->| Reset rls | | | | |
| | +--------+ | +-----------+ | | | |
| | | | | : | | | |
| | | ROM | | : | | | |
| | |services| | : | | | |
| | | | | +-------------+ | | | |
| | | | | | *R5 ROM* | | | | |
| | | | | +-------------+ | | | |
| | | |<---------|---|Load and auth| | | | |
| | | | | | tiboot3.bin | | | | |
| | | Start | | +-------------+ | | | |
| | | TIFS |<---------|---| Start | | | | |
| | | | | | TIFS | | | | |
| | +--------+ | +-------------+ | | | |
| | : | | | | | | |
| | +---------+ | | Load | | | | |
| | | *TIFS* | | | system | | | | |
| | +---------+ | | Config data | | | | |
| | | |<--------|---| | | | | |
| | | | | +-------------+ | | | |
| | | | | : | | | |
| | | | | : | | | |
| | | | | : | | | |
| | | | | +-------------+ | | | |
| | | | | | *R5 SPL* | | | | |
| | | | | +-------------+ | | | |
| | | | | | DDR | | | | |
| | | | | | config | | | | |
| | | | | +-------------+ | | | |
| | | | | | Load | | | | |
| | | | | | tispl.bin | | | | |
| | | | | +-------------+ | | | |
| | | | | | Load R5 | | | | |
| | | | | | firmware | | | | |
| | | | | +-------------+ | | | |
| | | |<--------|---| Start A72 | | | | |
| | | | | | and jump to | | | | |
| | | | | | DM fw image | | | | |
| | | | | +-------------+ | | | |
| | | | | | +-----------+ | | |
| | | |---------|-----------------------|---->| Reset rls | | | |
| | | | | | +-----------+ | | |
| | | TIFS | | | : | | |
| | |Services | | | +-------------+ | | |
| | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | | |
| | | | | | +-------------+ | | |
| | | | | | : | | |
| | | | | | +-----------+ | | |
| | | |<--------|-----------------------|---->| *A72 SPL* | | | |
| | | | | | +-----------+ | | |
| | | | | | | Load | | | |
| | | | | | | u-boot.img| | | |
| | | | | | +-----------+ | | |
| | | | | | : | | |
| | | | | | +-----------+ | | |
| | | |<--------|-----------------------|---->| *U-Boot* | | | |
| | | | | | +-----------+ | | |
| | | | | | | prompt | | | |
| | | | | | +-----------+ | | |
| | | | | | | Load R5 | | | |
| | | | | | | Firmware | | | |
| | | | | | +-----------+ | | |
| | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | |
| | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | |
| | | | | | | Load C7 | | +-----------+ | |
| | | | | | | Firmware | | | |
| | | | | | +-----------+ | | |
| | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | |
| | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | |
| | | | | | | +-----------+ | |
| | | | | | | | |
| | +---------+ | | | | |
| | | | | | |
| +------------------------------------------------------------------------+-----------------------+ |
| |
| - Here DMSC acts as master and provides all the critical services. R5/A72 |
| requests DMSC to get these services done as shown in the above diagram. |
| |
| Sources: |
| -------- |
| 1. Trusted Firmware-A: |
| Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ |
| Branch: master |
| |
| 2. OP-TEE: |
| Tree: https://github.com/OP-TEE/optee_os.git |
| Branch: master |
| |
| 3. U-Boot: |
| Tree: https://source.denx.de/u-boot/u-boot |
| Branch: master |
| |
| 4. TI Linux Firmware: |
| Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git |
| Branch: ti-linux-firmware |
| |
| Build procedure: |
| ---------------- |
| 1. Trusted Firmware-A: |
| |
| .. code-block:: bash |
| |
| $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed |
| |
| 2. OP-TEE: |
| |
| .. code-block:: bash |
| |
| $ make PLATFORM=k3-j7200 CFG_ARM64_core=y |
| |
| 3. U-Boot: |
| |
| * 4.1 R5: |
| |
| .. code-block:: bash |
| |
| $ make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5 |
| $ make CROSS_COMPILE=arm-linux-gnueabihf- \ |
| BINMAN_INDIRS=<path/to/ti-linux-firmware> |
| |
| * 4.2 A72: |
| |
| .. code-block:: bash |
| |
| $ make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72 |
| $ make CROSS_COMPILE=aarch64-linux-gnu- \ |
| BL31=<path/to/trusted-firmware-a/dir>/build/k3/generic/release/bl31.bin \ |
| TEE=<path/to/optee_os/dir>/out/arm-plat-k3/core/tee-raw.bin \ |
| BINMAN_INDIRS=<path/to/ti-linux-firmware> |
| |
| Target Images |
| -------------- |
| Copy the below images to an SD card and boot: |
| |
| - GP |
| |
| * tiboot3-j7200-gp-evm.bin from step 4.1 |
| * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2 |
| |
| - HS-FS |
| |
| * tiboot3-j7200_sr2-hs-fs-evm.bin from step 4.1 |
| * tispl.bin, u-boot.img from step 4.2 |
| |
| - HS-SE |
| |
| * tiboot3-j7200_sr2-hs-evm.bin from step 4.1 |
| * tispl.bin, u-boot.img from step 4.2 |
| |
| Image formats: |
| -------------- |
| |
| - tiboot3.bin: |
| |
| .. code-block:: console |
| |
| +-----------------------+ |
| | X.509 | |
| | Certificate | |
| | +-------------------+ | |
| | | | | |
| | | R5 | | |
| | | u-boot-spl.bin | | |
| | | | | |
| | +-------------------+ | |
| | | | | |
| | | FIT header | | |
| | | +---------------+ | | |
| | | | | | | |
| | | | DTB 1...N | | | |
| | | +---------------+ | | |
| | +-------------------+ | |
| | | | | |
| | | FIT HEADER | | |
| | | +---------------+ | | |
| | | | | | | |
| | | | sysfw.bin | | | |
| | | +---------------+ | | |
| | | | | | | |
| | | | board config | | | |
| | | +---------------+ | | |
| | | | | | | |
| | | | PM config | | | |
| | | +---------------+ | | |
| | | | | | | |
| | | | RM config | | | |
| | | +---------------+ | | |
| | | | | | | |
| | | | Secure config | | | |
| | | +---------------+ | | |
| | +-------------------+ | |
| +-----------------------+ |
| |
| - tispl.bin |
| |
| .. code-block:: console |
| |
| +-----------------------+ |
| | | |
| | FIT HEADER | |
| | +-------------------+ | |
| | | | | |
| | | A72 TF-A | | |
| | +-------------------+ | |
| | | | | |
| | | A72 OP-TEE | | |
| | +-------------------+ | |
| | | | | |
| | | R5 DM FW | | |
| | +-------------------+ | |
| | | | | |
| | | A72 SPL | | |
| | +-------------------+ | |
| | | | | |
| | | SPL DTB 1...N | | |
| | +-------------------+ | |
| +-----------------------+ |
| |
| |
| Switch Setting for Boot Mode |
| ---------------------------- |
| |
| Boot Mode pins provide means to select the boot mode and options before the |
| device is powered up. After every POR, they are the main source to populate |
| the Boot Parameter Tables. |
| |
| The following table shows some common boot modes used on J7200 platform. More |
| details can be found in the Technical Reference Manual: |
| https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section. |
| |
| |
| *Boot Modes* |
| |
| ============ ============= ============= |
| Switch Label SW9: 12345678 SW8: 12345678 |
| ============ ============= ============= |
| SD 00000000 10000010 |
| EMMC 01000000 10000000 |
| OSPI 01000000 00000110 |
| UART 01110000 00000000 |
| USB DFU 00100000 10000000 |
| ============ ============= ============= |
| |
| For SW8 and SW9, the switch state in the "ON" position = 1. |
| |
| eMMC: |
| ----- |
| ROM supports booting from eMMC raw read or UDA FS mode. |
| |
| Below is memory layout in case of booting from |
| boot 0/1 partition in raw mode. |
| |
| Current allocated size for tiboot3 size is 1MB, tispl is 2MB. |
| |
| Size of u-boot.img is taken 4MB for refernece, |
| But this is subject to change depending upon atf, optee size |
| |
| .. code-block:: console |
| |
| boot0/1 partition (8 MB) user partition |
| 0x0+----------------------------------+ 0x0+------------------------+ |
| | tiboot3.bin (1 MB) | | | |
| 0x800+----------------------------------+ | | |
| | tispl.bin (2 MB) | | | |
| 0x1800+----------------------------------+ | | |
| | u-boot.img (4MB) | | | |
| 0x3800+----------------------------------+ | | |
| | | | | |
| 0x3900+ environment | | | |
| | | | | |
| 0x3A00+----------------------------------+ +-------------------------+ |
| |
| In case of UDA FS mode booting, following is layout. |
| |
| All boot images tiboot3.bin, tispl and u-boot should be written to |
| fat formatted UDA FS as file. |
| |
| .. code-block:: console |
| |
| boot0/1 partition (8 MB) user partition |
| 0x0+---------------------------------+ 0x0+-------------------------+ |
| | | | tiboot3.bin* | |
| 0x800+----------------------------------+ | | |
| | | | tispl.bin | |
| 0x1800+----------------------------------+ | | |
| | | | u-boot.img | |
| 0x3800+----------------------------------+ | | |
| | | | | |
| 0x3900+ | | environment | |
| | | | | |
| 0x3A00+----------------------------------+ +-------------------------+ |
| |
| |
| |
| In case of booting from eMMC, write above images into raw or UDA FS. |
| and set mmc partconf accordingly. |