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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1ee652ab2f356c8a775bc4878f32f26f29a4c941 / . / doc / board / ti / j7200_evm.rst
blob: 5e3d75059ca59fa4f7bbc4449a770b6a1c770738 [file] [log] [blame]
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]1.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2.. sectionauthor:: Udit Kumar <u-kumar1@ti.com>
3
4J7200 Platforms
5===============
6
7Introduction:
8-------------
9The J7200 family of SoCs are part of K3 Multicore SoC architecture platform
10targeting automotive applications. They are designed as a low power, high
11performance and highly integrated device architecture, adding significant
12enhancement on processing power, graphics capability, video and imaging
13processing, virtualization and coherent memory support.
14
15The device is partitioned into three functional domains, each containing
16specific processing cores and peripherals:
17
181. Wake-up (WKUP) domain:
19 * Device Management and Security Controller (DMSC)
20
212. Microcontroller (MCU) domain:
22 * Dual Core ARM Cortex-R5F processor
23
243. MAIN domain:
25 * Dual core 64-bit ARM Cortex-A72
26
27More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1
28
29Boot Flow:
30----------
31Below is the pictorial representation of boot flow:
32
33.. code-block:: text
34
35 +------------------------------------------------------------------------+-----------------------+
36 | DMSC | MCU R5 | A72 | MAIN R5/C7x |
37 +------------------------------------------------------------------------+-----------------------+
38 | +--------+ | | | |
39 | | Reset | | | | |
40 | +--------+ | | | |
41 | : | | | |
42 | +--------+ | +-----------+ | | |
43 | | *ROM* |----------|-->| Reset rls | | | |
44 | +--------+ | +-----------+ | | |
45 | | | | : | | |
46 | | ROM | | : | | |
47 | |services| | : | | |
48 | | | | +-------------+ | | |
49 | | | | | *R5 ROM* | | | |
50 | | | | +-------------+ | | |
51 | | |<---------|---|Load and auth| | | |
52 | | | | | tiboot3.bin | | | |
53 | | Start | | +-------------+ | | |
54 | | TIFS |<---------|---| Start | | | |
55 | | | | | TIFS | | | |
56 | +--------+ | +-------------+ | | |
57 | : | | | | | |
58 | +---------+ | | Load | | | |
59 | | *TIFS* | | | system | | | |
60 | +---------+ | | Config data | | | |
61 | | |<--------|---| | | | |
62 | | | | +-------------+ | | |
63 | | | | : | | |
64 | | | | : | | |
65 | | | | : | | |
66 | | | | +-------------+ | | |
67 | | | | | *R5 SPL* | | | |
68 | | | | +-------------+ | | |
69 | | | | | DDR | | | |
70 | | | | | config | | | |
71 | | | | +-------------+ | | |
72 | | | | | Load | | | |
73 | | | | | tispl.bin | | | |
74 | | | | +-------------+ | | |
75 | | | | | Load R5 | | | |
76 | | | | | firmware | | | |
77 | | | | +-------------+ | | |
78 | | |<--------|---| Start A72 | | | |
79 | | | | | and jump to | | | |
80 | | | | | DM fw image | | | |
81 | | | | +-------------+ | | |
82 | | | | | +-----------+ | |
83 | | |---------|-----------------------|---->| Reset rls | | |
84 | | | | | +-----------+ | |
85 | | TIFS | | | : | |
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]86 | |Services | | | +-------------+ | |
87 | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | |
88 | | | | | +-------------+ | |
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]89 | | | | | : | |
90 | | | | | +-----------+ | |
91 | | |<--------|-----------------------|---->| *A72 SPL* | | |
92 | | | | | +-----------+ | |
93 | | | | | | Load | | |
94 | | | | | | u-boot.img| | |
95 | | | | | +-----------+ | |
96 | | | | | : | |
97 | | | | | +-----------+ | |
98 | | |<--------|-----------------------|---->| *U-Boot* | | |
99 | | | | | +-----------+ | |
100 | | | | | | prompt | | |
101 | | | | | +-----------+ | |
102 | | | | | | Load R5 | | |
103 | | | | | | Firmware | | |
104 | | | | | +-----------+ | |
105 | | |<--------|-----------------------|-----| Start R5 | | +-----------+ |
106 | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | |
107 | | | | | | Load C7 | | +-----------+ |
108 | | | | | | Firmware | | |
109 | | | | | +-----------+ | |
110 | | |<--------|-----------------------|-----| Start C7 | | +-----------+ |
111 | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | |
112 | | | | | | +-----------+ |
113 | | | | | | |
114 | +---------+ | | | |
115 | | | | |
116 +------------------------------------------------------------------------+-----------------------+
117
118- Here DMSC acts as master and provides all the critical services. R5/A72
119 requests DMSC to get these services done as shown in the above diagram.
120
121Sources:
122--------
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1231. Trusted Firmware-A:
124 Tree: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]125 Branch: master
126
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1272. OP-TEE:
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]128 Tree: https://github.com/OP-TEE/optee_os.git
129 Branch: master
130
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1313. U-Boot:
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]132 Tree: https://source.denx.de/u-boot/u-boot
133 Branch: master
134
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1354. TI Linux Firmware:
136 Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git
137 Branch: ti-linux-firmware
138
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]139Build procedure:
140----------------
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1411. Trusted Firmware-A:
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]142
143.. code-block:: bash
144
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]145 $ make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]146
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1472. OP-TEE:
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]148
149.. code-block:: bash
150
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]151 $ make PLATFORM=k3-j7200 CFG_ARM64_core=y
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]152
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]1533. U-Boot:
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]154
155* 4.1 R5:
156
157.. code-block:: bash
158
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]159 $ make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5
160 $ make CROSS_COMPILE=arm-linux-gnueabihf- \
161 BINMAN_INDIRS=<path/to/ti-linux-firmware>
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]162
163* 4.2 A72:
164
165.. code-block:: bash
166
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]167 $ make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72
168 $ make CROSS_COMPILE=aarch64-linux-gnu- \
169 BL31=<path/to/trusted-firmware-a/dir>/build/k3/generic/release/bl31.bin \
170 TEE=<path/to/optee_os/dir>/out/arm-plat-k3/core/tee-raw.bin \
171 BINMAN_INDIRS=<path/to/ti-linux-firmware>
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]172
173Target Images
174--------------
175Copy the below images to an SD card and boot:
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]176
177 - GP
178
179 * tiboot3-j7200-gp-evm.bin from step 4.1
180 * tispl.bin_unsigned, u-boot.img_unsigned from step 4.2
181
182 - HS-FS
183
184 * tiboot3-j7200_sr2-hs-fs-evm.bin from step 4.1
185 * tispl.bin, u-boot.img from step 4.2
186
187 - HS-SE
188
189 * tiboot3-j7200_sr2-hs-evm.bin from step 4.1
190 * tispl.bin, u-boot.img from step 4.2
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]191
192Image formats:
193--------------
194
195- tiboot3.bin:
196
197.. code-block:: console
198
199 +-----------------------+
200 | X.509 |
201 | Certificate |
202 | +-------------------+ |
203 | | | |
204 | | R5 | |
205 | | u-boot-spl.bin | |
206 | | | |
207 | +-------------------+ |
208 | | | |
209 | | FIT header | |
210 | | +---------------+ | |
211 | | | | | |
212 | | | DTB 1...N | | |
213 | | +---------------+ | |
214 | +-------------------+ |
215 | | | |
216 | | FIT HEADER | |
217 | | +---------------+ | |
218 | | | | | |
219 | | | sysfw.bin | | |
220 | | +---------------+ | |
221 | | | | | |
222 | | | board config | | |
223 | | +---------------+ | |
224 | | | | | |
225 | | | PM config | | |
226 | | +---------------+ | |
227 | | | | | |
228 | | | RM config | | |
229 | | +---------------+ | |
230 | | | | | |
231 | | | Secure config | | |
232 | | +---------------+ | |
233 | +-------------------+ |
234 +-----------------------+
235
236- tispl.bin
237
238.. code-block:: console
239
240 +-----------------------+
241 | |
242 | FIT HEADER |
243 | +-------------------+ |
244 | | | |
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]245 | | A72 TF-A | |
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]246 | +-------------------+ |
247 | | | |
Neha Malcom Francis1ee652a2023-07-22 00:14:43 +0530[diff] [blame^]248 | | A72 OP-TEE | |
Udit Kumardb7af512023-05-11 14:47:48 +0530[diff] [blame]249 | +-------------------+ |
250 | | | |
251 | | R5 DM FW | |
252 | +-------------------+ |
253 | | | |
254 | | A72 SPL | |
255 | +-------------------+ |
256 | | | |
257 | | SPL DTB 1...N | |
258 | +-------------------+ |
259 +-----------------------+
260
261
262Switch Setting for Boot Mode
263----------------------------
264
265Boot Mode pins provide means to select the boot mode and options before the
266device is powered up. After every POR, they are the main source to populate
267the Boot Parameter Tables.
268
269The following table shows some common boot modes used on J7200 platform. More
270details can be found in the Technical Reference Manual:
271https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section.
272
273
274*Boot Modes*
275
276============ ============= =============
277Switch Label SW9: 12345678 SW8: 12345678
278============ ============= =============
279SD 00000000 10000010
280EMMC 01000000 10000000
281OSPI 01000000 00000110
282UART 01110000 00000000
283USB DFU 00100000 10000000
284============ ============= =============
285
286For SW8 and SW9, the switch state in the "ON" position = 1.
287
288eMMC:
289-----
290ROM supports booting from eMMC raw read or UDA FS mode.
291
292Below is memory layout in case of booting from
293boot 0/1 partition in raw mode.
294
295Current allocated size for tiboot3 size is 1MB, tispl is 2MB.
296
297Size of u-boot.img is taken 4MB for refernece,
298But this is subject to change depending upon atf, optee size
299
300.. code-block:: console
301
302 boot0/1 partition (8 MB) user partition
303 0x0+----------------------------------+ 0x0+------------------------+
304 | tiboot3.bin (1 MB) | | |
305 0x800+----------------------------------+ | |
306 | tispl.bin (2 MB) | | |
307 0x1800+----------------------------------+ | |
308 | u-boot.img (4MB) | | |
309 0x3800+----------------------------------+ | |
310 | | | |
311 0x3900+ environment | | |
312 | | | |
313 0x3A00+----------------------------------+ +-------------------------+
314
315In case of UDA FS mode booting, following is layout.
316
317All boot images tiboot3.bin, tispl and u-boot should be written to
318fat formatted UDA FS as file.
319
320.. code-block:: console
321
322 boot0/1 partition (8 MB) user partition
323 0x0+---------------------------------+ 0x0+-------------------------+
324 | | | tiboot3.bin* |
325 0x800+----------------------------------+ | |
326 | | | tispl.bin |
327 0x1800+----------------------------------+ | |
328 | | | u-boot.img |
329 0x3800+----------------------------------+ | |
330 | | | |
331 0x3900+ | | environment |
332 | | | |
333 0x3A00+----------------------------------+ +-------------------------+
334
335
336
337In case of booting from eMMC, write above images into raw or UDA FS.
338and set mmc partconf accordingly.