* Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c
index 19f8ff8..30a2091 100644
--- a/cpu/74xx_7xx/cpu.c
+++ b/cpu/74xx_7xx/cpu.c
@@ -194,7 +194,7 @@
!defined(CONFIG_ELPPC)
/* no generic way to do board reset. simply call soft_reset. */
void
-do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr;
/* flush and disable I/D cache */
diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c
index 23b71d4..12bdf37 100644
--- a/cpu/74xx_7xx/speed.c
+++ b/cpu/74xx_7xx/speed.c
@@ -49,29 +49,29 @@
};
static const int hid1_fx_multipliers_x_10[] = {
- 00, /* 0000 - off */
- 00, /* 0001 - off */
- 10, /* 0010 - bypass */
- 10, /* 0011 - bypass */
- 20, /* 0100 - 2x */
- 25, /* 0101 - 2.5x */
- 30, /* 0110 - 3x */
- 35, /* 0111 - 3.5x */
- 40, /* 1000 - 4x */
- 45, /* 1001 - 4.5x */
- 50, /* 1010 - 5x */
- 55, /* 1011 - 5.5x */
- 60, /* 1100 - 6x */
- 65, /* 1101 - 6.5x */
- 70, /* 1110 - 7x */
- 75, /* 1111 - 7.5 */
- 80, /* 10000 - 8x */
- 85, /* 10001 - 8.5x */
- 90, /* 10010 - 9x */
- 95, /* 10011 - 9.5x */
- 100, /* 10100 - 10x */
- 110, /* 10101 - 11x */
- 120, /* 10110 - 12x */
+ 00, /* 0000 - off */
+ 00, /* 0001 - off */
+ 10, /* 0010 - bypass */
+ 10, /* 0011 - bypass */
+ 20, /* 0100 - 2x */
+ 25, /* 0101 - 2.5x */
+ 30, /* 0110 - 3x */
+ 35, /* 0111 - 3.5x */
+ 40, /* 1000 - 4x */
+ 45, /* 1001 - 4.5x */
+ 50, /* 1010 - 5x */
+ 55, /* 1011 - 5.5x */
+ 60, /* 1100 - 6x */
+ 65, /* 1101 - 6.5x */
+ 70, /* 1110 - 7x */
+ 75, /* 1111 - 7.5 */
+ 80, /* 10000 - 8x */
+ 85, /* 10001 - 8.5x */
+ 90, /* 10010 - 9x */
+ 95, /* 10011 - 9.5x */
+ 100, /* 10100 - 10x */
+ 110, /* 10101 - 11x */
+ 120, /* 10110 - 12x */
};
@@ -87,8 +87,8 @@
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_750FX
- ulong clock = CFG_BUS_CLK * \
- hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
+ ulong clock = CFG_BUS_CLK * \
+ hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
#else
ulong clock = CFG_BUS_CLK * \
hid1_multipliers_x_10[get_hid1 () >> 28] / 10;
diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index 4857908..7d37c8e 100644
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -233,9 +233,9 @@
STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
- /*
- * On the MPC8xx, this is a software emulation interrupt. It
- * occurs for all unimplemented and illegal instructions.
+ /*
+ * On the MPC8xx, this is a software emulation interrupt. It
+ * occurs for all unimplemented and illegal instructions.
*/
STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
@@ -282,9 +282,9 @@
#if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
.long 0x7e00066c
/*
- * dssall instruction, gas doesn't have it yet
- * ...for altivec, data stream stop all this probably
- * isn't needed unless we warm (software) reboot U-Boot
+ * dssall instruction, gas doesn't have it yet
+ * ...for altivec, data stream stop all this probably
+ * isn't needed unless we warm (software) reboot U-Boot
*/
#endif
@@ -325,15 +325,15 @@
* Cache must be enabled here for stack-in-cache trick.
* This means we need to enable the BATS.
* This means:
- * 1) for the EVB, original gt regs need to be mapped
+ * 1) for the EVB, original gt regs need to be mapped
* 2) need to have an IBAT for the 0xf region,
* we are running there!
- * Cache should be turned on after BATs, since by default
- * everything is write-through.
- * The init-mem BAT can be reused after reloc. The old
- * gt-regs BAT can be reused after board_init_f calls
- * board_pre_init (EVB only).
- */
+ * Cache should be turned on after BATs, since by default
+ * everything is write-through.
+ * The init-mem BAT can be reused after reloc. The old
+ * gt-regs BAT can be reused after board_init_f calls
+ * board_pre_init (EVB only).
+ */
#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC)
/* enable address translation */
bl enable_addr_trans
@@ -391,10 +391,10 @@
mtspr DBAT2U, r0
mtspr DBAT3U, r0
#ifdef CONFIG_750FX
- mtspr DBAT4U, r0
- mtspr DBAT5U, r0
- mtspr DBAT6U, r0
- mtspr DBAT7U, r0
+ mtspr DBAT4U, r0
+ mtspr DBAT5U, r0
+ mtspr DBAT6U, r0
+ mtspr DBAT7U, r0
#endif
isync
sync
@@ -479,76 +479,76 @@
#ifdef CONFIG_750FX
/* IBAT 4 */
- addis r4, r0, CFG_IBAT4L@h
- ori r4, r4, CFG_IBAT4L@l
- addis r3, r0, CFG_IBAT4U@h
- ori r3, r3, CFG_IBAT4U@l
- mtspr IBAT4L, r4
- mtspr IBAT4U, r3
- isync
+ addis r4, r0, CFG_IBAT4L@h
+ ori r4, r4, CFG_IBAT4L@l
+ addis r3, r0, CFG_IBAT4U@h
+ ori r3, r3, CFG_IBAT4U@l
+ mtspr IBAT4L, r4
+ mtspr IBAT4U, r3
+ isync
/* DBAT 4 */
- addis r4, r0, CFG_DBAT4L@h
- ori r4, r4, CFG_DBAT4L@l
- addis r3, r0, CFG_DBAT4U@h
- ori r3, r3, CFG_DBAT4U@l
- mtspr DBAT4L, r4
- mtspr DBAT4U, r3
- isync
+ addis r4, r0, CFG_DBAT4L@h
+ ori r4, r4, CFG_DBAT4L@l
+ addis r3, r0, CFG_DBAT4U@h
+ ori r3, r3, CFG_DBAT4U@l
+ mtspr DBAT4L, r4
+ mtspr DBAT4U, r3
+ isync
- /* IBAT 5 */
- addis r4, r0, CFG_IBAT5L@h
- ori r4, r4, CFG_IBAT5L@l
- addis r3, r0, CFG_IBAT5U@h
- ori r3, r3, CFG_IBAT5U@l
- mtspr IBAT5L, r4
- mtspr IBAT5U, r3
- isync
+ /* IBAT 5 */
+ addis r4, r0, CFG_IBAT5L@h
+ ori r4, r4, CFG_IBAT5L@l
+ addis r3, r0, CFG_IBAT5U@h
+ ori r3, r3, CFG_IBAT5U@l
+ mtspr IBAT5L, r4
+ mtspr IBAT5U, r3
+ isync
/* DBAT 5 */
- addis r4, r0, CFG_DBAT5L@h
- ori r4, r4, CFG_DBAT5L@l
- addis r3, r0, CFG_DBAT5U@h
- ori r3, r3, CFG_DBAT5U@l
- mtspr DBAT5L, r4
- mtspr DBAT5U, r3
- isync
+ addis r4, r0, CFG_DBAT5L@h
+ ori r4, r4, CFG_DBAT5L@l
+ addis r3, r0, CFG_DBAT5U@h
+ ori r3, r3, CFG_DBAT5U@l
+ mtspr DBAT5L, r4
+ mtspr DBAT5U, r3
+ isync
- /* IBAT 6 */
- addis r4, r0, CFG_IBAT6L@h
- ori r4, r4, CFG_IBAT6L@l
- addis r3, r0, CFG_IBAT6U@h
- ori r3, r3, CFG_IBAT6U@l
- mtspr IBAT6L, r4
- mtspr IBAT6U, r3
- isync
+ /* IBAT 6 */
+ addis r4, r0, CFG_IBAT6L@h
+ ori r4, r4, CFG_IBAT6L@l
+ addis r3, r0, CFG_IBAT6U@h
+ ori r3, r3, CFG_IBAT6U@l
+ mtspr IBAT6L, r4
+ mtspr IBAT6U, r3
+ isync
/* DBAT 6 */
- addis r4, r0, CFG_DBAT6L@h
- ori r4, r4, CFG_DBAT6L@l
- addis r3, r0, CFG_DBAT6U@h
- ori r3, r3, CFG_DBAT6U@l
- mtspr DBAT6L, r4
- mtspr DBAT6U, r3
- isync
+ addis r4, r0, CFG_DBAT6L@h
+ ori r4, r4, CFG_DBAT6L@l
+ addis r3, r0, CFG_DBAT6U@h
+ ori r3, r3, CFG_DBAT6U@l
+ mtspr DBAT6L, r4
+ mtspr DBAT6U, r3
+ isync
- /* IBAT 7 */
- addis r4, r0, CFG_IBAT7L@h
- ori r4, r4, CFG_IBAT7L@l
- addis r3, r0, CFG_IBAT7U@h
- ori r3, r3, CFG_IBAT7U@l
- mtspr IBAT7L, r4
- mtspr IBAT7U, r3
- isync
+ /* IBAT 7 */
+ addis r4, r0, CFG_IBAT7L@h
+ ori r4, r4, CFG_IBAT7L@l
+ addis r3, r0, CFG_IBAT7U@h
+ ori r3, r3, CFG_IBAT7U@l
+ mtspr IBAT7L, r4
+ mtspr IBAT7U, r3
+ isync
/* DBAT 7 */
- addis r4, r0, CFG_DBAT7L@h
- ori r4, r4, CFG_DBAT7L@l
- addis r3, r0, CFG_DBAT7U@h
- ori r3, r3, CFG_DBAT7U@l
- mtspr DBAT7L, r4
- mtspr DBAT7U, r3
- isync
+ addis r4, r0, CFG_DBAT7L@h
+ ori r4, r4, CFG_DBAT7L@l
+ addis r3, r0, CFG_DBAT7U@h
+ ori r3, r3, CFG_DBAT7U@l
+ mtspr DBAT7L, r4
+ mtspr DBAT7U, r3
+ isync
#endif
/* bats are done, now invalidate the TLBs */
@@ -768,8 +768,8 @@
/*
* Relocation Function, r14 point to got2+0x8000
*
- * Adjust got2 pointers, no need to check for 0, this code
- * already puts a few entries in the table.
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
@@ -783,7 +783,7 @@
bdnz 1b
/*
- * Now adjust the fixups and the pointers to the fixups
+ * Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
2: li r0,__fixup_entries@sectoff@l
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index 52787fe..b1ee188 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -80,7 +80,6 @@
#endif
-
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
@@ -91,7 +90,7 @@
{
unsigned long flags;
const char *processor_modes[] =
- { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
+ { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
"UK6_26", "UK7_26",
"UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
"UK14_26", "UK15_26",
diff --git a/cpu/arm720t/start.S b/cpu/arm720t/start.S
index e9899a9..2ca91d2 100644
--- a/cpu/arm720t/start.S
+++ b/cpu/arm720t/start.S
@@ -24,7 +24,6 @@
*/
-
#include <config.h>
#include <version.h>
@@ -247,8 +246,6 @@
mov pc, lr
-
-
/*
*************************************************************************
*
diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c
index dd944fb..9ff06c1 100644
--- a/cpu/arm920t/interrupts.c
+++ b/cpu/arm920t/interrupts.c
@@ -91,7 +91,6 @@
#endif
-
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
diff --git a/cpu/arm920t/serial.c b/cpu/arm920t/serial.c
index 10cfade..7ed452e 100644
--- a/cpu/arm920t/serial.c
+++ b/cpu/arm920t/serial.c
@@ -92,7 +92,7 @@
int serial_getc (void)
{
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
-
+
/* wait for character to arrive */
while (!(uart->UTRSTAT & 0x1));
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index ed16176..9f53b87 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -25,7 +25,6 @@
*/
-
#include <config.h>
#include <version.h>
@@ -271,8 +270,6 @@
mov pc, lr
-
-
/*
*************************************************************************
*
diff --git a/cpu/at91rm9200/at45.c b/cpu/at91rm9200/at45.c
index e0057e7..cf456fb 100644
--- a/cpu/at91rm9200/at45.c
+++ b/cpu/at91rm9200/at45.c
@@ -45,7 +45,7 @@
/* Reset the SPI */
AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
- /* Configure SPI in Master Mode with No CS selected !!! */
+ /* Configure SPI in Master Mode with No CS selected !!! */
AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
/* Configure CS0 and CS3 */
@@ -83,38 +83,38 @@
/*----------------------------------------------------------------------------*/
unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
{
- unsigned int timeout;
+ unsigned int timeout;
pDesc->state = BUSY;
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
- /* Initialize the Transmit and Receive Pointer */
- AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
- AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
+ /* Initialize the Transmit and Receive Pointer */
+ AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
+ AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
- /* Intialize the Transmit and Receive Counters */
- AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
- AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
+ /* Intialize the Transmit and Receive Counters */
+ AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
+ AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
if ( pDesc->tx_data_size != 0 ) {
- /* Initialize the Next Transmit and Next Receive Pointer */
- AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
+ /* Initialize the Next Transmit and Next Receive Pointer */
+ AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
/* Intialize the Next Transmit and Next Receive Counters */
AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
- AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
- }
+ AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
+ }
- /* arm simple, non interrupt dependent timer */
+ /* arm simple, non interrupt dependent timer */
reset_timer_masked();
timeout = 0;
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
- AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
- pDesc->state = IDLE;
+ AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
+ pDesc->state = IDLE;
if (timeout >= CFG_SPI_WRITE_TOUT){
printf("Error Timeout\n\r");
@@ -181,12 +181,12 @@
pDesc->command[1] = 0;
pDesc->DataFlash_state = GET_STATUS;
- pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */
- pDesc->tx_cmd_pt = pDesc->command ;
- pDesc->rx_cmd_pt = pDesc->command ;
- pDesc->rx_cmd_size = 2 ;
- pDesc->tx_cmd_size = 2 ;
- status = AT91F_SpiWrite (pDesc);
+ pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */
+ pDesc->tx_cmd_pt = pDesc->command ;
+ pDesc->rx_cmd_pt = pDesc->command ;
+ pDesc->rx_cmd_size = 2 ;
+ pDesc->tx_cmd_size = 2 ;
+ status = AT91F_SpiWrite (pDesc);
pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
@@ -215,7 +215,6 @@
}
-
/*------------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashContinuousRead */
/* Object : Continuous stream Read */
@@ -226,7 +225,7 @@
/* Return value : State of the dataflash */
/*------------------------------------------------------------------------------*/
AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
- AT91PS_DataFlash pDataFlash,
+ AT91PS_DataFlash pDataFlash,
int src,
unsigned char *dataBuffer,
int sizeToRead )
@@ -245,7 +244,6 @@
}
-
/*------------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashPagePgmBuf */
/* Object : Main memory page program through buffer 1 or buffer 2 */
@@ -289,13 +287,12 @@
return DATAFLASH_BAD_COMMAND;
/* no data to transmit or receive */
- pDataFlash->pDataFlashDesc->tx_data_size = 0;
+ pDataFlash->pDataFlashDesc->tx_data_size = 0;
return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, 4, page*pDataFlash->pDevice->pages_size));
}
-
/*----------------------------------------------------------------------------- */
/* Function Name : AT91F_DataFlashWriteBuffer */
/* Object : Write data to the internal sram buffer 1 or 2 */
@@ -324,24 +321,24 @@
if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
return DATAFLASH_BUSY;
- /* Send first Write Command */
- pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
+ /* Send first Write Command */
+ pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
pDataFlash->pDataFlashDesc->command[1] = 0;
- pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
- pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
+ pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
+ pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
- pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->tx_cmd_size = 4 ;
- pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
- pDataFlash->pDataFlashDesc->rx_cmd_size = 4 ;
+ pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
+ pDataFlash->pDataFlashDesc->tx_cmd_size = 4 ;
+ pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
+ pDataFlash->pDataFlashDesc->rx_cmd_size = 4 ;
- pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ;
- pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ;
- pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
- pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
+ pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ;
+ pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ;
+ pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
+ pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
- return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
+ return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
}
@@ -404,7 +401,6 @@
}
-
/*------------------------------------------------------------------------------*/
/* Function Name : AT91F_DataFlashWrite_Overloaded */
/* Object : */
@@ -422,11 +418,11 @@
AT91F_SpiEnable(pDataFlash->pDevice->cs);
- if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
+ if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
return DATAFLASH_MEMORY_OVERFLOW;
- /* If destination does not fit a page start address */
- if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) {
+ /* If destination does not fit a page start address */
+ if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) {
length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
if (size < length)
@@ -438,12 +434,12 @@
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, 1000);
/* Update size, source and destination pointers */
- size -= length;
- dest += length;
- src += length;
- }
+ size -= length;
+ dest += length;
+ src += length;
+ }
- while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
+ while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
/* program dataflash page */
if(!AT91F_DataFlashPagePgmBuf(pDataFlash, src, dest, pDataFlash->pDevice->pages_size ))
return DATAFLASH_ERROR;
@@ -451,20 +447,20 @@
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, 1000);
/* Update size, source and destination pointers */
- size -= pDataFlash->pDevice->pages_size ;
- dest += pDataFlash->pDevice->pages_size ;
- src += pDataFlash->pDevice->pages_size ;
- }
+ size -= pDataFlash->pDevice->pages_size ;
+ dest += pDataFlash->pDevice->pages_size ;
+ src += pDataFlash->pDevice->pages_size ;
+ }
- /* If still some bytes to read */
- if ( size > 0 ) {
+ /* If still some bytes to read */
+ if ( size > 0 ) {
/* program dataflash page */
if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
return DATAFLASH_ERROR;
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, 1000);
}
- return DATAFLASH_OK;
+ return DATAFLASH_OK;
}
@@ -501,7 +497,7 @@
buffer += SizeToRead;
}
- return DATAFLASH_OK;
+ return DATAFLASH_OK;
}
@@ -514,8 +510,8 @@
int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
{
AT91F_SpiEnable(cs);
- AT91F_DataFlashGetStatus(pDesc);
- return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
+ AT91F_DataFlashGetStatus(pDesc);
+ return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
}
#endif
diff --git a/cpu/at91rm9200/at91rm9200_ether.c b/cpu/at91rm9200/at91rm9200_ether.c
index 6e44150..47b57da 100644
--- a/cpu/at91rm9200/at91rm9200_ether.c
+++ b/cpu/at91rm9200/at91rm9200_ether.c
@@ -69,15 +69,15 @@
/** functions to interface the DAVICOM 10/100Mbps ethernet phy **********/
/*
- * Name:
+ * Name:
* dm9161_IsPhyConnected
- * Description:
+ * Description:
* Reads the 2 PHY ID registers
- * Arguments:
+ * Arguments:
* p_mac - pointer to AT91S_EMAC struct
- * Return value:
+ * Return value:
* TRUE - if id read successfully
- * FALSE- if error
+ * FALSE- if error
*/
static unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
{
@@ -96,14 +96,14 @@
}
/*
- * Name:
+ * Name:
* dm9161_GetLinkSpeed
- * Description:
- * Link parallel detection status of MAC is checked and set in the
+ * Description:
+ * Link parallel detection status of MAC is checked and set in the
* MAC configuration registers
- * Arguments:
- * p_mac - pointer to MAC
- * Return value:
+ * Arguments:
+ * p_mac - pointer to MAC
+ * Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
@@ -152,14 +152,14 @@
/*
- * Name:
+ * Name:
* dm9161_InitPhy
- * Description:
- * MAC starts checking its link by using parallel detection and
+ * Description:
+ * MAC starts checking its link by using parallel detection and
* Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
+ * Arguments:
* p_mac - pointer to struct AT91S_EMAC
- * Return value:
+ * Return value:
* TRUE - if link status set succesfully
* FALSE - if link status not set
*/
@@ -188,14 +188,14 @@
/*
- * Name:
+ * Name:
* dm9161_AutoNegotiate
- * Description:
- * MAC Autonegotiates with the partner status of same is set in the
+ * Description:
+ * MAC Autonegotiates with the partner status of same is set in the
* MAC configuration registers
- * Arguments:
+ * Arguments:
* dev - pointer to struct net_device
- * Return value:
+ * Return value:
* TRUE - if link status set successfully
* FALSE - if link status not set
*/
@@ -259,17 +259,15 @@
}
-
-
/*********** EMAC Phy layer Management functions *************************/
/*
- * Name:
+ * Name:
* at91rm9200_EmacEnableMDIO
- * Description:
+ * Description:
* Enables the MDIO bit in MAC control register
- * Arguments:
+ * Arguments:
* p_mac - pointer to struct AT91S_EMAC
- * Return value:
+ * Return value:
* none
*/
static void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
@@ -279,13 +277,13 @@
}
/*
- * Name:
+ * Name:
* at91rm9200_EmacDisableMDIO
- * Description:
+ * Description:
* Disables the MDIO bit in MAC control register
- * Arguments:
+ * Arguments:
* p_mac - pointer to struct AT91S_EMAC
- * Return value:
+ * Return value:
* none
*/
static void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
@@ -296,15 +294,15 @@
/*
- * Name:
+ * Name:
* at91rm9200_EmacReadPhy
- * Description:
+ * Description:
* Reads data from the PHY register
- * Arguments:
+ * Arguments:
* dev - pointer to struct net_device
* RegisterAddress - unsigned char
- * pInput - pointer to value read from register
- * Return value:
+ * pInput - pointer to value read from register
+ * Return value:
* TRUE - if data read successfully
*/
static UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
@@ -324,15 +322,15 @@
/*
- * Name:
+ * Name:
* at91rm9200_EmacWritePhy
- * Description:
+ * Description:
* Writes data to the PHY register
- * Arguments:
+ * Arguments:
* dev - pointer to struct net_device
* RegisterAddress - unsigned char
- * pOutput - pointer to value to be written in the register
- * Return value:
+ * pOutput - pointer to value to be written in the register
+ * Return value:
* TRUE - if data read successfully
*/
static UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
@@ -349,13 +347,13 @@
}
/*
- * Name:
+ * Name:
* at91rm92000_GetPhyInterface
- * Description:
- * Initialise the interface functions to the PHY
- * Arguments:
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
* None
- * Return value:
+ * Return value:
* None
*/
void at91rm92000_GetPhyInterface (void)
diff --git a/cpu/at91rm9200/cpu.c b/cpu/at91rm9200/cpu.c
index ad3cd13..262ca34 100644
--- a/cpu/at91rm9200/cpu.c
+++ b/cpu/at91rm9200/cpu.c
@@ -54,7 +54,7 @@
{
/*printf("write %08lx to p15/c1\n", value); */
__asm__ __volatile__(
- "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
: "=r" (value)
:
: "memory");
@@ -86,7 +86,7 @@
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_end +
- CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+ CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
_armboot_real_end = FIQ_STACK_START + 4;
#else
diff --git a/cpu/at91rm9200/interrupts.c b/cpu/at91rm9200/interrupts.c
index d9c7c55..407df9c 100644
--- a/cpu/at91rm9200/interrupts.c
+++ b/cpu/at91rm9200/interrupts.c
@@ -45,7 +45,6 @@
AT91PS_TC tmr;
-
void enable_interrupts (void)
{
return;
@@ -209,11 +208,11 @@
ulong now = READ_TIMER;
if (now >= lastinc)
{
- /* normal mode */
- timestamp += now - lastinc;
+ /* normal mode */
+ timestamp += now - lastinc;
} else {
- /* we have an overflow ... */
- timestamp += now + TIMER_LOAD_VAL - lastinc;
+ /* we have an overflow ... */
+ timestamp += now + TIMER_LOAD_VAL - lastinc;
}
lastinc = now;
@@ -233,5 +232,3 @@
while(get_timer_masked() < tmo);
/*NOP*/;
}
-
-
diff --git a/cpu/at91rm9200/start.S b/cpu/at91rm9200/start.S
index 9b3e7aa..e955d43 100644
--- a/cpu/at91rm9200/start.S
+++ b/cpu/at91rm9200/start.S
@@ -24,7 +24,6 @@
*/
-
#include "config.h"
#include "version.h"
@@ -124,12 +123,12 @@
reset:
/*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0x13
- msr cpsr,r0
+ * set the cpu to SVC32 mode
+ */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0x13
+ msr cpsr,r0
/*
* relocate exeception table
@@ -144,18 +143,18 @@
bne copyex
/*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
#ifdef CONFIG_INIT_CRITICAL
- bl cpu_init_crit
+ bl cpu_init_crit
#endif
- /* set up the stack */
- ldr r0, _armboot_end
- add r0, r0, #CONFIG_STACKSIZE
- sub sp, r0, #12 /* leave 3 words for abort-stack */
- ldr pc,_start_armboot
+ /* set up the stack */
+ ldr r0, _armboot_end
+ add r0, r0, #CONFIG_STACKSIZE
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+ ldr pc,_start_armboot
_start_armboot: .word start_armboot
@@ -172,8 +171,6 @@
mov pc, lr
-
-
/*
*************************************************************************
*
diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile
index 7067a06..c44412a 100644
--- a/cpu/i386/Makefile
+++ b/cpu/i386/Makefile
@@ -25,10 +25,10 @@
LIB = lib$(CPU).a
-START = start.o start16.o reset.o
-COBJS = serial.o interrupts.o cpu.o timer.o sc520.o
+START = start.o start16.o reset.o
+COBJS = serial.o interrupts.o cpu.o timer.o sc520.o
AOBJS = sc520_asm.o
-
+
all: .depend $(START) $(LIB)
$(LIB): $(COBJS) $(AOBJS)
diff --git a/cpu/i386/config.mk b/cpu/i386/config.mk
index c7cf151..16a160d 100644
--- a/cpu/i386/config.mk
+++ b/cpu/i386/config.mk
@@ -21,6 +21,6 @@
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS +=
+PLATFORM_RELFLAGS +=
PLATFORM_CPPFLAGS += -march=i386 -Werror
diff --git a/cpu/i386/cpu.c b/cpu/i386/cpu.c
index 3c67c12..f24e4ba 100644
--- a/cpu/i386/cpu.c
+++ b/cpu/i386/cpu.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
- *
+ *
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
@@ -40,11 +40,11 @@
{
/* initialize FPU, reset EM, set MP and NE */
asm ("fninit\n" \
- "movl %cr0, %eax\n" \
- "andl $~0x4, %eax\n" \
- "orl $0x22, %eax\n" \
- "movl %eax, %cr0\n" );
-
+ "movl %cr0, %eax\n" \
+ "andl $~0x4, %eax\n" \
+ "orl $0x22, %eax\n" \
+ "movl %eax, %cr0\n" );
+
return 0;
}
@@ -66,4 +66,3 @@
asm("wbinvd\n");
return;
}
-
diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c
index 614d408..84825ae 100644
--- a/cpu/i386/interrupts.c
+++ b/cpu/i386/interrupts.c
@@ -29,7 +29,6 @@
#include <asm/ibmpc.h>
-
struct idt_entry {
u16 base_low;
u16 selector;
@@ -44,7 +43,7 @@
#define MAX_IRQ 16
-typedef struct irq_handler {
+typedef struct irq_handler {
struct irq_handler *next;
interrupt_handler_t* isr_func;
void *isr_data;
@@ -60,27 +59,26 @@
static irq_desc_t irq_table[MAX_IRQ];
-
asm(".globl syscall_entry\n" \
- "syscall_entry:\n" \
- "popl %ebx\n" /* throw away the return address, flags */ \
- "popl %ebx\n" /* and segment that the INT instruction pushed */ \
- "popl %ebx\n" /* on to the stack */ \
- "movl %eax, %ecx\n" /* load the syscall nr argument*/ \
- "movl syscall_tbl, %eax\n" /* load start of syscall table */ \
- "cmpl $(11-1), %ecx\n" /* FixMe: find a way to use NR_SYSCALLS macro here */ \
- "ja bad_syscall\n" \
- "movl (%eax, %ecx, 4), %eax\n" /* load the handler of the syscall*/ \
- "test %eax, %eax\n" /* test for null */ \
- "je bad_syscall\n" \
- "popl %ecx\n" \
- "popl %ebx\n" \
- "sti \n" \
- "jmp *%eax\n" \
+ "syscall_entry:\n" \
+ "popl %ebx\n" /* throw away the return address, flags */ \
+ "popl %ebx\n" /* and segment that the INT instruction pushed */ \
+ "popl %ebx\n" /* on to the stack */ \
+ "movl %eax, %ecx\n" /* load the syscall nr argument*/ \
+ "movl syscall_tbl, %eax\n" /* load start of syscall table */ \
+ "cmpl $(11-1), %ecx\n" /* FixMe: find a way to use NR_SYSCALLS macro here */ \
+ "ja bad_syscall\n" \
+ "movl (%eax, %ecx, 4), %eax\n" /* load the handler of the syscall*/ \
+ "test %eax, %eax\n" /* test for null */ \
+ "je bad_syscall\n" \
+ "popl %ecx\n" \
+ "popl %ebx\n" \
+ "sti \n" \
+ "jmp *%eax\n" \
"bad_syscall: movl $0xffffffff, %eax\n" \
- "popl %ecx\n" \
- "popl %ebx\n" \
- "ret");
+ "popl %ecx\n" \
+ "popl %ebx\n" \
+ "ret");
void __attribute__ ((regparm(0))) syscall_entry(void);
@@ -104,7 +102,7 @@
"pusha \n" \
"pushl $"#x"\n" \
"pushl $irq_return\n" \
- "jmp do_irq\n"); \
+ "jmp do_irq\n"); \
void __attribute__ ((regparm(0))) irq_##x(void)
#define DECLARE_EXCEPTION(x, f) \
@@ -173,20 +171,20 @@
DECLARE_INTERRUPT(13);
DECLARE_INTERRUPT(14);
DECLARE_INTERRUPT(15);
-
-void __attribute__ ((regparm(0))) default_isr(void);
+
+void __attribute__ ((regparm(0))) default_isr(void);
asm ("default_isr: iret\n");
-void disable_irq(int irq)
+void disable_irq(int irq)
{
if (irq >= MAX_IRQ) {
return;
}
irq_table[irq].status |= IRQ_DISABLED;
-
+
}
-void enable_irq(int irq)
+void enable_irq(int irq)
{
if (irq >= MAX_IRQ) {
return;
@@ -198,7 +196,7 @@
static void unmask_irq(int irq)
{
int imr_port;
-
+
if (irq >= MAX_IRQ) {
return;
}
@@ -207,7 +205,7 @@
} else {
imr_port = MASTER_PIC + IMR;
}
-
+
outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
}
@@ -216,7 +214,7 @@
static void mask_irq(int irq)
{
int imr_port;
-
+
if (irq >= MAX_IRQ) {
return;
}
@@ -225,8 +223,8 @@
} else {
imr_port = MASTER_PIC + IMR;
}
-
- outb(inb(imr_port)|(1<<(irq&7)), imr_port);
+
+ outb(inb(imr_port)|(1<<(irq&7)), imr_port);
}
@@ -238,110 +236,110 @@
if (irq > 7) {
outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
irq = SEOI_IR2; /* also do IR2 on master */
- }
+ }
outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
}
-void __attribute__ ((regparm(0))) do_irq(int irq)
+void __attribute__ ((regparm(0))) do_irq(int irq)
{
-
+
mask_irq(irq);
-
+
if (irq_table[irq].status & IRQ_DISABLED) {
unmask_irq(irq);
specific_eoi(irq);
return;
}
-
-
+
+
if (NULL != irq_table[irq].handler) {
irq_handler_t *handler;
- for (handler = irq_table[irq].handler;
+ for (handler = irq_table[irq].handler;
NULL!= handler; handler = handler->next) {
handler->isr_func(handler->isr_data);
}
} else {
- if ((irq & 7) != 7) {
+ if ((irq & 7) != 7) {
printf("Spurious irq %d\n", irq);
}
- }
+ }
unmask_irq(irq);
- specific_eoi(irq);
+ specific_eoi(irq);
}
-void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
{
printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
}
-void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
{
printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
while(1);
}
-void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
{
printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
}
-void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
{
printf("NMI Interrupt at %04x:%08x\n", seg, ip);
}
-
-void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
+
+void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
{
printf("Invalid Instruction at %04x:%08x\n", seg, ip);
while(1);
}
-
-void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
+
+void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
{
printf("Double fault at %04x:%08x\n", seg, ip);
while(1);
}
-void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
{
printf("Invalid TSS at %04x:%08x\n", seg, ip);
}
-
-void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
+
+void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
{
printf("Segmentation fault at %04x:%08x\n", seg, ip);
while(1);
}
-void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
{
printf("Stack fault at %04x:%08x\n", seg, ip);
while(1);
}
-void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
{
printf("General protection fault at %04x:%08x\n", seg, ip);
}
-void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
{
printf("Page fault at %04x:%08x\n", seg, ip);
while(1);
}
-void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
{
printf("Floating point exception at %04x:%08x\n", seg, ip);
}
-void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
+void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
{
printf("Alignment check at %04x:%08x\n", seg, ip);
}
-
-void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
+
+void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
{
printf("Machine check exception at %04x:%08x\n", seg, ip);
}
@@ -350,31 +348,31 @@
void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
{
int status;
-
+
if (ino>MAX_IRQ) {
return;
}
-
+
if (NULL != irq_table[ino].handler) {
return;
}
-
+
status = disable_interrupts();
irq_table[ino].handler = malloc(sizeof(irq_handler_t));
if (NULL == irq_table[ino].handler) {
return;
}
-
+
memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
-
+
irq_table[ino].handler->isr_func = func;
irq_table[ino].handler->isr_data = pdata;
if (status) {
enable_interrupts();
}
-
+
unmask_irq(ino);
-
+
return;
}
@@ -384,7 +382,7 @@
if (ino>MAX_IRQ) {
return;
}
-
+
status = disable_interrupts();
mask_irq(ino);
if (NULL == irq_table[ino].handler) {
@@ -406,33 +404,33 @@
static void set_vector(int intnum, void *routine)
{
- idt[intnum].base_high = (u16)((u32)(routine)>>16);
- idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
+ idt[intnum].base_high = (u16)((u32)(routine)>>16);
+ idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
}
int interrupt_init(void)
{
int i;
-
+
/* Just in case... */
disable_interrupts();
-
+
/* Initialize the IDT and stuff */
-
-
+
+
memset(irq_table, 0, sizeof(irq_table));
/* Setup the IDT */
- for (i=0;i<256;i++) {
+ for (i=0;i<256;i++) {
idt[i].access = 0x8e;
- idt[i].res = 0;
- idt[i].selector = 0x10;
+ idt[i].res = 0;
+ idt[i].selector = 0x10;
set_vector(i, default_isr);
- }
-
+ }
+
asm ("cs lidt idt_ptr\n");
-
+
/* Setup exceptions */
set_vector(0x00, exp_0);
set_vector(0x01, exp_1);
@@ -487,39 +485,39 @@
/* vectors 0x30-0x3f are reserved for irq 16-31 */
set_vector(0x40, syscall_entry);
-
+
/* Mask all interrupts */
outb(0xff, MASTER_PIC + IMR);
outb(0xff, SLAVE_PIC + IMR);
-
+
/* Master PIC */
- outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
+ outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
outb(0x20, MASTER_PIC + ICW2); /* Place master PIC interrupts at INT20 */
- outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */
+ outb(IR2, MASTER_PIC + ICW3); /* ICW3, One slevc PIC is present */
outb(ICW4_PM, MASTER_PIC + ICW4);
-
+
for (i=0;i<8;i++) {
outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
}
-
+
/* Slave PIC */
- outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
+ outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
outb(0x28, SLAVE_PIC + ICW2); /* Place slave PIC interrupts at INT28 */
outb(0x02, SLAVE_PIC + ICW3); /* Slave ID */
- outb(ICW4_PM, SLAVE_PIC + ICW4);
-
+ outb(ICW4_PM, SLAVE_PIC + ICW4);
+
for (i=0;i<8;i++) {
outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
}
-
-
+
+
/* enable cascade interrerupt */
outb(0xfb, MASTER_PIC + IMR);
outb(0xff, SLAVE_PIC + IMR);
-
+
/* It is now safe to enable interrupts */
- enable_interrupts();
-
+ enable_interrupts();
+
return 0;
}
@@ -531,9 +529,9 @@
int disable_interrupts(void)
{
long flags;
-
+
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
-
+
return (flags&0x200); /* IE flags is bit 9 */
}
@@ -541,9 +539,9 @@
#ifdef CFG_RESET_GENERIC
void __attribute__ ((regparm(0))) generate_gpf(void);
-asm(".globl generate_gpf\n"
- "generate_gpf:\n"
- "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
+asm(".globl generate_gpf\n"
+ "generate_gpf:\n"
+ "ljmp $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
* exist */
void reset_cpu(ulong addr)
{
diff --git a/cpu/i386/reset.S b/cpu/i386/reset.S
index 57e32a8..07a7384 100644
--- a/cpu/i386/reset.S
+++ b/cpu/i386/reset.S
@@ -1,5 +1,5 @@
/*
- * U-boot - i386 Startup Code
+ * U-boot - i386 Startup Code
*
* Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
*
@@ -28,11 +28,10 @@
.section .reset, "ax"
.code16
-reset_vector:
- cli
- cld
- jmp start16
+reset_vector:
+ cli
+ cld
+ jmp start16
.org 0xf
nop
-
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 500089a..689e775 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -36,26 +36,26 @@
#include <asm/pci.h>
#include <asm/ic/sc520.h>
-/*
- * utility functions for boards based on the AMD sc520
- *
+/*
+ * utility functions for boards based on the AMD sc520
+ *
* void write_mmcr_byte(u16 mmcr, u8 data)
* void write_mmcr_word(u16 mmcr, u16 data)
* void write_mmcr_long(u16 mmcr, u32 data)
- *
+ *
* u8 read_mmcr_byte(u16 mmcr)
* u16 read_mmcr_word(u16 mmcr)
* u32 read_mmcr_long(u16 mmcr)
- *
+ *
* void init_sc520(void)
* unsigned long init_sc520_dram(void)
* void pci_sc520_init(struct pci_controller *hose)
- *
+ *
* void reset_timer(void)
* ulong get_timer(ulong base)
* void set_timer(ulong t)
* void udelay(unsigned long usec)
- *
+ *
*/
static u32 mmcr_base= 0xfffef000;
@@ -67,7 +67,7 @@
void write_mmcr_word(u16 mmcr, u16 data)
{
- writew(data, mmcr+mmcr_base);
+ writew(data, mmcr+mmcr_base);
}
void write_mmcr_long(u16 mmcr, u32 data)
@@ -82,7 +82,7 @@
u16 read_mmcr_word(u16 mmcr)
{
- return readw(mmcr+mmcr_base);
+ return readw(mmcr+mmcr_base);
}
u32 read_mmcr_long(u16 mmcr)
@@ -94,19 +94,19 @@
void init_sc520(void)
{
DECLARE_GLOBAL_DATA_PTR;
-
+
/* Set the UARTxCTL register at it's slower,
- * baud clock giving us a 1.8432 MHz reference
+ * baud clock giving us a 1.8432 MHz reference
*/
write_mmcr_byte(SC520_UART1CTL, 7);
write_mmcr_byte(SC520_UART2CTL, 7);
-
+
/* first set the timer pin mapping */
write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
-
+
/* enable PCI bus arbitrer */
write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
-
+
write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
@@ -120,10 +120,10 @@
printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000;
}
-
+
/* wait at least one millisecond */
- asm("movl $0x2000,%%ecx\n"
+ asm("movl $0x2000,%%ecx\n"
"wait_loop: pushl %%ecx\n"
"popl %%ecx\n"
"loop wait_loop\n": : : "ecx");
@@ -141,19 +141,19 @@
{
DECLARE_GLOBAL_DATA_PTR;
bd_t *bd = gd->bd;
-
+
u32 dram_present=0;
u32 dram_ctrl;
int val;
-
- int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
- int refresh_rate = CFG_SDRAM_REFRESH_RATE;
+
+ int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
+ int refresh_rate = CFG_SDRAM_REFRESH_RATE;
int ras_cas_delay = CFG_SDRAM_RAS_CAS_DELAY;
-
+
/* set SDRAM speed here */
-
- refresh_rate/=78;
+
+ refresh_rate/=78;
if (refresh_rate<=1) {
val = 0; /* 7.8us */
} else if (refresh_rate==2) {
@@ -164,22 +164,22 @@
val = 3; /* 62.4us */
}
write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
-
+
val = read_mmcr_byte(SC520_DRCTMCTL);
val &= 0xf0;
-
- if (cas_precharge_delay==3) {
+
+ if (cas_precharge_delay==3) {
val |= 0x04; /* 3T */
- } else if (cas_precharge_delay==4) {
+ } else if (cas_precharge_delay==4) {
val |= 0x08; /* 4T */
- } else if (cas_precharge_delay>4) {
+ } else if (cas_precharge_delay>4) {
val |= 0x0c;
- }
-
+ }
+
if (ras_cas_delay > 3) {
- val |= 2;
+ val |= 2;
} else {
- val |= 1;
+ val |= 1;
}
write_mmcr_byte(SC520_DRCTMCTL, val);
@@ -187,37 +187,37 @@
/* We read-back the configuration of the dram
* controller that the assembly code wrote */
dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
-
+
bd->bi_dram[0].start = 0;
if (dram_ctrl & 0x80) {
/* bank 0 enabled */
dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
- bd->bi_dram[0].size = bd->bi_dram[1].start;
+ bd->bi_dram[0].size = bd->bi_dram[1].start;
} else {
bd->bi_dram[0].size = 0;
bd->bi_dram[1].start = bd->bi_dram[0].start;
}
-
+
if (dram_ctrl & 0x8000) {
/* bank 1 enabled */
dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
- bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
+ bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
} else {
bd->bi_dram[1].size = 0;
bd->bi_dram[2].start = bd->bi_dram[1].start;
}
-
+
if (dram_ctrl & 0x800000) {
/* bank 2 enabled */
dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
- bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
+ bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
} else {
bd->bi_dram[2].size = 0;
bd->bi_dram[3].start = bd->bi_dram[2].start;
- }
-
+ }
+
if (dram_ctrl & 0x80000000) {
/* bank 3 enabled */
dram_present = (dram_ctrl & 0x7f000000) >> 2;
@@ -226,12 +226,12 @@
bd->bi_dram[3].size = 0;
}
-
-#if 0
+
+#if 0
printf("Configured %d bytes of dram\n", dram_present);
-#endif
+#endif
gd->ram_size = dram_present;
-
+
return dram_present;
}
@@ -265,19 +265,19 @@
/* The interrupt used for PCI INTA-INTD */
-int sc520_pci_ints[15] = {
+int sc520_pci_ints[15] = {
-1, -1, -1, -1, -1, -1, -1, -1,
-1, -1, -1, -1, -1, -1, -1
};
/* utility function to configure a pci interrupt */
-int pci_sc520_set_irq(int pci_pin, int irq)
+int pci_sc520_set_irq(int pci_pin, int irq)
{
int i;
-
+
# if 0
printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
-#endif
+#endif
if (irq < 0 || irq > 15) {
return -1; /* illegal irq */
}
@@ -286,7 +286,7 @@
return -1; /* illegal pci int pin */
}
- /* first disable any non-pci interrupt source that use
+ /* first disable any non-pci interrupt source that use
* this level */
for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
@@ -296,31 +296,31 @@
write_mmcr_byte(i, SC520_IRQ_DISABLED);
}
}
-
+
/* Set the trigger to level */
- write_mmcr_byte(sc520_irq[irq].level_reg,
+ write_mmcr_byte(sc520_irq[irq].level_reg,
read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
-
-
+
+
if (pci_pin < 4) {
/* PCI INTA-INTD */
/* route the interrupt */
write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
-
-
+
+
} else {
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
-
+
/* also set the polarity in this case */
- write_mmcr_word(SC520_INTPINPOL,
+ write_mmcr_word(SC520_INTPINPOL,
read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
-
+
}
-
- /* register the pin */
+
+ /* register the pin */
sc520_pci_ints[pci_pin] = irq;
-
+
return 0; /* OK */
}
@@ -331,35 +331,35 @@
hose->last_busno = 0xff;
/* System memory space */
- pci_set_region(hose->regions + 0,
+ pci_set_region(hose->regions + 0,
SC520_PCI_MEMORY_BUS,
SC520_PCI_MEMORY_PHYS,
SC520_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
- pci_set_region(hose->regions + 1,
+ pci_set_region(hose->regions + 1,
SC520_PCI_MEM_BUS,
SC520_PCI_MEM_PHYS,
SC520_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* ISA/PCI memory space */
- pci_set_region(hose->regions + 2,
+ pci_set_region(hose->regions + 2,
SC520_ISA_MEM_BUS,
SC520_ISA_MEM_PHYS,
SC520_ISA_MEM_SIZE,
PCI_REGION_MEM);
/* PCI I/O space */
- pci_set_region(hose->regions + 3,
+ pci_set_region(hose->regions + 3,
SC520_PCI_IO_BUS,
SC520_PCI_IO_PHYS,
SC520_PCI_IO_SIZE,
PCI_REGION_IO);
/* ISA/PCI I/O space */
- pci_set_region(hose->regions + 4,
+ pci_set_region(hose->regions + 4,
SC520_ISA_IO_BUS,
SC520_ISA_IO_PHYS,
SC520_ISA_IO_SIZE,
@@ -374,15 +374,14 @@
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
-
+
/* enable target memory acceses on host brige */
- pci_write_config_word(0, PCI_COMMAND,
+ pci_write_config_word(0, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
-
#endif
#ifdef CFG_TIMER_SC520
@@ -392,7 +391,7 @@
{
write_mmcr_word(SC520_GPTMR0CNT, 0);
write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
-
+
}
ulong get_timer(ulong base)
@@ -414,19 +413,19 @@
{
int m=0;
long u;
-
+
read_mmcr_word(SC520_SWTMRMILLI);
read_mmcr_word(SC520_SWTMRMICRO);
-
+
#if 0
/* do not enable this line, udelay is used in the serial driver -> recursion */
printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
-#endif
+#endif
while (1) {
-
+
m += read_mmcr_word(SC520_SWTMRMILLI);
u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
-
+
if (usec <= u) {
break;
}
@@ -440,13 +439,13 @@
u8 temp=0;
if (freq >= 8192) {
- temp |= CTL_CLK_SEL_4;
+ temp |= CTL_CLK_SEL_4;
} else if (freq >= 4096) {
- temp |= CTL_CLK_SEL_8;
+ temp |= CTL_CLK_SEL_8;
} else if (freq >= 2048) {
- temp |= CTL_CLK_SEL_16;
+ temp |= CTL_CLK_SEL_16;
} else if (freq >= 1024) {
- temp |= CTL_CLK_SEL_32;
+ temp |= CTL_CLK_SEL_32;
} else if (freq >= 512) {
temp |= CTL_CLK_SEL_64;
} else if (freq >= 256) {
@@ -456,47 +455,47 @@
} else {
temp |= CTL_CLK_SEL_512;
}
-
+
if (!lsb_first) {
temp |= MSBF_ENB;
}
-
+
if (inv_clock) {
temp |= CLK_INV_ENB;
}
-
+
if (inv_phase) {
temp |= PHS_INV_ENB;
}
-
+
write_mmcr_byte(SC520_SSICTL, temp);
-
+
return 0;
}
-u8 ssi_txrx_byte(u8 data)
+u8 ssi_txrx_byte(u8 data)
{
write_mmcr_byte(SC520_SSIXMIT, data);
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
- return read_mmcr_byte(SC520_SSIRCV);
-}
+ return read_mmcr_byte(SC520_SSIRCV);
+}
-void ssi_tx_byte(u8 data)
+void ssi_tx_byte(u8 data)
{
write_mmcr_byte(SC520_SSIXMIT, data);
- while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
+ while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
}
-u8 ssi_rx_byte(void)
+u8 ssi_rx_byte(void)
{
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
return read_mmcr_byte(SC520_SSIRCV);
-}
+}
#endif /* CONFIG_SC520 */
diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index 7a957c7..80464fa 100644
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -22,21 +22,21 @@
*/
/* This file is largely based on code obtned from AMD. AMD's original
- * copyright is included below
+ * copyright is included below
*/
/*
* =============================================================================
- *
- * Copyright 1999 Advanced Micro Devices, Inc.
- *
- * This software is the property of Advanced Micro Devices, Inc (AMD) which
- * specifically grants the user the right to modify, use and distribute this
- * software provided this COPYRIGHT NOTICE is not removed or altered. All
- * other rights are reserved by AMD.
- *
- * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
- * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
+ *
+ * Copyright 1999 Advanced Micro Devices, Inc.
+ *
+ * This software is the property of Advanced Micro Devices, Inc (AMD) which
+ * specifically grants the user the right to modify, use and distribute this
+ * software provided this COPYRIGHT NOTICE is not removed or altered. All
+ * other rights are reserved by AMD.
+ *
+ * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
+ * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
* THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
* IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
* (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
@@ -45,19 +45,19 @@
* SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
* LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
* LIMITATION MAY NOT APPLY TO YOU.
- *
+ *
* AMD does not assume any responsibility for any errors that may appear in
* the Materials nor any responsibility to support or update the Materials.
* AMD retains the right to make changes to its test specifications at any
* time, without notice.
- *
- * So that all may benefit from your experience, please report any problems
- * or suggestions about this software back to AMD. Please include your name,
- * company, telephone number, AMD product requiring support and question or
- * problem encountered.
- *
- * Advanced Micro Devices, Inc. Worldwide support and contact
- * Embedded Processor Division information available at:
+ *
+ * So that all may benefit from your experience, please report any problems
+ * or suggestions about this software back to AMD. Please include your name,
+ * company, telephone number, AMD product requiring support and question or
+ * problem encountered.
+ *
+ * Advanced Micro Devices, Inc. Worldwide support and contact
+ * Embedded Processor Division information available at:
* Systems Engineering epd.support@amd.com
* 5204 E. Ben White Blvd. -or-
* Austin, TX 78741 http://www.amd.com/html/support/techsup.html
@@ -66,7 +66,7 @@
/*******************************************************************************
- * AUTHOR : Buddy Fey - Original.
+ * AUTHOR : Buddy Fey - Original.
*******************************************************************************
*/
@@ -140,368 +140,368 @@
* initialize dram controller registers
*/
.globl mem_init
-mem_init:
- xorw %ax,%ax
- movl $DBCTL, %edi
+mem_init:
+ xorw %ax,%ax
+ movl $DBCTL, %edi
movb %al, (%edi) /* disable write buffer */
- movl $ECCCTL, %edi
+ movl $ECCCTL, %edi
movb %al, (%edi) /* disable ECC */
- movl $DRCTMCTL, %edi
- movb $0x1E,%al /* Set SDRAM timing for slowest */
+ movl $DRCTMCTL, %edi
+ movb $0x1E,%al /* Set SDRAM timing for slowest */
movb %al, (%edi)
/*
* setup loop to do 4 external banks starting with bank 3
*/
- movl $0xff000000,%eax /* enable last bank and setup */
- movl $DRCBENDADR, %edi /* ending address register */
+ movl $0xff000000,%eax /* enable last bank and setup */
+ movl $DRCBENDADR, %edi /* ending address register */
movl %eax, (%edi)
- movl $DRCCFG, %edi /* setup */
- movw $0xbbbb,%ax /* dram config register for */
+ movl $DRCCFG, %edi /* setup */
+ movw $0xbbbb,%ax /* dram config register for */
movw %ax, (%edi)
/*
* issue a NOP to all DRAMs
*/
- movl $DRCCTL, %edi /* setup DRAM control register with */
- movb $0x1,%al /* Disable refresh,disable write buffer */
+ movl $DRCCTL, %edi /* setup DRAM control register with */
+ movb $0x1,%al /* Disable refresh,disable write buffer */
movb %al, (%edi)
- movl $CACHELINESZ, %esi /* just a dummy address to write for */
+ movl $CACHELINESZ, %esi /* just a dummy address to write for */
movw %ax, (%esi)
/*
* delay for 100 usec? 200?
* ******this is a cludge for now *************
*/
- movw $100,%cx
-sizdelay:
- loop sizdelay /* we need 100 usec here */
+ movw $100,%cx
+sizdelay:
+ loop sizdelay /* we need 100 usec here */
/***********************************************/
/*
* issue all banks precharge
*/
- movb $0x2,%al /* All banks precharge */
+ movb $0x2,%al /* All banks precharge */
movb %al, (%edi)
movw %ax, (%esi)
/*
- * issue 2 auto refreshes to all banks
+ * issue 2 auto refreshes to all banks
*/
- movb $0x4,%al /* Auto refresh cmd */
+ movb $0x4,%al /* Auto refresh cmd */
movb %al, (%edi)
- movw $2,%cx
-refresh1:
+ movw $2,%cx
+refresh1:
movw %ax, (%esi)
- loop refresh1
+ loop refresh1
/*
* issue LOAD MODE REGISTER command
*/
- movb $0x3,%al /* Load mode register cmd */
+ movb $0x3,%al /* Load mode register cmd */
movb %al, (%edi)
movw %ax, (%esi)
/*
- * issue 8 more auto refreshes to all banks
- */
- movb $0x4,%al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $8,%cx
-refresh2:
- movw %ax, (%esi)
- loop refresh2
-
- /*
- * set control register to NORMAL mode
+ * issue 8 more auto refreshes to all banks
*/
- movb $0x0,%al /* Normal mode value */
+ movb $0x4,%al /* Auto refresh cmd */
+ movb %al, (%edi)
+ movw $8,%cx
+refresh2:
+ movw %ax, (%esi)
+ loop refresh2
+
+ /*
+ * set control register to NORMAL mode
+ */
+ movb $0x0,%al /* Normal mode value */
movb %al, (%edi)
/*
* size dram starting with external bank 3 moving to external bank 0
*/
- movl $0x3,%ecx /* start with external bank 3 */
+ movl $0x3,%ecx /* start with external bank 3 */
-nextbank:
+nextbank:
/*
* write col 11 wrap adr
*/
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
+ movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
movl %eax, (%esi) /* write max col pattern at max col adr */
movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
* write col 10 wrap adr
*/
- movl $COL10_ADR, %esi /* set address to 10 col wrap address */
- movl $COL10_DATA, %eax /* pattern for 10 col wrap */
+ movl $COL10_ADR, %esi /* set address to 10 col wrap address */
+ movl $COL10_DATA, %eax /* pattern for 10 col wrap */
movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
* write col 9 wrap adr
*/
- movl $COL09_ADR, %esi /* set address to 9 col wrap address */
- movl $COL09_DATA, %eax /* pattern for 9 col wrap */
+ movl $COL09_ADR, %esi /* set address to 9 col wrap address */
+ movl $COL09_DATA, %eax /* pattern for 9 col wrap */
movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
* write col 8 wrap adr
*/
- movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
- movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
+ movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
+ movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
movl %eax, (%esi) /* write min col pattern @ min col adr */
movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
* write row 14 wrap adr
*/
- movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
- movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
+ movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
+ movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
movl %eax, (%esi) /* write max row pattern at max row adr */
movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
* write row 13 wrap adr
*/
- movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
- movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
+ movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
+ movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
* write row 12 wrap adr
*/
- movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
- movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
+ movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
+ movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
movl (%esi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
* write row 11 wrap adr
*/
- movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
- movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
+ movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
+ movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
movl (%edi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
* write row 10 wrap adr --- this write is really to determine number of banks
*/
- movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
- movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
+ movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
+ movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
movl (%edi), %ebx /* optional read */
- cmpl %ebx,%eax /* to verify write */
- jnz bad_ram /* this ram is bad */
+ cmpl %ebx,%eax /* to verify write */
+ jnz bad_ram /* this ram is bad */
/*
- * read data @ row 12 wrap adr to determine * banks,
+ * read data @ row 12 wrap adr to determine * banks,
* and read data @ row 14 wrap adr to determine * rows.
* if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
- * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
+ * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
* if data @ row 12 wrap == 11 or 12, we have 4 banks,
*/
- xorw %di,%di /* value for 2 banks in DI */
- movl (%esi), %ebx /* read from 12 row wrap to check banks
- * (esi is setup from the write to row 12 wrap) */
- cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */
- jz only2 /* if pattern == AA, we only have 2 banks */
+ xorw %di,%di /* value for 2 banks in DI */
+ movl (%esi), %ebx /* read from 12 row wrap to check banks
+ * (esi is setup from the write to row 12 wrap) */
+ cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */
+ jz only2 /* if pattern == AA, we only have 2 banks */
/* 4 banks */
-
- movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */
- cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
- jz only2
- cmpl $ROW12_DATA, %ebx /* and 12 */
- jnz bad_ram /* its bad if not 11 or 12! */
-
+
+ movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */
+ cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
+ jz only2
+ cmpl $ROW12_DATA, %ebx /* and 12 */
+ jnz bad_ram /* its bad if not 11 or 12! */
+
/* fall through */
-only2:
+only2:
/*
* validate row mask
*/
- movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
+ movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
movl (%esi), %eax /* read actual number of rows @ row14 adr */
- cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
- jb bad_ram
+ cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
+ jb bad_ram
- cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
- ja bad_ram
+ cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
+ ja bad_ram
- cmpb %ah,%al /* verify all 4 bytes of dword same */
- jnz bad_ram
- movl %eax,%ebx
- shrl $16,%ebx
- cmpw %bx,%ax
- jnz bad_ram
+ cmpb %ah,%al /* verify all 4 bytes of dword same */
+ jnz bad_ram
+ movl %eax,%ebx
+ shrl $16,%ebx
+ cmpw %bx,%ax
+ jnz bad_ram
/*
* read col 11 wrap adr for real column data value
*/
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
+ movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
movl (%esi), %eax /* read real col number at max col adr */
/*
* validate column data
*/
- cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
- jb bad_ram
+ cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
+ jb bad_ram
- cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
- ja bad_ram
+ cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
+ ja bad_ram
- subl $COL08_DATA, %eax /* normalize column data to zero */
- jc bad_ram
- cmpb %ah,%al /* verify all 4 bytes of dword equal */
- jnz bad_ram
- movl %eax,%edx
- shrl $16,%edx
- cmpw %dx,%ax
- jnz bad_ram
+ subl $COL08_DATA, %eax /* normalize column data to zero */
+ jc bad_ram
+ cmpb %ah,%al /* verify all 4 bytes of dword equal */
+ jnz bad_ram
+ movl %eax,%edx
+ shrl $16,%edx
+ cmpw %dx,%ax
+ jnz bad_ram
/*
* merge bank and col data together
*/
- addw %di,%dx /* merge of bank and col info in dl */
+ addw %di,%dx /* merge of bank and col info in dl */
/*
* fix ending addr mask based upon col info
*/
- movb $3,%al
- subb %dh,%al /* dh contains the overflow from the bank/col merge */
- movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
- xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
- shrb %cl,%dh /* */
- incb %dh /* ending addr is 1 greater than real end */
- xchgw %cx,%ax /* cx is bank number again */
+ movb $3,%al
+ subb %dh,%al /* dh contains the overflow from the bank/col merge */
+ movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
+ xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
+ shrb %cl,%dh /* */
+ incb %dh /* ending addr is 1 greater than real end */
+ xchgw %cx,%ax /* cx is bank number again */
/*
* issue all banks precharge
*/
-bad_reint:
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x2,%al /* All banks precharge */
+bad_reint:
+ movl $DRCCTL, %esi /* setup DRAM control register with */
+ movb $0x2,%al /* All banks precharge */
movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
+ movl $CACHELINESZ, %esi /* address to init read buffer */
movw %ax, (%esi)
/*
* update ENDING ADDRESS REGISTER
*/
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movl %ecx,%ebx
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movl %ecx,%ebx
addl %ebx, %edi
movb %dh, (%edi)
/*
* update CONFIG REGISTER
*/
- xorb %dh,%dh
- movw $0x00f,%bx
- movw %cx,%ax
- shlw $2,%ax
- xchgw %cx,%ax
- shlw %cl,%dx
- shlw %cl,%bx
- notw %bx
- xchgw %cx,%ax
- movl $DRCCFG, %edi
+ xorb %dh,%dh
+ movw $0x00f,%bx
+ movw %cx,%ax
+ shlw $2,%ax
+ xchgw %cx,%ax
+ shlw %cl,%dx
+ shlw %cl,%bx
+ notw %bx
+ xchgw %cx,%ax
+ movl $DRCCFG, %edi
mov (%edi), %ax
- andw %bx,%ax
- orw %dx,%ax
+ andw %bx,%ax
+ orw %dx,%ax
movw %ax, (%edi)
- jcxz cleanup
+ jcxz cleanup
- decw %cx
- movl %ecx,%ebx
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movb $0xff,%al
+ decw %cx
+ movl %ecx,%ebx
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movb $0xff,%al
addl %ebx, %edi
movb %al, (%edi)
/*
- * set control register to NORMAL mode
+ * set control register to NORMAL mode
*/
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x0,%al /* Normal mode value */
+ movl $DRCCTL, %esi /* setup DRAM control register with */
+ movb $0x0,%al /* Normal mode value */
movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
+ movl $CACHELINESZ, %esi /* address to init read buffer */
movw %ax, (%esi)
- jmp nextbank
+ jmp nextbank
-cleanup:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movw $4,%cx
- xorw %ax,%ax
-cleanuplp:
+cleanup:
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+ movw $4,%cx
+ xorw %ax,%ax
+cleanuplp:
movb (%edi), %al
- orb %al,%al
- jz emptybank
+ orb %al,%al
+ jz emptybank
- addb %ah,%al
- jns nottoomuch
+ addb %ah,%al
+ jns nottoomuch
- movb $0x7f,%al
-nottoomuch:
- movb %al,%ah
- orb $0x80,%al
+ movb $0x7f,%al
+nottoomuch:
+ movb %al,%ah
+ orb $0x80,%al
movb %al, (%edi)
-emptybank:
- incl %edi
- loop cleanuplp
+emptybank:
+ incl %edi
+ loop cleanuplp
#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
/* set the CAS latency now since it is hard to do
* when we run from the RAM */
movl $DRCTMCTL, %edi /* DRAM timing register */
- movb (%edi), %al
+ movb (%edi), %al
#ifdef CFG_SDRAM_CAS_LATENCY_2T
andb $0xef, %al
#endif
#ifdef CFG_SDRAM_CAS_LATENCY_3T
orb $0x10, %al
-#endif
+#endif
movb %al, (%edi)
#endif
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x3,%al /* Load mode register cmd */
+ movl $DRCCTL, %edi /* DRAM Control register */
+ movb $0x3,%al /* Load mode register cmd */
movb %al, (%edi)
movw %ax, (%esi)
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x18,%al /* Enable refresh and NORMAL mode */
+ movl $DRCCTL, %edi /* DRAM Control register */
+ movb $0x18,%al /* Enable refresh and NORMAL mode */
movb %al, (%edi)
- jmp dram_done
+ jmp dram_done
-bad_ram:
- xorl %edx,%edx
- xorl %edi,%edi
- jmp bad_reint
+bad_ram:
+ xorl %edx,%edx
+ xorl %edi,%edi
+ jmp bad_reint
-dram_done:
-
+dram_done:
+
/* readback DRCBENDADR and return the number
- * of available ram bytes in %eax */
+ * of available ram bytes in %eax */
- movl $DRCBENDADR, %edi /* DRAM ending address register */
-
+ movl $DRCBENDADR, %edi /* DRAM ending address register */
+
movl (%edi), %eax
movl %eax, %ecx
andl $0x80000000, %ecx
jz bank2
andl $0x7f000000, %eax
- shrl $2, %eax
+ shrl $2, %eax
movl %eax, %ebx
bank2: movl (%edi), %eax
@@ -509,7 +509,7 @@
andl $0x00800000, %ecx
jz bank1
andl $0x007f0000, %eax
- shll $6, %eax
+ shll $6, %eax
movl %eax, %ebx
bank1: movl (%edi), %eax
@@ -517,7 +517,7 @@
andl $0x00008000, %ecx
jz bank0
andl $0x00007f00, %eax
- shll $14, %eax
+ shll $14, %eax
movl %eax, %ebx
bank0: movl (%edi), %eax
@@ -525,7 +525,7 @@
andl $0x00000080, %ecx
jz done
andl $0x0000007f, %eax
- shll $22, %eax
+ shll $22, %eax
movl %eax, %ebx
done: movl %ebx, %eax
diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c
index 22c3c2a..f58b47c 100644
--- a/cpu/i386/serial.c
+++ b/cpu/i386/serial.c
@@ -1,7 +1,7 @@
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se
- *
+ *
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
@@ -81,7 +81,6 @@
#define asyncLSRRxFifoError1 0x80
-
#if CONFIG_SERIAL_SOFTWARE_FIFO
/*-----------------------------------------------------------------------------+
| Fifo
@@ -100,7 +99,7 @@
static int serial_div(int baudrate)
{
-
+
switch (baudrate) {
case 1200:
return 96;
@@ -113,9 +112,9 @@
case 57600:
return 2;
case 115200:
- return 1;
+ return 1;
}
-
+
return 12;
}
@@ -132,7 +131,7 @@
volatile char val;
int bdiv = serial_div(gd->baudrate);
-
+
outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
outb(bdiv, UART0_BASE + UART_DLL); /* set baudrate divisor */
@@ -154,7 +153,7 @@
DECLARE_GLOBAL_DATA_PTR;
unsigned short bdiv;
-
+
bdiv = serial_div(gd->baudrate);
outb(0x80, UART0_BASE + UART_LCR); /* set DLAB bit */
@@ -199,7 +198,7 @@
return serial_buffered_getc();
}
#endif
-
+
while (1) {
#if defined(CONFIG_HW_WATCHDOG)
WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
@@ -262,28 +261,28 @@
} else {
space = buf_info.rx_get - rx_put;
}
-
+
while (inb(UART0_BASE + UART_LSR) & 1) {
c = inb(UART0_BASE);
if (space) {
buf_info.rx_buffer[rx_put++] = c;
space--;
-
+
if (rx_put == buf_info.rx_get) {
buf_info.rx_get++;
if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
buf_info.rx_get = 0;
}
}
-
+
if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
rx_put = 0;
if (0 == buf_info.rx_get) {
buf_info.rx_get = 1;
}
-
+
}
-
+
}
if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
/* Stop flow by setting RTS inactive */
@@ -309,20 +308,20 @@
buf_info.cts = 0;
}
- irq_install_handler ( VECNUM_U0 /*UART0 *//*int vec */ ,
+ irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
serial_isr /*interrupt_handler_t *handler */ ,
(void *) &buf_info /*void *arg */ );
/* Enable "RX Data Available" Interrupt on UART */
/* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */
outb(0x01, UART0_BASE + UART_IER);
-
+
/* Set DTR and RTS active, enable interrupts */
outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR);
-
+
/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
outb( /*(1 << 6) |*/ 1, UART0_BASE + UART_FCR);
-
+
serial_buffer_active = 1;
}
@@ -348,7 +347,7 @@
buf_info.cts = 1;
}
}
-
+
#endif
serial_putc (c);
}
@@ -508,4 +507,3 @@
}
#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
#endif /* CFG_CMD_KGDB */
-
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index 025555c..afcbb24 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -1,5 +1,5 @@
/*
- * U-boot - i386 Startup Code
+ * U-boot - i386 Startup Code
*
* Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
*
@@ -26,71 +26,71 @@
#include <config.h>
#include <version.h>
-
+
.section .text
.code32
.globl _start
-.type _start, @function
+.type _start, @function
.globl _i386boot_start
_i386boot_start:
-_start:
- movl $0x18,%eax /* Load our segement registes, the
- * gdt have already been loaded by start16.S */
- movw %ax,%fs
+_start:
+ movl $0x18,%eax /* Load our segement registes, the
+ * gdt have already been loaded by start16.S */
+ movw %ax,%fs
movw %ax,%ds
- movw %ax,%gs
- movw %ax,%es
- movw %ax,%ss
-
+ movw %ax,%gs
+ movw %ax,%es
+ movw %ax,%ss
+
/* We call a few functions in the board support package
* since we have no stack yet we'll have to use %ebp
* to store the return address */
-
+
/* Early platform init (setup gpio, etc ) */
mov $early_board_init_ret, %ebp
jmp early_board_init
early_board_init_ret:
-
+
/* The __port80 entry-point should be usabe by now */
/* so we try to indicate progress */
- movw $0x01, %ax
+ movw $0x01, %ax
movl $.progress0, %ebp
jmp __show_boot_progress
-.progress0:
+.progress0:
/* size memory */
mov $mem_init_ret, %ebp
- jmp mem_init
+ jmp mem_init
mem_init_ret:
-
- /* check ammount of configured memory
- * (we need atleast bss start+bss size+stack size) */
+
+ /* check ammount of configured memory
+ * (we need atleast bss start+bss size+stack size) */
movl $_i386boot_bss_start, %ecx /* BSS start */
- addl $_i386boot_bss_size, %ecx /* BSS size */
+ addl $_i386boot_bss_size, %ecx /* BSS size */
addl $CFG_STACK_SIZE, %ecx
- cmpl %ecx, %eax
+ cmpl %ecx, %eax
jae mem_ok
-
+
/* indicate (lack of) progress */
- movw $0x81, %ax
+ movw $0x81, %ax
movl $.progress0a, %ebp
jmp __show_boot_progress
-.progress0a:
+.progress0a:
jmp die
-mem_ok:
+mem_ok:
/* indicate progress */
- movw $0x02, %ax
+ movw $0x02, %ax
movl $.progress1, %ebp
jmp __show_boot_progress
-.progress1:
+.progress1:
/* create a stack after the bss */
- movl $_i386boot_bss_start, %eax
+ movl $_i386boot_bss_start, %eax
addl $_i386boot_bss_size, %eax
addl $CFG_STACK_SIZE, %eax
- movl %eax, %esp
-
+ movl %eax, %esp
+
pushl $0
popl %eax
cmpl $0, %eax
@@ -102,83 +102,83 @@
no_stack:
/* indicate (lack of) progress */
- movw $0x82, %ax
+ movw $0x82, %ax
movl $.progress1a, %ebp
jmp __show_boot_progress
-.progress1a:
+.progress1a:
jmp die
-
-
-stack_ok:
+
+
+stack_ok:
/* indicate progress */
- movw $0x03, %ax
+ movw $0x03, %ax
movl $.progress2, %ebp
jmp __show_boot_progress
-.progress2:
+.progress2:
/* copy data section to ram, size must be 4-byte aligned */
movl $_i386boot_romdata_dest, %edi /* destination address */
- movl $_i386boot_romdata_start, %esi /* source address */
+ movl $_i386boot_romdata_start, %esi /* source address */
movl $_i386boot_romdata_size, %ecx /* number of bytes to copy */
movl %ecx, %eax
andl $3, %eax
jnz data_fail
-
+
shrl $2, %ecx /* copy 4 byte each time */
- cld
+ cld
cmpl $0, %ecx
- je data_ok
-data_segment:
- movsl
+ je data_ok
+data_segment:
+ movsl
loop data_segment
jmp data_ok
data_fail:
/* indicate (lack of) progress */
- movw $0x83, %ax
+ movw $0x83, %ax
movl $.progress2a, %ebp
jmp __show_boot_progress
-.progress2a:
+.progress2a:
jmp die
-data_ok:
+data_ok:
/* indicate progress */
- movw $0x04, %ax
+ movw $0x04, %ax
movl $.progress3, %ebp
jmp __show_boot_progress
-.progress3:
+.progress3:
/* clear bss section in ram, size must be 4-byte aligned */
movl $_i386boot_bss_start, %eax /* BSS start */
- movl $_i386boot_bss_size, %ecx /* BSS size */
+ movl $_i386boot_bss_size, %ecx /* BSS size */
movl %ecx, %eax
andl $3, %eax
jnz bss_fail
shrl $2, %ecx /* clear 4 byte each time */
- cld
+ cld
cmpl $0, %ecx
- je bss_ok
-bss:
+ je bss_ok
+bss:
movl $0, (%edi)
- add $4, %edi
+ add $4, %edi
loop bss
jmp bss_ok
bss_fail:
/* indicate (lack of) progress */
- movw $0x84, %ax
+ movw $0x84, %ax
movl $.progress3a, %ebp
jmp __show_boot_progress
-.progress3a:
+.progress3a:
jmp die
-bss_ok:
+bss_ok:
- wbinvd
+ wbinvd
/* indicate progress */
- movw $0x05, %ax
+ movw $0x05, %ax
movl $.progress4, %ebp
jmp __show_boot_progress
.progress4:
@@ -186,13 +186,11 @@
call start_i386boot /* Enter, U-boot! */
/* indicate (lack of) progress */
- movw $0x85, %ax
+ movw $0x85, %ax
movl $.progress4a, %ebp
jmp __show_boot_progress
.progress4a:
die: hlt
jmp die
- hlt
-
-
+ hlt
diff --git a/cpu/i386/start16.S b/cpu/i386/start16.S
index a34642f..239f2ff 100644
--- a/cpu/i386/start16.S
+++ b/cpu/i386/start16.S
@@ -1,5 +1,5 @@
/*
- * U-boot - i386 Startup Code
+ * U-boot - i386 Startup Code
*
* Copyright (c) 2002, 2003 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
*
@@ -30,37 +30,37 @@
.section .start16, "ax"
.code16
.globl start16
-start16:
+start16:
/* First we let the BSP do some early initialization
* this code have to map the flash to its final position
*/
mov $board_init16_ret, %bp
jmp board_init16
-board_init16_ret:
-
+board_init16_ret:
+
/* Turn of cache (this might require a 486-class CPU) */
- movl %cr0, %eax
- orl $0x60000000,%eax
- movl %eax, %cr0
- wbinvd
-
+ movl %cr0, %eax
+ orl $0x60000000,%eax
+ movl %eax, %cr0
+ wbinvd
+
/* load the descriptor tables */
o32 cs lidt idt_ptr
-o32 cs lgdt gdt_ptr
+o32 cs lgdt gdt_ptr
/* Now, we enter protected mode */
- movl %cr0, %eax
- orl $1,%eax
- movl %eax, %cr0
-
+ movl %cr0, %eax
+ orl $1,%eax
+ movl %eax, %cr0
+
/* Flush the prefetch queue */
- jmp ff
+ jmp ff
ff:
/* Finally jump to the 32bit initialization code */
- movw $code32start, %ax
- movw %ax,%bp
+ movw $code32start, %ax
+ movw %ax,%bp
o32 cs ljmp *(%bp)
/* 48-bit far pointer */
@@ -71,17 +71,17 @@
idt_ptr:
.word 0 /* limit */
.long 0 /* base */
-
+
gdt_ptr:
.word 0x30 /* limit (48 bytes = 6 GDT entries) */
.long BOOT_SEG + gdt /* base */
- /* The GDT table ...
+ /* The GDT table ...
*
- * Selector Type
+ * Selector Type
* 0x00 NULL
* 0x08 Unused
- * 0x10 32bit code
+ * 0x10 32bit code
* 0x18 32bit data/stack
* 0x20 16bit code
* 0x28 16bit data/stack
@@ -100,12 +100,12 @@
.word 0x0 /* base address = 0 */
.word 0x9300 /* data read/write */
.word 0x00CF /* granularity = 4096, 386 (+5th nibble of limit) */
-
+
.word 0xFFFF /* 64kb */
.word 0 /* base address = 0 */
.word 0x9b00 /* data read/write */
.word 0x0010 /* granularity = 1 (+5th nibble of limit) */
-
+
.word 0xFFFF /* 64kb */
.word 0 /* base address = 0 */
.word 0x9300 /* data read/write */
diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c
index a23cd6e..486d927 100644
--- a/cpu/i386/timer.c
+++ b/cpu/i386/timer.c
@@ -46,28 +46,28 @@
int timer_init(void)
{
system_ticks = 0;
-
+
irq_install_handler(0, timer_isr, NULL);
-
- /* initialize timer 0 and 2
- *
+
+ /* initialize timer 0 and 2
+ *
* Timer 0 is used to increment system_tick 1000 times/sec
* Timer 1 was used for DRAM refresh in early PC's
* Timer 2 is used to drive the speaker
* (to stasrt a beep: write 3 to port 0x61,
* to stop it again: write 0)
*/
-
- outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND);
+
+ outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND);
outb(TIMER0_VALUE&0xff, PIT_BASE + PIT_T0);
outb(TIMER0_VALUE>>8, PIT_BASE + PIT_T0);
- outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND);
+ outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND);
outb(TIMER2_VALUE&0xff, PIT_BASE + PIT_T2);
outb(TIMER2_VALUE>>8, PIT_BASE + PIT_T2);
timer_init_done = 1;
-
+
return 0;
}
@@ -87,7 +87,7 @@
return (system_ticks - base);
}
-void set_timer (ulong t)
+void set_timer (ulong t)
{
system_ticks = t;
}
@@ -102,20 +102,20 @@
/* this is not very exact */
void udelay (unsigned long usec)
-{
+{
int counter;
int wraps;
-
+
if (!timer_init_done) {
return;
}
counter = read_pit();
wraps = usec/1000;
usec = usec%1000;
-
+
usec*=1194;
usec/=1000;
- usec+=counter;
+ usec+=counter;
if (usec > 1194) {
usec-=1194;
wraps++;
@@ -123,26 +123,26 @@
while (1) {
int new_count = read_pit();
-
+
if (((new_count < usec) && !wraps) || wraps < 0) {
break;
}
-
+
if (new_count > counter) {
wraps--;
}
counter = new_count;
}
-
+
}
#if 0
/* this is a version with debug output */
void _udelay (unsigned long usec)
-{
+{
int counter;
int wraps;
-
+
int usec1, usec2, usec3;
int wraps1, wraps2, wraps3, wraps4;
int ctr1, ctr2, ctr3, nct1, nct2;
@@ -155,13 +155,13 @@
ctr1 = counter;
wraps = usec/1000;
usec = usec%1000;
-
+
usec2 = usec;
wraps1 = wraps;
-
+
usec*=1194;
usec/=1000;
- usec+=counter;
+ usec+=counter;
if (usec > 1194) {
usec-=1194;
wraps++;
@@ -169,7 +169,7 @@
usec3 = usec;
wraps2 = wraps;
-
+
ctr2 = wraps3 = nct1 = 4711;
ctr3 = wraps4 = nct2 = 4711;
i=0;
@@ -179,7 +179,7 @@
if ((new_count < usec && !wraps) || wraps < 0) {
break;
}
-
+
if (new_count > counter) {
wraps--;
}
@@ -192,10 +192,10 @@
wraps4 = wraps;
nct2 = new_count;
}
-
+
counter = new_count;
}
-
+
printf("udelay(%d)\n", usec1);
printf("counter %d\n", ctr1);
printf("1: wraps %d, usec %d\n", wraps1, usec2);
diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 55daa89..01fbb2f 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -150,7 +150,7 @@
sw zero, 28(a0)
addu a0, 32
bltu a0, a1, 2b
-
+
/* Set invalid tag.
*/
@@ -267,4 +267,3 @@
j ra
.end mips_cache_lock
-
diff --git a/cpu/mips/config.mk b/cpu/mips/config.mk
index 4ea6617..1664e14 100644
--- a/cpu/mips/config.mk
+++ b/cpu/mips/config.mk
@@ -22,4 +22,3 @@
#
PLATFORM_CPPFLAGS += -mcpu=4kc -EB -mabicalls
-
diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c
index e9676c1..c27abbd 100644
--- a/cpu/mips/cpu.c
+++ b/cpu/mips/cpu.c
@@ -42,4 +42,3 @@
{
}
-
diff --git a/cpu/mips/incaip_clock.c b/cpu/mips/incaip_clock.c
index 7fc6eb0..27f0609 100644
--- a/cpu/mips/incaip_clock.c
+++ b/cpu/mips/incaip_clock.c
@@ -25,14 +25,13 @@
#include <asm/inca-ip.h>
-
/*******************************************************************************
*
-* get_cpuclk - returns the frequency of the CPU.
+* get_cpuclk - returns the frequency of the CPU.
*
* Gets the value directly from the INCA-IP hardware.
*
-* RETURNS:
+* RETURNS:
* 150.000.000 for 150 MHz
* 130.000.000. for 130 Mhz
* 100.000.000. for 100 Mhz
@@ -55,24 +54,24 @@
else
{
/* MUX I set to 100/133 MHz clock */
- if (*((volatile ulong*)INCA_IP_CGU_CGU_DIVCR) & 0x40)
+ if (*((volatile ulong*)INCA_IP_CGU_CGU_DIVCR) & 0x40)
{
- /* Division value is 1/3, maximum CPU operating */
- /* frequency is 133.3 MHz */
- return 130000000;
+ /* Division value is 1/3, maximum CPU operating */
+ /* frequency is 133.3 MHz */
+ return 130000000;
}
else
{
- /* Division value is 1/4, maximum CPU operating */
- /* frequency is 100 MHz */
- return 100000000;
+ /* Division value is 1/4, maximum CPU operating */
+ /* frequency is 100 MHz */
+ return 100000000;
}
}
}
/*******************************************************************************
*
-* get_fpiclk - returns the frequency of the FPI bus.
+* get_fpiclk - returns the frequency of the FPI bus.
*
* Gets the value directly from the INCA-IP hardware.
*
@@ -82,26 +81,24 @@
* This functions should be used by the hardware driver to get the correct
* frequency of the CPU. Don't use the macros, which are set to init the CPU
* frequency in the ROM code.
-* The calculation for the
+* The calculation for the
*/
uint incaip_get_fpiclk(void)
{
uint clkCPU;
-
+
clkCPU = incaip_get_cpuclk();
-
+
switch (*((volatile ulong*)INCA_IP_CGU_CGU_DIVCR) & 0xC)
{
case 0x4:
- return clkCPU >> 1; /* devided by 2 */
- break;
+ return clkCPU >> 1; /* devided by 2 */
+ break;
case 0x8:
- return clkCPU >> 2; /* devided by 4 */
- break;
+ return clkCPU >> 2; /* devided by 4 */
+ break;
default:
- return clkCPU;
- break;
+ return clkCPU;
+ break;
}
}
-
-
diff --git a/cpu/mips/incaip_wdt.S b/cpu/mips/incaip_wdt.S
index 9455569..71adaa1 100644
--- a/cpu/mips/incaip_wdt.S
+++ b/cpu/mips/incaip_wdt.S
@@ -70,4 +70,3 @@
j ra
nop
-
diff --git a/cpu/mips/interrupts.c b/cpu/mips/interrupts.c
index 0490a76..87f7a9f 100644
--- a/cpu/mips/interrupts.c
+++ b/cpu/mips/interrupts.c
@@ -31,4 +31,3 @@
{
return 0;
}
-
diff --git a/cpu/mips/serial.c b/cpu/mips/serial.c
index b26f41d..585227a 100644
--- a/cpu/mips/serial.c
+++ b/cpu/mips/serial.c
@@ -23,7 +23,7 @@
#define TOUT_LOOP 100000
/* Set base address for second FPI interrupt control register bank */
-#define SFPI_INTCON_BASEADDR 0xBF0F0000
+#define SFPI_INTCON_BASEADDR 0xBF0F0000
/* Register offset from base address */
#define FBS_ISR 0x00000000 /* Interrupt status register */
@@ -75,11 +75,11 @@
/* we have to set PMU.EN13 bit to enable an ASC device*/
INCAASC_PMU_ENABLE(13);
#endif
-
+
/* and we have to set CLC register*/
CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS);
SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
-
+
/* initialy we are in async mode */
pAsc->asc_con = ASCCON_M_8ASYNC;
@@ -89,13 +89,13 @@
#ifdef ASC_FIFO_PRESENT
/* TXFIFO's filling level */
SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK,
- ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
+ ASCTXFCON_TXFITLOFF, INCAASC_TXFIFO_FL);
/* enable TXFIFO */
SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN);
/* RXFIFO's filling level */
- SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
- ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
+ SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK,
+ ASCRXFCON_RXFITLOFF, INCAASC_RXFIFO_FL);
/* enable RXFIFO */
SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN);
#endif
@@ -123,7 +123,7 @@
/* set the options */
serial_setopt();
-
+
return 0;
}
@@ -141,25 +141,25 @@
#ifndef INCAASC_USE_FDV
fdv = 2;
uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
+#else
fdv = INCAASC_FDV_HIGH_BAUDRATE;
uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
#endif /* INCAASC_USE_FDV */
-
+
if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
{
#ifndef INCAASC_USE_FDV
- fdv = 3;
- uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
-#else
- fdv = INCAASC_FDV_LOW_BAUDRATE;
- uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
+ fdv = 3;
+ uiReloadValue = (f_ASC / (fdv * 16 * CONFIG_BAUDRATE)) - 1;
+#else
+ fdv = INCAASC_FDV_LOW_BAUDRATE;
+ uiReloadValue = (f_ASC / (8192 * CONFIG_BAUDRATE / fdv)) - 1;
#endif /* INCAASC_USE_FDV */
-
- if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
- {
- return; /* can't impossibly generate that baud rate */
- }
+
+ if ( (uiReloadValue < 0) || (uiReloadValue > 8191) )
+ {
+ return; /* can't impossibly generate that baud rate */
+ }
}
/* Disable Baud Rate Generator; BG should only be written when R=0 */
@@ -174,9 +174,9 @@
CLEAR_BIT(pAsc->asc_con, ASCCON_FDE);
if ( fdv == 2 )
- CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
+ CLEAR_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 0 */
else
- SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
+ SET_BIT(pAsc->asc_con, ASCCON_BRS); /* BRS = 1 */
#else /* INCAASC_USE_FDV */
@@ -217,42 +217,42 @@
{
/* 7-bit-data */
case ASCOPT_CS7:
- con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
- break;
+ con = ASCCON_M_7ASYNCPAR; /* 7-bit-data and parity bit */
+ break;
/* 8-bit-data */
case ASCOPT_CS8:
- if ( ASC_OPTIONS & ASCOPT_PARENB )
- con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
- else
- con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
- break;
-
- /*
+ if ( ASC_OPTIONS & ASCOPT_PARENB )
+ con = ASCCON_M_8ASYNCPAR; /* 8-bit-data and parity bit */
+ else
+ con = ASCCON_M_8ASYNC; /* 8-bit-data no parity */
+ break;
+
+ /*
* only 7 and 8-bit frames are supported
- * if we don't use IOCTL extensions
+ * if we don't use IOCTL extensions
*/
default:
- return -1;
+ return -1;
}
if ( ASC_OPTIONS & ASCOPT_STOPB )
- SET_BIT(con, ASCCON_STP); /* 2 stop bits */
+ SET_BIT(con, ASCCON_STP); /* 2 stop bits */
else
- CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
+ CLEAR_BIT(con, ASCCON_STP); /* 1 stop bit */
if ( ASC_OPTIONS & ASCOPT_PARENB )
- SET_BIT(con, ASCCON_PEN); /* enable parity checking */
+ SET_BIT(con, ASCCON_PEN); /* enable parity checking */
else
- CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
-
+ CLEAR_BIT(con, ASCCON_PEN); /* disable parity checking */
+
if ( ASC_OPTIONS & ASCOPT_PARODD )
- SET_BIT(con, ASCCON_ODD); /* odd parity */
+ SET_BIT(con, ASCCON_ODD); /* odd parity */
else
- CLEAR_BIT(con, ASCCON_ODD); /* even parity */
+ CLEAR_BIT(con, ASCCON_ODD); /* even parity */
if ( ASC_OPTIONS & ASCOPT_CREAD )
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_SETREN); /* Receiver enable */
pAsc->asc_con |= con;
@@ -293,14 +293,14 @@
#ifndef ASC_FIFO_PRESENT
*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) = FBS_ISR_AB |
- FBS_ISR_AT;
+ FBS_ISR_AT;
#endif
-
+
/* check for errors */
if ( pAsc->asc_con & ASCCON_OE )
{
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
- return;
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+ return;
}
}
@@ -321,7 +321,7 @@
symbol_mask =
((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff);
-
+
c = (char)(pAsc->asc_rbuf & symbol_mask);
#ifndef ASC_FIFO_PRESENT
@@ -338,30 +338,30 @@
#ifdef ASC_FIFO_PRESENT
if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 )
{
- res = 0;
+ res = 0;
}
#else
if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) &
- FBS_ISR_AR))
-
+ FBS_ISR_AR))
+
{
- res = 0;
+ res = 0;
}
#endif
else if ( pAsc->asc_con & ASCCON_FE )
{
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
- res = 0;
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE);
+ res = 0;
}
else if ( pAsc->asc_con & ASCCON_PE )
{
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
- res = 0;
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE);
+ res = 0;
}
else if ( pAsc->asc_con & ASCCON_OE )
{
- SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
- res = 0;
+ SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE);
+ res = 0;
}
return res;
diff --git a/cpu/mips/serial.h b/cpu/mips/serial.h
index ee63360..7ffdcfa 100644
--- a/cpu/mips/serial.h
+++ b/cpu/mips/serial.h
@@ -24,7 +24,7 @@
#ifdef INCAASC_USE_FDV
#define INCAASC_FDV_LOW_BAUDRATE 71
- #define INCAASC_FDV_HIGH_BAUDRATE 453
+ #define INCAASC_FDV_HIGH_BAUDRATE 453
#endif /*INCAASC_USE_FDV*/
@@ -41,7 +41,7 @@
#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
-/* interrupt controller access macros */
+/* interrupt controller access macros */
#define ASC_INTERRUPTS_ENABLE(X) \
*((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
#define ASC_INTERRUPTS_DISABLE(X) \
@@ -96,9 +96,9 @@
#define ASCABCON_FCDETEN 0x0010
#define ASCABCON_EMMASK 0x0300
#define ASCABCON_EMOFF 8
- #define ASCABCON_EM_DISAB 0x0
- #define ASCABCON_EM_DURAB 0x1
- #define ASCABCON_EM_ALWAYS 0x2
+ #define ASCABCON_EM_DISAB 0x0
+ #define ASCABCON_EM_DURAB 0x1
+ #define ASCABCON_EM_ALWAYS 0x2
#define ASCABCON_TXINV 0x0400
#define ASCABCON_RXINV 0x0800
@@ -175,4 +175,3 @@
} incaAsc_t;
#endif /* __INCincaAscSioh */
-
diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index b504393..12129de 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -65,7 +65,7 @@
RVECENT(romReserved,14)
RVECENT(romReserved,15)
RVECENT(romReserved,16)
- RVECENT(romReserved,17)
+ RVECENT(romReserved,17)
RVECENT(romReserved,18)
RVECENT(romReserved,19)
RVECENT(romReserved,20)
@@ -111,7 +111,7 @@
RVECENT(romReserved,60)
RVECENT(romReserved,61)
RVECENT(romReserved,62)
- RVECENT(romReserved,63)
+ RVECENT(romReserved,63)
XVECENT(romExcHandle,0x200) /* bfc00200: R4000 tlbmiss vector */
RVECENT(romReserved,65)
RVECENT(romReserved,66)
@@ -127,7 +127,7 @@
RVECENT(romReserved,76)
RVECENT(romReserved,77)
RVECENT(romReserved,78)
- RVECENT(romReserved,79)
+ RVECENT(romReserved,79)
XVECENT(romExcHandle,0x280) /* bfc00280: R4000 xtlbmiss vector */
RVECENT(romReserved,81)
RVECENT(romReserved,82)
@@ -143,7 +143,7 @@
RVECENT(romReserved,92)
RVECENT(romReserved,93)
RVECENT(romReserved,94)
- RVECENT(romReserved,95)
+ RVECENT(romReserved,95)
XVECENT(romExcHandle,0x300) /* bfc00300: R4000 cache vector */
RVECENT(romReserved,97)
RVECENT(romReserved,98)
@@ -176,7 +176,7 @@
RVECENT(romReserved,125)
RVECENT(romReserved,126)
RVECENT(romReserved,127)
-
+
/* We hope there are no more reserved vectors!
* 128 * 8 == 1024 == 0x400
* so this is address R_VEC+0x400 == 0xbfc00400
@@ -237,7 +237,7 @@
nop
#endif
- /* Initialize any external memory.
+ /* Initialize any external memory.
*/
bal memsetup
nop
@@ -300,7 +300,7 @@
sub gp, CFG_MONITOR_BASE
add gp, a2 /* gp now adjusted */
sub t6, gp, t6 /* t6 <-- relocation offset */
-
+
li t0, CFG_MONITOR_BASE
la t3, in_ram
lw t2, -12(t3) /* t2 <-- uboot_end_data */
@@ -363,14 +363,13 @@
1: addi t1, 4
bltl t1, t2, 1b
sw zero, 0(t1) /* delay slot */
-
+
move a0, a1
la t9, board_init_r
j t9
move a1, a2 /* delay slot */
.end relocate_code
-
/* Exception handlers.
@@ -380,4 +379,3 @@
romExcHandle:
b romExcHandle
-
diff --git a/cpu/mpc5xx/Makefile b/cpu/mpc5xx/Makefile
index c05b394..ee20dda 100644
--- a/cpu/mpc5xx/Makefile
+++ b/cpu/mpc5xx/Makefile
@@ -23,10 +23,10 @@
#
# File: cpu/mpc5xx/Makefile
-#
+#
# Discription: Makefile to build mpc5xx cpu configuration.
# Will include top config.mk which itselfs
-# uses the definitions made in cpu/mpc5xx/config.mk
+# uses the definitions made in cpu/mpc5xx/config.mk
#
@@ -34,7 +34,7 @@
LIB = lib$(CPU).a
-START = start.S
+START = start.S
OBJS = serial.o cpu.o cpu_init.o interrupts.o traps.o speed.o
all: .depend $(START) $(LIB)
diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk
index d302d48..cfed499 100644
--- a/cpu/mpc5xx/config.mk
+++ b/cpu/mpc5xx/config.mk
@@ -23,12 +23,11 @@
#
# File: config.mk
-#
+#
# Discription: compiler flags and make definitions
#
-
+
PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float
-
diff --git a/cpu/mpc5xx/cpu.c b/cpu/mpc5xx/cpu.c
index 5b3bd26..cc69511 100644
--- a/cpu/mpc5xx/cpu.c
+++ b/cpu/mpc5xx/cpu.c
@@ -17,15 +17,15 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation,
+ * Foundation,
*/
/*
* File: cpu.c
- *
- * Discription: Some cpu specific function for watchdog,
+ *
+ * Discription: Some cpu specific function for watchdog,
* cpu version test, clock setting ...
- *
+ *
*/
@@ -74,7 +74,7 @@
}
/*
- * Called by macro WATCHDOG_RESET
+ * Called by macro WATCHDOG_RESET
*/
#if defined(CONFIG_WATCHDOG)
void watchdog_reset (void)
@@ -93,7 +93,7 @@
{
/* Use the MPC5xx Internal Watchdog */
immr->im_siu_conf.sc_swsr = 0x556c; /* Prevent SW time-out */
- immr->im_siu_conf.sc_swsr = 0xaa39;
+ immr->im_siu_conf.sc_swsr = 0xaa39;
}
#endif /* CONFIG_WATCHDOG */
@@ -124,32 +124,31 @@
/*
- * Reset board
+ * Reset board
*/
int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong addr;
-
+
/* Interrupts off, enable reset */
- __asm__ volatile (" mtspr 81, %r0 \n\t"
+ __asm__ volatile (" mtspr 81, %r0 \n\t"
" mfmsr %r3 \n\t"
" rlwinm %r31,%r3,0,25,23\n\t"
" mtmsr %r31 \n\t");
- /*
- * Trying to execute the next instruction at a non-existing address
- * should cause a machine check, resulting in reset
- */
+ /*
+ * Trying to execute the next instruction at a non-existing address
+ * should cause a machine check, resulting in reset
+ */
#ifdef CFG_RESET_ADDRESS
- addr = CFG_RESET_ADDRESS;
+ addr = CFG_RESET_ADDRESS;
#else
- /*
- * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address
- * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
- * "(ulong)-1" used to be a good choice for many systems...
- */
- addr = CFG_MONITOR_BASE - sizeof (ulong);
+ /*
+ * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE * - sizeof (ulong) is usually a valid address. Better pick an address
+ * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
+ * "(ulong)-1" used to be a good choice for many systems...
+ */
+ addr = CFG_MONITOR_BASE - sizeof (ulong);
#endif
((void (*) (void)) addr) ();
return 1;
}
-
diff --git a/cpu/mpc5xx/cpu_init.c b/cpu/mpc5xx/cpu_init.c
index 27cf3d6..e19d0f4 100644
--- a/cpu/mpc5xx/cpu_init.c
+++ b/cpu/mpc5xx/cpu_init.c
@@ -16,12 +16,12 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation,
+ * Foundation,
*/
/*
* File: cpu_init.c
- *
+ *
* Discription: Contains initialisation functions to setup
* the cpu properly
*
@@ -32,7 +32,7 @@
#include <watchdog.h>
/*
- * Setup essential cpu registers to run
+ * Setup essential cpu registers to run
*/
void cpu_init_f (volatile immap_t * immr)
{
@@ -45,7 +45,7 @@
#if defined(CONFIG_WATCHDOG)
reset_5xx_watchdog (immr);
-#endif
+#endif
/* SIUMCR - contains debug pin configuration */
immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
@@ -56,10 +56,10 @@
/* Full IMB bus speed */
immr->im_uimb.uimb_umcr = CFG_UMCR;
-
+
/* Time base and decrementer will be enables (TBE) */
/* in init_timebase() in time.c called from board_init_f(). */
-
+
/* Initialize the PIT. Unlock PISCRK */
immr->im_sitk.sitk_piscrk = KAPWR_KEY;
immr->im_sit.sit_piscr = CFG_PISCR;
diff --git a/cpu/mpc5xx/interrupts.c b/cpu/mpc5xx/interrupts.c
index 282c316..4618680 100644
--- a/cpu/mpc5xx/interrupts.c
+++ b/cpu/mpc5xx/interrupts.c
@@ -17,12 +17,12 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation,
+ * Foundation,
*/
/*
* File: interrupt.c
- *
+ *
* Discription: Contains interrupt routines needed by U-Boot
*
*/
@@ -46,7 +46,7 @@
static struct interrupt_action irq_vecs[NR_IRQS];
/*
- * Local function prototypes
+ * Local function prototypes
*/
static __inline__ unsigned long get_msr (void)
{
@@ -78,15 +78,15 @@
}
/*
- * Enable interrupts
- */
+ * Enable interrupts
+ */
void enable_interrupts (void)
{
set_msr (get_msr () | MSR_EE);
}
-/*
- * Returns flag if MSR_EE was set before
+/*
+ * Returns flag if MSR_EE was set before
*/
int disable_interrupts (void)
{
@@ -97,7 +97,7 @@
}
/*
- * Initialise interrupts
+ * Initialise interrupts
*/
int interrupt_init (void)
@@ -209,7 +209,7 @@
volatile ulong timestamp = 0;
/*
- * Timer interrupt - gets called when bit 0 of DEC changes from
+ * Timer interrupt - gets called when bit 0 of DEC changes from
* 0. Decrementer is enabled with bit TBE in TBSCR.
*/
void timer_interrupt (struct pt_regs *regs)
@@ -226,7 +226,7 @@
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
__asm__ ("nop");
immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
-
+
/* Restore Decrementer Count */
set_dec (decrementer_count);
@@ -249,7 +249,7 @@
}
/*
- * Reset timer
+ * Reset timer
*/
void reset_timer (void)
{
diff --git a/cpu/mpc5xx/serial.c b/cpu/mpc5xx/serial.c
index 738c275..4868782 100644
--- a/cpu/mpc5xx/serial.c
+++ b/cpu/mpc5xx/serial.c
@@ -17,13 +17,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation,
+ * Foundation,
*/
/*
* File: serial.c
- *
- * Discription: Serial interface driver for SCI1 and SCI2.
+ *
+ * Discription: Serial interface driver for SCI1 and SCI2.
* Since this code will be called from ROM use
* only non-static local variables.
*
@@ -36,7 +36,7 @@
/*
- * Local function prototypes
+ * Local function prototypes
*/
static int ready_to_send(void);
@@ -54,25 +54,25 @@
#if defined(CONFIG_5xx_CONS_SCI1)
/* 10-Bit, 1 start bit, 8 data bit, no parity, 1 stop bit */
immr->im_qsmcm.qsmcm_scc1r1 = SCI_M_10;
- immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE;
+ immr->im_qsmcm.qsmcm_scc1r1 = SCI_TE | SCI_RE;
#else
- immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10;
+ immr->im_qsmcm.qsmcm_scc2r1 = SCI_M_10;
immr->im_qsmcm.qsmcm_scc2r1 = SCI_TE | SCI_RE;
#endif
return 0;
}
void serial_putc(const char c)
-{
+{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
-
+
/* Test for completition */
if(ready_to_send()) {
#if defined(CONFIG_5xx_CONS_SCI1)
- immr->im_qsmcm.qsmcm_sc1dr = (short)c;
+ immr->im_qsmcm.qsmcm_sc1dr = (short)c;
#else
immr->im_qsmcm.qsmcm_sc2dr = (short)c;
-#endif
+#endif
if(c == '\n') {
if(ready_to_send());
#if defined(CONFIG_5xx_CONS_SCI1)
@@ -85,27 +85,27 @@
}
int serial_getc(void)
-{
+{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile short status;
unsigned char tmp;
-
+
/* New data ? */
do {
#if defined(CONFIG_5xx_CONS_SCI1)
- status = immr->im_qsmcm.qsmcm_sc1sr;
+ status = immr->im_qsmcm.qsmcm_sc1sr;
#else
status = immr->im_qsmcm.qsmcm_sc2sr;
#endif
#if defined(CONFIG_WATCHDOG)
- reset_5xx_watchdog (immr);
+ reset_5xx_watchdog (immr);
#endif
- } while ((status & SCI_RDRF) == 0);
-
+ } while ((status & SCI_RDRF) == 0);
+
/* Read data */
#if defined(CONFIG_5xx_CONS_SCI1)
- tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK);
+ tmp = (unsigned char)(immr->im_qsmcm.qsmcm_sc1dr & SCI_SCXDR_MK);
#else
tmp = (unsigned char)( immr->im_qsmcm.qsmcm_sc2dr & SCI_SCXDR_MK);
#endif
@@ -115,27 +115,27 @@
int serial_tstc()
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
- short status;
+ short status;
/* New data character ? */
#if defined(CONFIG_5xx_CONS_SCI1)
- status = immr->im_qsmcm.qsmcm_sc1sr;
+ status = immr->im_qsmcm.qsmcm_sc1sr;
#else
status = immr->im_qsmcm.qsmcm_sc2sr;
#endif
- return (status & SCI_RDRF);
+ return (status & SCI_RDRF);
}
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
short scxbr;
/* Set baudrate */
scxbr = (gd->cpu_clk / (32 * gd->baudrate));
#if defined(CONFIG_5xx_CONS_SCI1)
- immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK);
+ immr->im_qsmcm.qsmcm_scc1r0 = (scxbr & SCI_SCXBR_MK);
#else
immr->im_qsmcm.qsmcm_scc2r0 = (scxbr & SCI_SCXBR_MK);
#endif
@@ -154,18 +154,17 @@
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile short status;
- do {
+ do {
#if defined(CONFIG_5xx_CONS_SCI1)
- status = immr->im_qsmcm.qsmcm_sc1sr;
+ status = immr->im_qsmcm.qsmcm_sc1sr;
#else
status = immr->im_qsmcm.qsmcm_sc2sr;
#endif
#if defined(CONFIG_WATCHDOG)
- reset_5xx_watchdog (immr);
+ reset_5xx_watchdog (immr);
#endif
- } while ((status & SCI_TDRE) == 0);
- return 1;
+ } while ((status & SCI_TDRE) == 0);
+ return 1;
}
-
diff --git a/cpu/mpc5xx/speed.c b/cpu/mpc5xx/speed.c
index 8098c99..f6097f5 100644
--- a/cpu/mpc5xx/speed.c
+++ b/cpu/mpc5xx/speed.c
@@ -17,14 +17,14 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation,
+ * Foundation,
*/
/*
* File: speed.c
- *
+ *
* Discription: Provides cpu speed calculation
- *
+ *
*/
#include <common.h>
@@ -49,8 +49,8 @@
gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1));
} else {
gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK));
- }
-
+ }
+
#else /* CONFIG_5xx_GCLK_FREQ */
gd->bus_clk = CONFIG_5xx_GCLK_FREQ;
#endif /* CONFIG_5xx_GCLK_FREQ */
diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S
index 694de77..3b6d344 100644
--- a/cpu/mpc5xx/start.S
+++ b/cpu/mpc5xx/start.S
@@ -3,7 +3,7 @@
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
* Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
* Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
- *
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -25,7 +25,7 @@
/*
* File: start.S
- *
+ *
* Discription: startup code
*
*/
@@ -39,9 +39,9 @@
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
-
+
#include <linux/config.h>
-#include <asm/processor.h>
+#include <asm/processor.h>
#ifndef CONFIG_IDENT_STRING
#define CONFIG_IDENT_STRING ""
@@ -88,7 +88,7 @@
_start:
mfspr r3, 638
li r4, CFG_ISB /* Set ISB bit */
- or r3, r3, r4
+ or r3, r3, r4
mtspr 638, r3
li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
b boot_cold
@@ -131,7 +131,7 @@
/* Initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
-
+
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r2, CFG_INIT_SP_ADDR@h
ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
@@ -169,7 +169,6 @@
bl board_init_f /* run 1st part of board init code (from Flash) */
-
.globl _start_of_vectors
_start_of_vectors:
@@ -389,7 +388,7 @@
SYNC
rfi
-
+
/*
* unsigned int get_immr (unsigned int mask)
*
@@ -476,7 +475,7 @@
stwu r0,-4(r7)
bdnz 3b
-4: sync
+4: sync
isync
/*
@@ -493,8 +492,8 @@
/*
* Relocation Function, r14 point to got2+0x8000
*
- * Adjust got2 pointers, no need to check for 0, this code
- * already puts a few entries in the table.
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
@@ -508,7 +507,7 @@
bdnz 1b
/*
- * Now adjust the fixups and the pointers to the fixups
+ * Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
2: li r0,__fixup_entries@sectoff@l
diff --git a/cpu/mpc824x/Makefile b/cpu/mpc824x/Makefile
index 743ced9..3c00fc7 100644
--- a/cpu/mpc824x/Makefile
+++ b/cpu/mpc824x/Makefile
@@ -27,7 +27,7 @@
START = start.S drivers/i2c/i2c2.o
OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \
- drivers/epic/epic1.o drivers/i2c/i2c1.o pci.o bedbug_603e.o
+ drivers/epic/epic1.o drivers/i2c/i2c1.o pci.o bedbug_603e.o
all: .depend $(START) $(LIB)
diff --git a/cpu/mpc824x/cpu.c b/cpu/mpc824x/cpu.c
index 0d822d5..312dfe2 100644
--- a/cpu/mpc824x/cpu.c
+++ b/cpu/mpc824x/cpu.c
@@ -92,8 +92,7 @@
/*------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc,
- char *argv[])
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong msr, addr;
@@ -114,11 +113,11 @@
addr = CFG_RESET_ADDRESS;
#else
/*
- * note: when CFG_MONITOR_BASE points to a RAM address,
- * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
- * address. Better pick an address known to be invalid on
- * your system and assign it to CFG_RESET_ADDRESS.
- * "(ulong)-1" used to be a good choice for many systems...
+ * note: when CFG_MONITOR_BASE points to a RAM address,
+ * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
+ * address. Better pick an address known to be invalid on
+ * your system and assign it to CFG_RESET_ADDRESS.
+ * "(ulong)-1" used to be a good choice for many systems...
*/
addr = CFG_MONITOR_BASE - sizeof (ulong);
#endif
diff --git a/cpu/mpc824x/cpu_init.c b/cpu/mpc824x/cpu_init.c
index 602f65d..3b5fb79 100644
--- a/cpu/mpc824x/cpu_init.c
+++ b/cpu/mpc824x/cpu_init.c
@@ -84,7 +84,7 @@
" \
: /* no output */ \
: "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
- "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
+ "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
);
M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
@@ -145,8 +145,8 @@
#if defined(CFG_ASRISE) && defined(CFG_ASFALL)
CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
- CFG_ASRISE << MCCR2_ASRISE_SHIFT |
- CFG_ASFALL << MCCR2_ASFALL_SHIFT);
+ CFG_ASRISE << MCCR2_ASRISE_SHIFT |
+ CFG_ASFALL << MCCR2_ASFALL_SHIFT);
#else
CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
#endif
@@ -196,13 +196,13 @@
CONFIG_WRITE_WORD(MCCR4,
(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
(CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
- (CFG_EXTROM ? MCCR4_EXTROM : 0) |
- (CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
+ (CFG_EXTROM ? MCCR4_EXTROM : 0) |
+ (CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
(CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
(CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
(((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
- (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
+ (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
(CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
(((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#else
diff --git a/cpu/mpc824x/drivers/dma/README b/cpu/mpc824x/drivers/dma/README
index ab4b68b..06f4bc0 100644
--- a/cpu/mpc824x/drivers/dma/README
+++ b/cpu/mpc824x/drivers/dma/README
@@ -98,5 +98,3 @@
7. The DMA driver routines contains a set
of utilities, Set and Get, for host system
to query and modify the desired DMA registers.
-
-
diff --git a/cpu/mpc824x/drivers/dma/dma1.c b/cpu/mpc824x/drivers/dma/dma1.c
index 8c3834e..9c85267 100644
--- a/cpu/mpc824x/drivers/dma/dma1.c
+++ b/cpu/mpc824x/drivers/dma/dma1.c
@@ -129,12 +129,12 @@
* snoop is the snoop enable control
*/
extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
- DMA_TRANSFER_TYPE type,
- unsigned int source,
- unsigned int dest,
- unsigned int len,
- DMA_CHANNEL channel,
- DMA_SNOOP_MODE snoop)
+ DMA_TRANSFER_TYPE type,
+ unsigned int source,
+ unsigned int dest,
+ unsigned int len,
+ DMA_CHANNEL channel,
+ DMA_SNOOP_MODE snoop)
{
DMA_MR md;
DMA_CDAR cdar;
@@ -755,7 +755,7 @@
}
else if ( stat.pe == 1 )
{
- /* PCI error */
+ /* PCI error */
rval = DMAPERROR;
if ( pe_func != 0 )
{
@@ -783,7 +783,7 @@
}
temp = ( stat.reserved0 & 0xffffff ) << 8;
- temp |= ( ( stat.lme & 0x1 ) << 7 ); /* write one to clear */
+ temp |= ( ( stat.lme & 0x1 ) << 7 ); /* write one to clear */
temp |= ( ( stat.reserved1 & 0x3 ) << 5 );
temp |= ( ( stat.pe & 0x1 ) << 4 ); /* write one to clear */
temp |= ( ( stat.reserved2 & 0x1 ) << 3 );
diff --git a/cpu/mpc824x/drivers/dma/dma2.S b/cpu/mpc824x/drivers/dma/dma2.S
index dab1de3..ccbc226 100644
--- a/cpu/mpc824x/drivers/dma/dma2.S
+++ b/cpu/mpc824x/drivers/dma/dma2.S
@@ -12,16 +12,16 @@
*
* output: r3 - register content
**********************************************************/
- .text
- .align 2
- .global load_runtime_reg
+ .text
+ .align 2
+ .global load_runtime_reg
load_runtime_reg:
- lwbrx r3,r4,r3
- sync
+ lwbrx r3,r4,r3
+ sync
- bclr 20, 0
+ bclr 20, 0
/****************************************************************
* function: store_runtime_reg
@@ -31,15 +31,12 @@
* r5 - new value to be stored
*
****************************************************************/
- .text
- .align 2
- .global store_runtime_reg
+ .text
+ .align 2
+ .global store_runtime_reg
store_runtime_reg:
- stwbrx r5, r4, r3
- sync
+ stwbrx r5, r4, r3
+ sync
- bclr 20,0
-
-
-
+ bclr 20,0
diff --git a/cpu/mpc824x/drivers/dma/dma_export.h b/cpu/mpc824x/drivers/dma/dma_export.h
index cb750dd..471e488 100644
--- a/cpu/mpc824x/drivers/dma/dma_export.h
+++ b/cpu/mpc824x/drivers/dma/dma_export.h
@@ -71,9 +71,9 @@
* This function must be called before DMA unit can be used.
*/
extern DMA_Status DMA_Initialize(
- int (*app_print_function)(char *,...)); /* pointer to optional "printf"
- * provided by application
- */
+ int (*app_print_function)(char *,...)); /* pointer to optional "printf"
+ * provided by application
+ */
/* Perform the DMA transfer, only direct mode is currently implemented.
* At this point, I think it would be better to define a different
@@ -91,10 +91,10 @@
* snoop is the snoop enable control
*/
extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
- DMA_TRANSFER_TYPE type,
- unsigned int source,
- unsigned int dest,
- unsigned int len,
- DMA_CHANNEL channel,
- DMA_SNOOP_MODE snoop);
+ DMA_TRANSFER_TYPE type,
+ unsigned int source,
+ unsigned int dest,
+ unsigned int len,
+ DMA_CHANNEL channel,
+ DMA_SNOOP_MODE snoop);
#endif
diff --git a/cpu/mpc824x/drivers/dma_export.h b/cpu/mpc824x/drivers/dma_export.h
index cb750dd..471e488 100644
--- a/cpu/mpc824x/drivers/dma_export.h
+++ b/cpu/mpc824x/drivers/dma_export.h
@@ -71,9 +71,9 @@
* This function must be called before DMA unit can be used.
*/
extern DMA_Status DMA_Initialize(
- int (*app_print_function)(char *,...)); /* pointer to optional "printf"
- * provided by application
- */
+ int (*app_print_function)(char *,...)); /* pointer to optional "printf"
+ * provided by application
+ */
/* Perform the DMA transfer, only direct mode is currently implemented.
* At this point, I think it would be better to define a different
@@ -91,10 +91,10 @@
* snoop is the snoop enable control
*/
extern DMA_Status DMA_direct_transfer( DMA_INTERRUPT_STEER int_steer,
- DMA_TRANSFER_TYPE type,
- unsigned int source,
- unsigned int dest,
- unsigned int len,
- DMA_CHANNEL channel,
- DMA_SNOOP_MODE snoop);
+ DMA_TRANSFER_TYPE type,
+ unsigned int source,
+ unsigned int dest,
+ unsigned int len,
+ DMA_CHANNEL channel,
+ DMA_SNOOP_MODE snoop);
#endif
diff --git a/cpu/mpc824x/drivers/epic/README b/cpu/mpc824x/drivers/epic/README
index ae95b88..5798996 100644
--- a/cpu/mpc824x/drivers/epic/README
+++ b/cpu/mpc824x/drivers/epic/README
@@ -100,5 +100,3 @@
shall always call the epicEOI just before
rfi instruction. Refer to the routine,
epic_exception, for a code sample.
-
-
diff --git a/cpu/mpc824x/drivers/epic/epic.h b/cpu/mpc824x/drivers/epic/epic.h
index 17e4afb..58f81c5 100644
--- a/cpu/mpc824x/drivers/epic/epic.h
+++ b/cpu/mpc824x/drivers/epic/epic.h
@@ -123,7 +123,7 @@
unsigned int *venId
);
void epicFeatures( unsigned int *noIRQs,
- unsigned int *noCPUs,
+ unsigned int *noCPUs,
unsigned int *VerId );
extern void epicInit( unsigned int IRQType, unsigned int clkRatio);
ULONG sysEUMBBARRead ( ULONG regNum );
@@ -131,8 +131,8 @@
extern void epicTmFrequencySet( unsigned int frq );
extern unsigned int epicTmFrequencyGet(void);
extern unsigned int epicTmBaseSet( ULONG srcAddr,
- unsigned int cnt,
- unsigned int inhibit );
+ unsigned int cnt,
+ unsigned int inhibit );
extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val );
extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val );
extern unsigned int epicTmInhibit( unsigned int timer );
@@ -144,7 +144,7 @@
extern unsigned int epicIntAck(void);
extern void epicSprSet( unsigned int eumbbar, unsigned char );
extern void epicConfigGet( unsigned int *clkRatio,
- unsigned int *serEnable );
+ unsigned int *serEnable );
extern void SrcVecTableInit(void);
extern unsigned int epicModeGet(void);
extern void epicIntEnable(int Vect);
diff --git a/cpu/mpc824x/drivers/epic/epic1.c b/cpu/mpc824x/drivers/epic/epic1.c
index eb7ed40..f89deed 100644
--- a/cpu/mpc824x/drivers/epic/epic1.c
+++ b/cpu/mpc824x/drivers/epic/epic1.c
@@ -78,12 +78,12 @@
tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */
if (IRQType == EPIC_DIRECT_IRQ) /* direct mode */
- sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff);
+ sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff);
else /* Serial mode */
- {
- tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */
- sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
- }
+ {
+ tmp = (clkRatio << 28) | 0x08000000; /* Set clock ratio */
+ sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
+ }
while (epicIntAck() != 0xff) /* Clear all pending interrupts */
epicEOI();
@@ -168,7 +168,7 @@
tmp = sysEUMBBARRead(srAddr);
actBit = (tmp & 40000000) >> 30; /* retrieve activity bit - bit 30 */
if (actBit == 1)
- return ERROR;
+ return ERROR;
tmp &= 0xff30ff00; /* Erase previously set P,S,Prio,Vector bits */
newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect;
@@ -220,7 +220,7 @@
{
if ( (prioNum < 0) || (prioNum > 0xF))
- return ERROR;
+ return ERROR;
sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum);
return OK;
}
@@ -465,7 +465,6 @@
}
-
/***********************************************************
* function: epicTmInhibit
*
diff --git a/cpu/mpc824x/drivers/epic/epic2.S b/cpu/mpc824x/drivers/epic/epic2.S
index 8979f88..8cc2fc6 100644
--- a/cpu/mpc824x/drivers/epic/epic2.S
+++ b/cpu/mpc824x/drivers/epic/epic2.S
@@ -17,14 +17,14 @@
**********************************************/
.text
.align 2
- .global CoreExtIntEnable
+ .global CoreExtIntEnable
CoreExtIntEnable:
- mfmsr r3
+ mfmsr r3
- ori r3,r3,0x8000 /* enable external interrupt */
- mtmsr r3
+ ori r3,r3,0x8000 /* enable external interrupt */
+ mtmsr r3
- bclr 20, 0
+ bclr 20, 0
/*******************************************
* function: CoreExtIntDisable
@@ -35,20 +35,20 @@
*******************************************/
.text
.align 2
- .global CoreExtIntDisable
+ .global CoreExtIntDisable
CoreExtIntDisable:
- mfmsr r4
+ mfmsr r4
xor r3,r3,r3
or r3,r3,r4
andis. r4,r4,0xffff
- andi. r3,r3,0x7fff /* disable external interrupt */
+ andi. r3,r3,0x7fff /* disable external interrupt */
or r3,r3,r4
- mtmsr r3
+ mtmsr r3
- bclr 20, 0
+ bclr 20, 0
/*********************************************************
* function: epicEOI
@@ -61,20 +61,20 @@
********************************************************/
.text
.align 2
- .global epicEOI
+ .global epicEOI
epicEOI:
lis r5,0x0006 /* Build End Of Interrupt Register offset */
ori r5,r5,0x00b0
xor r7,r7,r7 /* Clear r7 */
stwbrx r7,r5,r3 /* Save r7, writing to this register will
- * intidate the end of processing the
- * highest interrupt.
- */
+ * intidate the end of processing the
+ * highest interrupt.
+ */
sync
/* ---RESTORE MACHINE STATE */
mfmsr r13 /* Clear Recoverable Interrupt bit in MSR */
- or r7,r7,r13
+ or r7,r7,r13
andis. r7,r7,0xffff
andi. r13,r13,0x7ffd /* (and disable interrupts) */
@@ -147,8 +147,8 @@
stw r3,0x1c(r1) /* Push CTR */
mtspr SPRG0,r1 /* Save updated Supervisor stack pointer
- * value to SPRG0
- */
+ * value to SPRG0
+ */
mfmsr r3
ori r3,r3,0x0002 /* Set Recoverable Interrupt bit in MSR */
mtmsr r3
@@ -159,8 +159,8 @@
/* ---READ EPIC REGISTER: PROCESSOR INTERRUPT ACKNOWLEDGE REGISTER */
lis r5,0x0006 /* Build Interrupt Acknowledge Register
- * offset
- */
+ * offset
+ */
ori r5,r5,0x00a0
lwbrx r7,r5,r6 /* Load interrupt vector into r7 */
sync
diff --git a/cpu/mpc824x/drivers/epic/epicutil.S b/cpu/mpc824x/drivers/epic/epicutil.S
index a83fbd8..4877050 100644
--- a/cpu/mpc824x/drivers/epic/epicutil.S
+++ b/cpu/mpc824x/drivers/epic/epicutil.S
@@ -29,12 +29,12 @@
load_runtime_reg:
xor r5,r5,r5
- or r5,r5,r3 /* save eumbbar */
+ or r5,r5,r3 /* save eumbbar */
lwbrx r3,r4,r5
sync
- bclr 20, 0
+ bclr 20, 0
/****************************************************************
* function: store_runtime_reg
@@ -44,9 +44,9 @@
* r5 - new value to be stored
*
****************************************************************/
- .text
- .align 2
- .global store_runtime_reg
+ .text
+ .align 2
+ .global store_runtime_reg
store_runtime_reg:
xor r0,r0,r0
@@ -55,4 +55,3 @@
sync
bclr 20,0
-
diff --git a/cpu/mpc824x/drivers/errors.h b/cpu/mpc824x/drivers/errors.h
index 1435188..887f284 100644
--- a/cpu/mpc824x/drivers/errors.h
+++ b/cpu/mpc824x/drivers/errors.h
@@ -30,7 +30,7 @@
#include "config.h"
/*
- 1 2 3 4 5 6 7 8
+ 1 2 3 4 5 6 7 8
01234567890123456789012345678901234567890123456789012345678901234567890123456789
*/
/* List define statements here */
@@ -78,7 +78,6 @@
#define FOR_BOARD_ONLY 0xfb0a /* "Not available for Unix." */
-
/*----------------------------------------------------------------------*/
/* these are for the error checking toolbox */
@@ -147,9 +146,6 @@
#define UNKNOWN_PARAMETER 0xFE01 /* "unknown type of parameter "*/
-
-
-
/*----------------------------------------------------------------------*/
/* these are for the tokenizer toolbox */
@@ -164,7 +160,6 @@
#define NO_OPEN_IBS 0xFF08 /* "no open input buffers" */
-
/* these are for the read from screen toolbox */
#define RESERVED_WORD 0xFC00 /* used a reserved word as an arguement*/
@@ -175,7 +170,6 @@
#define FULL_BPDS 0xFA00 /* breakpoint data structure is full */
-
/* THESE are for the downloader */
#define NOT_IN_S_RECORD_FORMAT 0xf900 /* "not in S-Record Format" */
diff --git a/cpu/mpc824x/drivers/i2c/README b/cpu/mpc824x/drivers/i2c/README
index 8d82df3..1db7210 100644
--- a/cpu/mpc824x/drivers/i2c/README
+++ b/cpu/mpc824x/drivers/i2c/README
@@ -102,4 +102,3 @@
host system a way to use its own event
handler instead of the I2C_ISR provided
here.
-
diff --git a/cpu/mpc824x/drivers/i2c/i2c.h b/cpu/mpc824x/drivers/i2c/i2c.h
index 3209bfe..48a401d 100644
--- a/cpu/mpc824x/drivers/i2c/i2c.h
+++ b/cpu/mpc824x/drivers/i2c/i2c.h
@@ -109,13 +109,13 @@
*/
static I2CStatus I2C_put( unsigned int eumbbar,
unsigned char rcv_addr, /* receiver's address */
- unsigned char *buffer_ptr, /* pointer of data to be sent */
+ unsigned char *buffer_ptr, /* pointer of data to be sent */
unsigned int length, /* number of byte of in the buffer */
unsigned int stop_flag, /* 1 - signal STOP when buffer is empty
- * 0 - no STOP signal when buffer is empty
- */
+ * 0 - no STOP signal when buffer is empty
+ */
unsigned int is_cnt ); /* 1 - this is a restart, don't check MBB
- * 0 - this is a new start, check MBB
+ * 0 - this is a new start, check MBB
*/
/* Receive a buffer of data from the desired sender_addr
@@ -130,12 +130,12 @@
static I2CStatus I2C_get( unsigned int eumbbar,
unsigned char sender_addr, /* sender's address */
unsigned char *buffer_ptr, /* pointer of receiving buffer */
- unsigned int length, /* length of the receiving buffer */
+ unsigned int length, /* length of the receiving buffer */
unsigned int stop_flag, /* 1 - signal STOP when buffer is full
- * 0 - no STOP signal when buffer is full
+ * 0 - no STOP signal when buffer is full
*/
unsigned int is_cnt ); /* 1 - this is a restart, don't check MBB
- * 0 - this is a new start, check MBB
+ * 0 - this is a new start, check MBB
*/
#if 0 /* the I2C_write and I2C_read functions are not active */
@@ -160,10 +160,10 @@
*/
static I2CStatus I2C_write( unsigned int eumbbar,
unsigned char *buffer_ptr, /* pointer of data to be sent */
- unsigned int length, /* number of byte of in the buffer */
- unsigned int stop_flag ); /* 1 - signal STOP when buffer is empty
- * 0 - no STOP signal when buffer is empty
- */
+ unsigned int length, /* number of byte of in the buffer */
+ unsigned int stop_flag ); /* 1 - signal STOP when buffer is empty
+ * 0 - no STOP signal when buffer is empty
+ */
/* Receive a buffer of data from the sending master.
* If stop_flag is set, when the buffer is full and the
@@ -175,8 +175,8 @@
static I2CStatus I2C_read(unsigned int eumbbar,
unsigned char *buffer_ptr, /* pointer of receiving buffer */
unsigned int length, /* length of the receiving buffer */
- unsigned int stop_flag ); /* 1 - signal STOP when buffer is full
- * 0 - no STOP signal when buffer is full
+ unsigned int stop_flag ); /* 1 - signal STOP when buffer is full
+ * 0 - no STOP signal when buffer is full
*/
#endif /* of if0 for turning off I2C_read & I2C_write */
@@ -203,12 +203,12 @@
*/
static I2CStatus I2C_Start( unsigned int eumbbar,
unsigned char slave_addr, /* address of the receiver */
- I2C_MODE mode, /* XMIT(1) - put (write)
- * RCV(0) - get (read)
+ I2C_MODE mode, /* XMIT(1) - put (write)
+ * RCV(0) - get (read)
*/
unsigned int is_cnt ); /* 1 - this is a restart, don't check MBB
* 0 - this is a new start, check MBB
- */
+ */
/* Generate a STOP signal to terminate the transaction. */
static I2CStatus I2C_Stop( unsigned int eumbbar );
@@ -258,10 +258,10 @@
*/
static I2CStatus I2C_Init( unsigned int eumbbar,
unsigned char fdr, /* frequency divider */
- unsigned char addr, /* driver's address used for receiving */
- unsigned int en_int); /* 1 - enable I2C interrupt
- * 0 - disable I2C interrup
- */
+ unsigned char addr, /* driver's address used for receiving */
+ unsigned int en_int); /* 1 - enable I2C interrupt
+ * 0 - disable I2C interrup
+ */
/* I2C interrupt service routine.
*
@@ -299,11 +299,11 @@
* I2C_RESTART, this is a continuation of existing transaction
*/
static I2C_Status I2C_do_buffer( I2C_INTERRUPT_MODE en_int,
- I2C_TRANSACTION_MODE act,
- unsigned char i2c_addr,
- int len,
- unsigned char *buffer,
- I2C_STOP_MODE stop,
- int retry,
- I2C_RESTART_MODE rsta);
+ I2C_TRANSACTION_MODE act,
+ unsigned char i2c_addr,
+ int len,
+ unsigned char *buffer,
+ I2C_STOP_MODE stop,
+ int retry,
+ I2C_RESTART_MODE rsta);
#endif
diff --git a/cpu/mpc824x/drivers/i2c/i2c2.S b/cpu/mpc824x/drivers/i2c/i2c2.S
index 5cc7c98..3fd7e03 100644
--- a/cpu/mpc824x/drivers/i2c/i2c2.S
+++ b/cpu/mpc824x/drivers/i2c/i2c2.S
@@ -16,20 +16,20 @@
*
* output: r3 - register content
**********************************************************/
- .text
- .align 2
- .global load_runtime_reg
+ .text
+ .align 2
+ .global load_runtime_reg
load_runtime_reg:
-/* xor r5,r5,r5
-* or r5,r5,r3
-*
-* lwbrx r3,r4,r5
-*/
- lwbrx r3,r4,r3
- sync
+/* xor r5,r5,r5
+ * or r5,r5,r3
+ *
+ * lwbrx r3,r4,r5
+ */
+ lwbrx r3,r4,r3
+ sync
- bclr 20, 0
+ bclr 20, 0
/****************************************************************
* function: store_runtime_reg
@@ -39,16 +39,14 @@
* r5 - new value to be stored
*
****************************************************************/
- .text
- .align 2
- .global store_runtime_reg
+ .text
+ .align 2
+ .global store_runtime_reg
store_runtime_reg:
- stwbrx r5, r4, r3
- sync
+ stwbrx r5, r4, r3
+ sync
- bclr 20,0
-
-
+ bclr 20,0
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc824x/drivers/i2c/i2c_export.h b/cpu/mpc824x/drivers/i2c/i2c_export.h
index 17403ea..6264d18 100644
--- a/cpu/mpc824x/drivers/i2c/i2c_export.h
+++ b/cpu/mpc824x/drivers/i2c/i2c_export.h
@@ -71,11 +71,11 @@
extern I2C_Status I2C_Initialize(
unsigned char addr, /* driver's I2C slave address */
I2C_INTERRUPT_MODE en_int, /* 1 - enable I2C interrupt
- * 0 - disable I2C interrupt
- */
- int (*app_print_function)(char *,...)); /* pointer to optional "printf"
- * provided by application
- */
+ * 0 - disable I2C interrupt
+ */
+ int (*app_print_function)(char *,...)); /* pointer to optional "printf"
+ * provided by application
+ */
/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
* are implemented. Both are only in polling mode.
@@ -92,12 +92,12 @@
* I2C_RESTART, this is a continuation of existing transaction
*/
extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
- I2C_TRANSACTION_MODE act,
- unsigned char i2c_addr,
- unsigned char data_addr,
- int len,
- char *buffer,
- I2C_STOP_MODE stop,
- int retry,
- I2C_RESTART_MODE rsta);
+ I2C_TRANSACTION_MODE act,
+ unsigned char i2c_addr,
+ unsigned char data_addr,
+ int len,
+ char *buffer,
+ I2C_STOP_MODE stop,
+ int retry,
+ I2C_RESTART_MODE rsta);
#endif
diff --git a/cpu/mpc824x/drivers/i2c_export.h b/cpu/mpc824x/drivers/i2c_export.h
index 17403ea..6264d18 100644
--- a/cpu/mpc824x/drivers/i2c_export.h
+++ b/cpu/mpc824x/drivers/i2c_export.h
@@ -71,11 +71,11 @@
extern I2C_Status I2C_Initialize(
unsigned char addr, /* driver's I2C slave address */
I2C_INTERRUPT_MODE en_int, /* 1 - enable I2C interrupt
- * 0 - disable I2C interrupt
- */
- int (*app_print_function)(char *,...)); /* pointer to optional "printf"
- * provided by application
- */
+ * 0 - disable I2C interrupt
+ */
+ int (*app_print_function)(char *,...)); /* pointer to optional "printf"
+ * provided by application
+ */
/* Perform the given I2C transaction, only MASTER_XMIT and MASTER_RCV
* are implemented. Both are only in polling mode.
@@ -92,12 +92,12 @@
* I2C_RESTART, this is a continuation of existing transaction
*/
extern I2C_Status I2C_do_transaction( I2C_INTERRUPT_MODE en_int,
- I2C_TRANSACTION_MODE act,
- unsigned char i2c_addr,
- unsigned char data_addr,
- int len,
- char *buffer,
- I2C_STOP_MODE stop,
- int retry,
- I2C_RESTART_MODE rsta);
+ I2C_TRANSACTION_MODE act,
+ unsigned char i2c_addr,
+ unsigned char data_addr,
+ int len,
+ char *buffer,
+ I2C_STOP_MODE stop,
+ int retry,
+ I2C_RESTART_MODE rsta);
#endif
diff --git a/cpu/mpc824x/drivers/i2o.h b/cpu/mpc824x/drivers/i2o.h
index 87225ab..c47253d 100644
--- a/cpu/mpc824x/drivers/i2o.h
+++ b/cpu/mpc824x/drivers/i2o.h
@@ -123,11 +123,11 @@
PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
**/
extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ); /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned char n ); /* b'1' - msg 0
+ * b'10'- msg 1
+ * b'11'- both
+ */
/**
Disable the interrupt associated with in/out bound msg
@@ -137,11 +137,11 @@
PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
**/
extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ); /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned char n ); /* b'1' - msg 0
+ * b'10'- msg 1
+ * b'11'- both
+ */
/**
Read the msg register either from local inbound msg 0/1,
@@ -154,9 +154,9 @@
Otherwise local inbound msg is read.
**/
extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int *msg );
+ unsigned int base, /*pcsrbar/eumbbar */
+ unsigned int n, /* 0 or 1 */
+ unsigned int *msg );
/**
Write to nth Msg register either on local outbound msg 0/1,
@@ -169,9 +169,9 @@
Otherwise local outbound msg is written.
**/
extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int msg );
+ unsigned int base, /*pcsrbar/eumbbar */
+ unsigned int n, /* 0 or 1 */
+ unsigned int msg );
/**
Enable the In/Out DoorBell Interrupt
@@ -183,8 +183,8 @@
PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
**/
extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
/**
Disable the In/Out DoorBell Interrupt
@@ -195,8 +195,8 @@
**/
extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
/**
Read a local indoorbell register, or an outdoorbell of devices.
@@ -209,7 +209,7 @@
Otherwise local in doorbell is read
**/
extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */
- unsigned int base); /* pcsrbar/eumbbar */
+ unsigned int base); /* pcsrbar/eumbbar */
/**
Write to a local outdoorbell register, or an indoorbell register of devices.
@@ -221,8 +221,8 @@
Otherwise local out doorbell is written
**/
extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int msg ); /* in / out */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int msg ); /* in / out */
/**
Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
@@ -251,8 +251,8 @@
MUCR.
**/
extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
- QUEUE_SIZE,
- unsigned int qba);/* queue base address that must be aligned at 1M */
+ QUEUE_SIZE,
+ unsigned int qba);/* queue base address that must be aligned at 1M */
/**
Enable the circular queue
**/
@@ -296,8 +296,8 @@
Unless both free queues are initialized, allocating a free MF will return 0xffffffff
**/
extern I2OSTATUS I2OFIFOAlloc( LOCATION,
- unsigned int base,
- void **pMsg);
+ unsigned int base,
+ void **pMsg);
/**
Free a used msg frame back to free queue
PCI Master frees a MFA through outbound queue port of device(OFQPR)
@@ -310,8 +310,8 @@
and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
**/
extern I2OSTATUS I2OFIFOFree( LOCATION,
- unsigned int base,
- void *pMsg );
+ unsigned int base,
+ void *pMsg );
/**
Post a msg into FIFO
@@ -322,8 +322,8 @@
Otherwise queue overflow interrupt will assert.
**/
extern I2OSTATUS I2OFIFOPost( LOCATION,
- unsigned int base,
- void *pMsg );
+ unsigned int base,
+ void *pMsg );
/**
Read a msg from FIFO
@@ -331,14 +331,14 @@
while local processor reads a msg from its inbound post queue(IPTPR)
**/
extern I2OSTATUS I2OFIFOGet( LOCATION,
- unsigned int base,
+ unsigned int base,
void **pMsg );
/**
Get the I2O PCI configuration identification register
**/
extern I2OSTATUS I2OPCIConfigGet( LOCATION,
- unsigned int base,
+ unsigned int base,
I2OIOP *);
#endif
diff --git a/cpu/mpc824x/drivers/i2o/i2o.h b/cpu/mpc824x/drivers/i2o/i2o.h
index 26f7c5c..71572b2 100644
--- a/cpu/mpc824x/drivers/i2o/i2o.h
+++ b/cpu/mpc824x/drivers/i2o/i2o.h
@@ -124,11 +124,11 @@
PCI master needs to enable the devices' outbound interrupts it wants to handle (REMOTE)
**/
extern I2OSTATUS I2OMsgEnable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ); /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned char n ); /* b'1' - msg 0
+ * b'10'- msg 1
+ * b'11'- both
+ */
/**
Disable the interrupt associated with in/out bound msg
@@ -138,11 +138,11 @@
PCI master needs to disable outbound interrupts of devices it is not interested (REMOTE)
**/
extern I2OSTATUS I2OMsgDisable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ); /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
- */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned char n ); /* b'1' - msg 0
+ * b'10'- msg 1
+ * b'11'- both
+ */
/**
Read the msg register either from local inbound msg 0/1,
@@ -155,9 +155,9 @@
Otherwise local inbound msg is read.
**/
extern I2OSTATUS I2OMsgGet ( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int *msg );
+ unsigned int base, /*pcsrbar/eumbbar */
+ unsigned int n, /* 0 or 1 */
+ unsigned int *msg );
/**
Write to nth Msg register either on local outbound msg 0/1,
@@ -170,9 +170,9 @@
Otherwise local outbound msg is written.
**/
extern I2OSTATUS I2OMsgPost( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int msg );
+ unsigned int base, /*pcsrbar/eumbbar */
+ unsigned int n, /* 0 or 1 */
+ unsigned int msg );
/**
Enable the In/Out DoorBell Interrupt
@@ -184,8 +184,8 @@
PCI master needs to enable outbound doorbell interrupts of the devices it wants to handle
**/
extern I2OSTATUS I2ODBEnable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int in_db );/* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
/**
Disable the In/Out DoorBell Interrupt
@@ -196,8 +196,8 @@
**/
extern I2OSTATUS I2ODBDisable( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int in_db ); /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
/**
Read a local indoorbell register, or an outdoorbell of devices.
@@ -210,7 +210,7 @@
Otherwise local in doorbell is read
**/
extern unsigned int I2ODBGet( LOCATION, /* REMOTE/LOCAL */
- unsigned int base); /* pcsrbar/eumbbar */
+ unsigned int base); /* pcsrbar/eumbbar */
/**
Write to a local outdoorbell register, or an indoorbell register of devices.
@@ -222,8 +222,8 @@
Otherwise local out doorbell is written
**/
extern void I2ODBPost( LOCATION, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int msg ); /* in / out */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int msg ); /* in / out */
/**
Read the outbound msg unit interrupt status of devices. Reading an interrupt status register,
@@ -252,8 +252,8 @@
MUCR.
**/
extern I2OSTATUS I2OFIFOInit( unsigned int eumbbar,
- QUEUE_SIZE,
- unsigned int qba);/* queue base address that must be aligned at 1M */
+ QUEUE_SIZE,
+ unsigned int qba);/* queue base address that must be aligned at 1M */
/**
Enable the circular queue
**/
@@ -297,8 +297,8 @@
Unless both free queues are initialized, allocating a free MF will return 0xffffffff
**/
extern I2OSTATUS I2OFIFOAlloc( LOCATION,
- unsigned int base,
- void **pMsg);
+ unsigned int base,
+ void **pMsg);
/**
Free a used msg frame back to free queue
PCI Master frees a MFA through outbound queue port of device(OFQPR)
@@ -311,8 +311,8 @@
and by device to initialize Outbound free queue before I2OFIFOAlloc can be used.
**/
extern I2OSTATUS I2OFIFOFree( LOCATION,
- unsigned int base,
- void *pMsg );
+ unsigned int base,
+ void *pMsg );
/**
Post a msg into FIFO
@@ -323,8 +323,8 @@
Otherwise queue overflow interrupt will assert.
**/
extern I2OSTATUS I2OFIFOPost( LOCATION,
- unsigned int base,
- void *pMsg );
+ unsigned int base,
+ void *pMsg );
/**
Read a msg from FIFO
@@ -332,14 +332,14 @@
while local processor reads a msg from its inbound post queue(IPTPR)
**/
extern I2OSTATUS I2OFIFOGet( LOCATION,
- unsigned int base,
+ unsigned int base,
void **pMsg );
/**
Get the I2O PCI configuration identification register
**/
extern I2OSTATUS I2OPCIConfigGet( LOCATION,
- unsigned int base,
+ unsigned int base,
I2OIOP *);
#endif
diff --git a/cpu/mpc824x/drivers/i2o/i2o1.c b/cpu/mpc824x/drivers/i2o/i2o1.c
index d840af0..f058151 100644
--- a/cpu/mpc824x/drivers/i2o/i2o1.c
+++ b/cpu/mpc824x/drivers/i2o/i2o1.c
@@ -34,10 +34,10 @@
* PCI master needs to enable the outbound interrupts of devices it wants to handle(REMOTE)
************************************************************************************/
I2OSTATUS I2OMsgEnable ( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ) /* b'1' - msg 0
- * b'10'- msg 1
- * b'11'- both
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned char n ) /* b'1' - msg 0
+ * b'10'- msg 1
+ * b'11'- both
*/
{
unsigned int reg, val;
@@ -73,8 +73,8 @@
* PCI master needs to disable outbound interrupts of devices it is not interested(REMOTE)
*********************************************************************************/
I2OSTATUS I2OMsgDisable( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned char n ) /* b'1' - msg 0
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned char n ) /* b'1' - msg 0
* b'10'- msg 1
* b'11'- both
*/
@@ -114,9 +114,9 @@
* If it is remote, outbound msg on the device is read; otherwise local inbound msg is read
*************************************************************************/
I2OSTATUS I2OMsgGet ( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int *msg )
+ unsigned int base, /*pcsrbar/eumbbar */
+ unsigned int n, /* 0 or 1 */
+ unsigned int *msg )
{
if ( n >= I2O_NUM_MSG || msg == 0 )
{
@@ -151,9 +151,9 @@
* If it is remote, inbound msg on the device is written; otherwise local outbound msg is written
***************************************************************/
I2OSTATUS I2OMsgPost( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /*pcsrbar/eumbbar */
- unsigned int n, /* 0 or 1 */
- unsigned int msg )
+ unsigned int base, /*pcsrbar/eumbbar */
+ unsigned int n, /* 0 or 1 */
+ unsigned int msg )
{
if ( n >= I2O_NUM_MSG )
{
@@ -190,8 +190,8 @@
* PCI master needs to enable the outbound doorbell interrupts of device it wants to handle
**********************************************************************/
I2OSTATUS I2ODBEnable( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
{
/* LOCATION - REMOTE : PCI master initializes outbound doorbell message of device
@@ -209,15 +209,15 @@
/* pcsrbar is base */
val = load_runtime_reg( base, I2O_OMIMR );
val &= 0xfffffff7;
- store_runtime_reg( base, I2O_OMIMR , val );
+ store_runtime_reg( base, I2O_OMIMR , val );
}
else
{
/* eumbbar is base */
val = load_runtime_reg( base, I2O_IMIMR);
- in_db = ( (~in_db) & 0x3 ) << 3;
- val = ( val & 0xffffffe7) | in_db;
- store_runtime_reg( base, I2O_IMIMR, val );
+ in_db = ( (~in_db) & 0x3 ) << 3;
+ val = ( val & 0xffffffe7) | in_db;
+ store_runtime_reg( base, I2O_IMIMR, val );
}
return I2OSUCCESS;
@@ -237,8 +237,8 @@
* PCI master needs to disable outbound doorbell interrupts of device it is not interested
************************************************************************************/
I2OSTATUS I2ODBDisable( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int in_db ) /* when LOCAL, I2O_IN_DB, MC, I2O_IN_DB|MC */
{
/* LOCATION - REMOTE : handle device's out bound message initialization
* LOCAL : handle local in bound message initialization
@@ -255,14 +255,14 @@
/* pcsrbar is the base */
val = load_runtime_reg( base, I2O_OMIMR );
val |= 0x8;
- store_runtime_reg( base, I2O_OMIMR, val );
+ store_runtime_reg( base, I2O_OMIMR, val );
}
else
{
val = load_runtime_reg( base, I2O_IMIMR);
- in_db = ( in_db & 0x3 ) << 3;
- val |= in_db;
- store_runtime_reg( base, I2O_IMIMR, val );
+ in_db = ( in_db & 0x3 ) << 3;
+ val |= in_db;
+ store_runtime_reg( base, I2O_IMIMR, val );
}
return I2OSUCCESS;
@@ -287,22 +287,22 @@
* will cause interrupt pending.
*********************************************************************************/
unsigned int I2ODBGet( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base) /* pcsrbar/eumbbar */
+ unsigned int base) /* pcsrbar/eumbbar */
{
unsigned int msg, val;
if ( loc == REMOTE )
{
/* read outbound doorbell register of device, pcsrbar is the base */
- val = load_runtime_reg( base, I2O_ODBR );
- msg = val & 0xe0000000;
- store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */
+ val = load_runtime_reg( base, I2O_ODBR );
+ msg = val & 0xe0000000;
+ store_runtime_reg( base, I2O_ODBR, val ); /* clear the register */
}
else
{
/* read the inbound doorbell register, eumbbar is the base */
- val = load_runtime_reg( base, I2O_IDBR );
- store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */
+ val = load_runtime_reg( base, I2O_IDBR );
+ store_runtime_reg( base, I2O_IDBR, val ); /* clear the register */
msg = val;
}
@@ -323,8 +323,8 @@
* Otherwise local out doorbell is written
*********************************************************************/
void I2ODBPost( LOCATION loc, /* REMOTE/LOCAL */
- unsigned int base, /* pcsrbar/eumbbar */
- unsigned int msg ) /* in / out */
+ unsigned int base, /* pcsrbar/eumbbar */
+ unsigned int msg ) /* in / out */
{
if ( loc == REMOTE )
{
@@ -527,8 +527,8 @@
*
****************************************************/
I2OSTATUS I2OFIFOAlloc( LOCATION loc,
- unsigned int base,
- void **pMsg )
+ unsigned int base,
+ void **pMsg )
{
I2OSTATUS stat = I2OSUCCESS;
void *pHdr, *pTil;
@@ -543,12 +543,12 @@
{
/* pcsrbar is the base and read the inbound free tail ptr */
pTil = (void *)load_runtime_reg( base, I2O_IFQPR );
- if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
- {
+ if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
+ {
stat = I2OQUEEMPTY;
- }
+ }
else
- {
+ {
*pMsg = pTil;
}
}
@@ -562,7 +562,7 @@
if ( pHdr == pTil )
{
/* hdr and til point to the same fifo item, no free MFA */
- stat = I2OQUEEMPTY;
+ stat = I2OQUEEMPTY;
}
else
{
@@ -615,7 +615,7 @@
{
/* eumbbar is the base */
pHdr = (void **)load_runtime_reg( base, I2O_IFHPR );
- pTil = (void **)load_runtime_reg( base, I2O_IFTPR );
+ pTil = (void **)load_runtime_reg( base, I2O_IFTPR );
/* store MFA */
*pHdr = pMsg;
@@ -633,7 +633,7 @@
if ( pHdr != pTil )
{
store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr);
- }
+ }
else
{
stat = I2OQUEFULL;
@@ -677,7 +677,7 @@
{
/* eumbbar is the base */
pHdr = (void **)load_runtime_reg( base, I2O_OPHPR );
- pTil = (void **)load_runtime_reg( base, I2O_OPTPR );
+ pTil = (void **)load_runtime_reg( base, I2O_OPTPR );
/* store MFA */
*pHdr = pMsg;
@@ -695,7 +695,7 @@
if ( pHdr != pTil )
{
store_runtime_reg( base, I2O_OPHPR, (unsigned int)pHdr);
- }
+ }
else
{
stat = I2OQUEFULL;
@@ -734,12 +734,12 @@
{
/* pcsrbar is the base */
pTil = (void *)load_runtime_reg( base, I2O_OFQPR );
- if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
- {
+ if ( ( (unsigned int)pTil & 0xFFFFFFF ) == 0xFFFFFFFF )
+ {
stat = I2OQUEEMPTY;
- }
+ }
else
- {
+ {
*pMsg = pTil;
}
}
@@ -753,7 +753,7 @@
if ( pHdr == pTil )
{
/* no free MFA */
- stat = I2OQUEEMPTY;
+ stat = I2OQUEEMPTY;
}
else
{
@@ -783,8 +783,8 @@
* should pass eumbbar.
*********************************************************/
I2OSTATUS I2OPCIConfigGet( LOCATION loc,
- unsigned int base,
- I2OIOP * val)
+ unsigned int base,
+ I2OIOP * val)
{
unsigned int tmp;
if ( val == 0 )
diff --git a/cpu/mpc824x/drivers/i2o/i2o2.S b/cpu/mpc824x/drivers/i2o/i2o2.S
index 1033979..990f9ef 100644
--- a/cpu/mpc824x/drivers/i2o/i2o2.S
+++ b/cpu/mpc824x/drivers/i2o/i2o2.S
@@ -19,12 +19,12 @@
load_runtime_reg:
xor r5,r5,r5
- or r5,r5,r3 /* save eumbbar */
+ or r5,r5,r3 /* save eumbbar */
lwbrx r3,r4,r5
sync
- bclr 20, 0
+ bclr 20, 0
/****************************************************************
* function: store_runtime_reg
@@ -34,9 +34,9 @@
* r5 - new value to be stored
*
****************************************************************/
- .text
- .align 2
- .global store_runtime_reg
+ .text
+ .align 2
+ .global store_runtime_reg
store_runtime_reg:
xor r0,r0,r0
@@ -45,4 +45,3 @@
sync
bclr 20,0
-
diff --git a/cpu/mpc824x/interrupts.c b/cpu/mpc824x/interrupts.c
index 12841b3..753575f 100644
--- a/cpu/mpc824x/interrupts.c
+++ b/cpu/mpc824x/interrupts.c
@@ -83,12 +83,12 @@
{
decrementer_count = (get_bus_freq (0) / 4) / CFG_HZ;
- /*
- * It's all broken at the moment and I currently don't need
- * interrupts. If you want to fix it, have a look at the epic
- * drivers in dink32 v12. They do everthing and Motorola said
- * I could use the dink source in this project as long as
- * copyright notices remain intact.
+ /*
+ * It's all broken at the moment and I currently don't need
+ * interrupts. If you want to fix it, have a look at the epic
+ * drivers in dink32 v12. They do everthing and Motorola said
+ * I could use the dink source in this project as long as
+ * copyright notices remain intact.
*/
epicInit (EPIC_DIRECT_IRQ, 0);
diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S
index 004e3b3..b1cdb84 100644
--- a/cpu/mpc824x/start.S
+++ b/cpu/mpc824x/start.S
@@ -202,7 +202,6 @@
bl board_init_f /* run 1st part of board init code (from Flash) */
-
.globl _start_of_vectors
_start_of_vectors:
@@ -840,5 +839,3 @@
blt 1b
blr
-
-
diff --git a/cpu/mpc8260/bedbug_603e.c b/cpu/mpc8260/bedbug_603e.c
index 1ca057f..9c29b35 100644
--- a/cpu/mpc8260/bedbug_603e.c
+++ b/cpu/mpc8260/bedbug_603e.c
@@ -5,8 +5,7 @@
#include <common.h>
#include <command.h>
#include <linux/ctype.h>
-
-#include <cmd_bedbug.h>
+#include <bedbug/type.h>
#include <bedbug/bedbug.h>
#include <bedbug/regs.h>
#include <bedbug/ppc.h>
@@ -64,7 +63,7 @@
* ====================================================================== */
void bedbug603e_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
- char *argv[])
+ char *argv[])
{
long addr; /* Address to break at */
int which_bp; /* Breakpoint number */
@@ -116,8 +115,8 @@
/* Set a breakpoint at the address */
if(!(( isdigit( argv[ 1 ][ 0 ] )) ||
- (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) ||
- (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' ))))
+ (( argv[ 1 ][ 0 ] >= 'a' ) && ( argv[ 1 ][ 0 ] <= 'f' )) ||
+ (( argv[ 1 ][ 0 ] >= 'A' ) && ( argv[ 1 ][ 0 ] <= 'F' ))))
{
printf ("Usage:\n%s\n", cmdtp->usage);
return;
@@ -236,4 +235,3 @@
/* ====================================================================== */
#endif
-
diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
index b8ba48c..7662fc6 100644
--- a/cpu/mpc8260/cpu.c
+++ b/cpu/mpc8260/cpu.c
@@ -180,7 +180,7 @@
/* ------------------------------------------------------------------------- */
int
-do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
ulong msr, addr;
diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c
index d0545cf..fd09a8d 100644
--- a/cpu/mpc8260/cpu_init.c
+++ b/cpu/mpc8260/cpu_init.c
@@ -70,13 +70,13 @@
uint tpmsk = ~pmsk;
/*
- * the (somewhat confused) paragraph at the
- * bottom of page 35-5 warns that there might
- * be "unknown behaviour" when programming
- * PSORx and PDIRx, if PPARx = 1, so I
- * decided this meant I had to disable the
- * dedicated function first, and enable it
- * last.
+ * the (somewhat confused) paragraph at the
+ * bottom of page 35-5 warns that there might
+ * be "unknown behaviour" when programming
+ * PSORx and PDIRx, if PPARx = 1, so I
+ * decided this meant I had to disable the
+ * dedicated function first, and enable it
+ * last.
*/
iop->ppar &= tpmsk;
iop->psor = (iop->psor & tpmsk) | psor;
diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c
index 8b6af31..10133fa 100644
--- a/cpu/mpc8260/ether_scc.c
+++ b/cpu/mpc8260/ether_scc.c
@@ -43,31 +43,31 @@
# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE
# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK
# define CMXSCR_MASK (CMXSCR_SC1 |\
- CMXSCR_RS1CS_MSK |\
- CMXSCR_TS1CS_MSK)
+ CMXSCR_RS1CS_MSK |\
+ CMXSCR_TS1CS_MSK)
#elif (CONFIG_ETHER_INDEX == 2)
# define PROFF_ENET PROFF_SCC2
# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE
# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK
# define CMXSCR_MASK (CMXSCR_SC2 |\
- CMXSCR_RS2CS_MSK |\
- CMXSCR_TS2CS_MSK)
+ CMXSCR_RS2CS_MSK |\
+ CMXSCR_TS2CS_MSK)
#elif (CONFIG_ETHER_INDEX == 3)
# define PROFF_ENET PROFF_SCC3
# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE
# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK
# define CMXSCR_MASK (CMXSCR_SC3 |\
- CMXSCR_RS3CS_MSK |\
- CMXSCR_TS3CS_MSK)
+ CMXSCR_RS3CS_MSK |\
+ CMXSCR_TS3CS_MSK)
#elif (CONFIG_ETHER_INDEX == 4)
# define PROFF_ENET PROFF_SCC4
# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE
# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK
# define CMXSCR_MASK (CMXSCR_SC4 |\
- CMXSCR_RS4CS_MSK |\
- CMXSCR_TS4CS_MSK)
+ CMXSCR_RS4CS_MSK |\
+ CMXSCR_TS4CS_MSK)
#endif
@@ -104,27 +104,27 @@
int result = 0;
if (length <= 0) {
- printf("scc: bad packet size: %d\n", length);
- goto out;
+ printf("scc: bad packet size: %d\n", length);
+ goto out;
}
for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= TOUT_LOOP) {
- printf("scc: tx buffer not ready\n");
- goto out;
- }
+ if (i >= TOUT_LOOP) {
+ printf("scc: tx buffer not ready\n");
+ goto out;
+ }
}
rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
rtx->txbd[txIdx].cbd_datlen = length;
rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
- BD_ENET_TX_WRAP);
+ BD_ENET_TX_WRAP);
for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
- if (i >= TOUT_LOOP) {
- printf("scc: tx error\n");
- goto out;
- }
+ if (i >= TOUT_LOOP) {
+ printf("scc: tx error\n");
+ goto out;
+ }
}
/* return only status bits */
@@ -141,37 +141,37 @@
for (;;)
{
- if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
- length = -1;
- break; /* nothing received - leave for() loop */
- }
+ if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+ length = -1;
+ break; /* nothing received - leave for() loop */
+ }
- length = rtx->rxbd[rxIdx].cbd_datlen;
+ length = rtx->rxbd[rxIdx].cbd_datlen;
- if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
- {
- printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
- }
- else
- {
- /* Pass the packet up to the protocol layers. */
- NetReceive(NetRxPackets[rxIdx], length - 4);
- }
+ if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
+ {
+ printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
+ }
+ else
+ {
+ /* Pass the packet up to the protocol layers. */
+ NetReceive(NetRxPackets[rxIdx], length - 4);
+ }
- /* Give the buffer back to the SCC. */
- rtx->rxbd[rxIdx].cbd_datlen = 0;
+ /* Give the buffer back to the SCC. */
+ rtx->rxbd[rxIdx].cbd_datlen = 0;
- /* wrap around buffer index when necessary */
- if ((rxIdx + 1) >= PKTBUFSRX) {
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
- BD_ENET_RX_EMPTY);
- rxIdx = 0;
- }
- else {
- rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
- rxIdx++;
- }
+ /* wrap around buffer index when necessary */
+ if ((rxIdx + 1) >= PKTBUFSRX) {
+ rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
+ BD_ENET_RX_EMPTY);
+ rxIdx = 0;
+ }
+ else {
+ rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+ rxIdx++;
+ }
}
return length;
}
@@ -201,7 +201,7 @@
/* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
immr->im_cpmux.cmx_uar = 0;
immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
- CFG_CMXSCR_VALUE);
+ CFG_CMXSCR_VALUE);
/* 24.21 (6) write RBASE and TBASE to parameter RAM */
@@ -221,9 +221,9 @@
/* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
- CPM_CR_ENET_SBLOCK,
- 0x0c,
- CPM_CR_INIT_TRX) | CPM_CR_FLG;
+ CPM_CR_ENET_SBLOCK,
+ 0x0c,
+ CPM_CR_INIT_TRX) | CPM_CR_FLG;
/* 24.21 - (8-18): Set up parameter RAM */
pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
@@ -266,9 +266,9 @@
/* 24.21 - (19): Initialize RxBD */
for (i = 0; i < PKTBUFSRX; i++)
{
- rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
- rtx->rxbd[i].cbd_datlen = 0; /* Reset */
- rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+ rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+ rtx->rxbd[i].cbd_datlen = 0; /* Reset */
+ rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
}
rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
@@ -276,11 +276,11 @@
/* 24.21 - (20): Initialize TxBD */
for (i = 0; i < TX_BUF_CNT; i++)
{
- rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD |
- BD_ENET_TX_LAST |
- BD_ENET_TX_TC);
- rtx->txbd[i].cbd_datlen = 0; /* Reset */
- rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
+ rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD |
+ BD_ENET_TX_LAST |
+ BD_ENET_TX_TC);
+ rtx->txbd[i].cbd_datlen = 0; /* Reset */
+ rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
}
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
@@ -290,8 +290,8 @@
/* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
- SCCE_ENET_RXF |
- SCCE_ENET_TXB);
+ SCCE_ENET_RXF |
+ SCCE_ENET_TXB);
/* 24.21 - (23): we don't use ethernet interrupts */
@@ -300,9 +300,9 @@
/* 24.21 - (25): Clear GSMR_L to enable normal operations */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI |
- SCC_GSMRL_TPL_48 |
- SCC_GSMRL_TPP_10 |
- SCC_GSMRL_MODE_ENET);
+ SCC_GSMRL_TPL_48 |
+ SCC_GSMRL_TPP_10 |
+ SCC_GSMRL_MODE_ENET);
/* 24.21 - (26): Initialize DSR */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
@@ -331,18 +331,17 @@
/* 24.21 - (28): Write to GSMR_L to enable SCC */
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
- SCC_GSMRL_ENT);
+ SCC_GSMRL_ENT);
return 0;
}
-
void eth_halt(void)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
- SCC_GSMRL_ENT);
+ SCC_GSMRL_ENT);
}
#if 0
@@ -350,9 +349,8 @@
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
- SCC_GSMRL_ENT);
+ SCC_GSMRL_ENT);
}
#endif
#endif /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */
-
diff --git a/cpu/mpc8260/i2c.c b/cpu/mpc8260/i2c.c
index 69ae535..789c514 100644
--- a/cpu/mpc8260/i2c.c
+++ b/cpu/mpc8260/i2c.c
@@ -223,7 +223,7 @@
volatile I2C_BD *rxbd, *txbd;
uint dpaddr;
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CFG_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
@@ -494,7 +494,7 @@
volatile iic_t *iip;
volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
volatile I2C_BD *txbd, *rxbd;
- int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
+ int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
uint dpaddr;
PRINTD(("[I2C] i2c_doio\n"));
@@ -543,7 +543,7 @@
rxbd = ((I2C_BD*)state->rxbd) - n;
for (i = 0; i < n; i++) {
- rxtimeo += TOUT_LOOP * rxbd->length;
+ rxtimeo += TOUT_LOOP * rxbd->length;
rxbd++;
}
@@ -670,7 +670,7 @@
* and the extra bits end up in the "chip address" bit slots.
* This makes a 24WC08 (1Kbyte) chip look like four 256 byte
* chips.
- *
+ *
* Note that we consider the length of the address field to still
* be one byte because the extra address bits are hidden in the
* chip address.
@@ -719,7 +719,7 @@
* and the extra bits end up in the "chip address" bit slots.
* This makes a 24WC08 (1Kbyte) chip look like four 256 byte
* chips.
- *
+ *
* Note that we consider the length of the address field to still
* be one byte because the extra address bits are hidden in the
* chip address.
diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c
index ac77c16..b3a89f5 100644
--- a/cpu/mpc8260/pci.c
+++ b/cpu/mpc8260/pci.c
@@ -35,7 +35,7 @@
*
* 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
* 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
- *
+ *
* 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
* PCI Mem with prefetch
*
@@ -44,7 +44,7 @@
*
* 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
* 32-bit PCI IO
- *
+ *
* PCI->Local map (from PCI)
* MPC826x slave window controlled by
*
@@ -52,15 +52,15 @@
* MPC826x local memory
*/
-/*
- * Slave window that allows PCI masters to access MPC826x local memory.
+/*
+ * Slave window that allows PCI masters to access MPC826x local memory.
* This window is set up using the first set of Inbound ATU registers
*/
-#ifndef CFG_PCI_SLV_MEM_LOCAL
-#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
-#else
-#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
+#ifndef CFG_PCI_SLV_MEM_LOCAL
+#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
+#else
+#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
#endif
#ifndef CFG_PCI_SLV_MEM_BUS
@@ -71,22 +71,22 @@
#ifndef CFG_PICMR0_MASK_ATTRIB
#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
- PICMR_PREFETCH_EN)
+ PICMR_PREFETCH_EN)
#else
#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
#endif
-/*
+/*
* These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI
- * prefetch, non prefetch, and IO space (see below), must all fit within
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
* these windows.
*/
/* PCIBR0 */
#ifndef CFG_PCI_MSTR0_LOCAL
-#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
-#else
+#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
+#else
#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
#endif
@@ -98,9 +98,9 @@
/* PCIBR1 */
#ifndef CFG_PCI_MSTR1_LOCAL
-#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
-#else
-#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
+#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
+#else
+#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
#endif
#ifndef CFG_PCIMSK1_MASK
@@ -109,7 +109,7 @@
#define PCIMSK1_MASK CFG_PCIMSK1_MASK
#endif
-/*
+/*
* Master window that allows the CPU to access PCI Memory (prefetch).
* This window will be setup with the first set of Outbound ATU registers
* in the bridge.
@@ -145,34 +145,34 @@
#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
#endif
-/*
+/*
* Master window that allows the CPU to access PCI Memory (non-prefetch).
* This window will be setup with the second set of Outbound ATU registers
* in the bridge.
*/
-#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
-#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
-#else
-#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
+#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
+#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
+#else
+#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
#endif
-#ifndef CFG_PCI_MSTR_MEMIO_BUS
-#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
-#else
-#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
+#ifndef CFG_PCI_MSTR_MEMIO_BUS
+#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
+#else
+#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
#endif
-#ifndef CFG_CPU_PCI_MEMIO_START
-#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
-#else
-#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
+#ifndef CFG_CPU_PCI_MEMIO_START
+#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
+#else
+#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
#endif
-#ifndef CFG_PCI_MSTR_MEMIO_SIZE
-#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
-#else
-#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
+#ifndef CFG_PCI_MSTR_MEMIO_SIZE
+#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
+#else
+#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
#endif
#ifndef CFG_POCMR1_MASK_ATTRIB
@@ -181,34 +181,34 @@
#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
#endif
-/*
+/*
* Master window that allows the CPU to access PCI IO space.
* This window will be setup with the third set of Outbound ATU registers
* in the bridge.
*/
-#ifndef CFG_PCI_MSTR_IO_LOCAL
-#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
-#else
-#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
+#ifndef CFG_PCI_MSTR_IO_LOCAL
+#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
+#else
+#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
#endif
-#ifndef CFG_PCI_MSTR_IO_BUS
-#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
-#else
-#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
+#ifndef CFG_PCI_MSTR_IO_BUS
+#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
+#else
+#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
#endif
-#ifndef CFG_CPU_PCI_IO_START
-#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
-#else
-#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
+#ifndef CFG_CPU_PCI_IO_START
+#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
+#else
+#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
#endif
-#ifndef CFG_PCI_MSTR_IO_SIZE
-#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
-#else
-#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
+#ifndef CFG_PCI_MSTR_IO_SIZE
+#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
+#else
+#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
#endif
#ifndef CFG_POCMR2_MASK_ATTRIB
@@ -239,7 +239,7 @@
pci_dev_t host_devno = PCI_BDF(0, 0, 0);
pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
- CFG_IMMR + PCI_CFG_DATA_REG);
+ CFG_IMMR + PCI_CFG_DATA_REG);
/*
* Setting required to enable local bus for PCI (SIUMCR [LBPC]).
@@ -248,23 +248,23 @@
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
#else
- /*
- * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+ /*
+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
* and local bus for PCI (SIUMCR [LBPC]).
*/
- immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
- ~SIUMCR_LBPC11 &
- ~SIUMCR_CS10PC11 &
+ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~SIUMCR_LBPC11 &
+ ~SIUMCR_CS10PC11 &
~SIUMCR_LBPC11) |
- SIUMCR_LBPC01 |
- SIUMCR_CS10PC01 |
+ SIUMCR_LBPC01 |
+ SIUMCR_CS10PC01 |
SIUMCR_LBPC01;
#endif
/* Make PCI lowest priority */
- /* Each 4 bits is a device bus request and the MS 4bits
+ /* Each 4 bits is a device bus request and the MS 4bits
is highest priority */
- /* Bus 4bit value
+ /* Bus 4bit value
--- ----------
CPM high 0b0000
CPM middle 0b0001
@@ -282,8 +282,8 @@
/* Park bus on core while modifying PCI Bus accesses */
immap->im_siu_conf.sc_ppc_acr = 0x6;
- /*
- * Set up master windows that allow the CPU to access PCI space. These
+ /*
+ * Set up master windows that allow the CPU to access PCI space. These
* windows are set up using the two SIU PCIBR registers.
*/
*(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
@@ -294,40 +294,40 @@
*(volatile unsigned long*)(immr_addr + M8265_PCIMSK1) = PCIMSK1_MASK;
*(volatile unsigned long*)(immr_addr + M8265_PCIBR1) =
PCI_MSTR1_LOCAL | PCIBR_ENABLE;
-#endif
+#endif
/* Release PCI RST (by default the PCI RST signal is held low) */
pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
/* give it some time */
{
-#ifdef CONFIG_MPC8266ADS
- /* Give the PCI cards more time to initialize before query
+#ifdef CONFIG_MPC8266ADS
+ /* Give the PCI cards more time to initialize before query
This might be good for other boards also
*/
- int i;
- for (i = 0; i < 1000; ++i)
+ int i;
+ for (i = 0; i < 1000; ++i)
#endif
- udelay(1000);
+ udelay(1000);
}
- /*
- * Set up master window that allows the CPU to access PCI Memory (prefetch)
+ /*
+ * Set up master window that allows the CPU to access PCI Memory (prefetch)
* space. This window is set up using the first set of Outbound ATU registers.
*/
pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12); /* PCI base */
pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB); /* Size & attribute */
- /*
- * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
+ /*
+ * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
* space. This window is set up using the second set of Outbound ATU registers.
*/
pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB); /* Size & attribute */
-
- /*
+
+ /*
* Set up master window that allows the CPU to access PCI IO space. This window
* is set up using the third set of Outbound ATU registers.
*/
@@ -335,8 +335,8 @@
pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12); /* Local base */
pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB); /* Size & attribute */
- /*
- * Set up slave window that allows PCI masters to access MPC826x local memory.
+ /*
+ * Set up slave window that allows PCI masters to access MPC826x local memory.
* This window is set up using the first set of Inbound ATU registers
*/
pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12); /* Local base */
@@ -352,18 +352,18 @@
/* Host mode - specify the bridge as a host-PCI bridge */
pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE,
- PCI_CLASS_BRIDGE_CTLR);
+ PCI_CLASS_BRIDGE_CTLR);
/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort);
pci_hose_write_config_word(hose, host_devno, PCI_COMMAND,
- tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
#ifdef CONFIG_MPC8266ADS
/* do some bridge init, should be done on all 8260 based bridges */
pci_hose_write_config_byte(hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08);
pci_hose_write_config_byte(hose, host_devno, PCI_LATENCY_TIMER, 0xF8);
-#endif
+#endif
hose->first_busno = 0;
hose->last_busno = 0xff;
diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c
index ca76302..32016f2 100644
--- a/cpu/mpc8260/serial_scc.c
+++ b/cpu/mpc8260/serial_scc.c
@@ -82,7 +82,7 @@
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -196,12 +196,12 @@
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
- volatile immap_t *im;
+ volatile immap_t *im;
if (c == '\n')
serial_putc ('\r');
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
@@ -230,10 +230,10 @@
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile immap_t *im;
unsigned char c;
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
@@ -255,9 +255,9 @@
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile immap_t *im;
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
@@ -321,7 +321,7 @@
void
kgdb_serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -435,12 +435,12 @@
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
- volatile immap_t *im;
+ volatile immap_t *im;
if (c == '\n')
putDebugChar ('\r');
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
@@ -469,10 +469,10 @@
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im;
+ volatile immap_t *im;
unsigned char c;
- im = (immap_t *)CFG_IMMR;
+ im = (immap_t *)CFG_IMMR;
up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c
index b0e1ce4..0873319 100644
--- a/cpu/mpc8260/serial_smc.c
+++ b/cpu/mpc8260/serial_smc.c
@@ -74,7 +74,7 @@
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -186,7 +186,7 @@
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
if (c == '\n')
serial_putc ('\r');
@@ -220,7 +220,7 @@
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
unsigned char c;
up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
@@ -243,7 +243,7 @@
{
volatile cbd_t *rbdf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
@@ -289,7 +289,7 @@
void
kgdb_serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -401,7 +401,7 @@
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
if (c == '\n')
putDebugChar ('\r');
@@ -435,7 +435,7 @@
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
unsigned char c;
up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
diff --git a/cpu/mpc8260/spi.c b/cpu/mpc8260/spi.c
index 6a2dc8f..c1a607c 100644
--- a/cpu/mpc8260/spi.c
+++ b/cpu/mpc8260/spi.c
@@ -213,12 +213,12 @@
/***********IMPORTANT******************/
- /*
- * Setting transmit and receive buffer descriptor pointers
- * initially to rbase and tbase. Only the microcode patches
- * documentation talks about initializing this pointer. This
- * is missing from the sample I2C driver. If you dont
- * initialize these pointers, the kernel hangs.
+ /*
+ * Setting transmit and receive buffer descriptor pointers
+ * initially to rbase and tbase. Only the microcode patches
+ * documentation talks about initializing this pointer. This
+ * is missing from the sample I2C driver. If you dont
+ * initialize these pointers, the kernel hangs.
*/
spi->spi_rbptr = spi->spi_rbase;
spi->spi_tbptr = spi->spi_tbase;
diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S
index 2070ecc..d3fd865 100644
--- a/cpu/mpc8260/start.S
+++ b/cpu/mpc8260/start.S
@@ -966,8 +966,8 @@
/*
* Relocation Function, r14 point to got2+0x8000
*
- * Adjust got2 pointers, no need to check for 0, this code
- * already puts a few entries in the table.
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
@@ -981,7 +981,7 @@
bdnz 1b
/*
- * Now adjust the fixups and the pointers to the fixups
+ * Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
2: li r0,__fixup_entries@sectoff@l
diff --git a/cpu/mpc8xx/bedbug_860.c b/cpu/mpc8xx/bedbug_860.c
index b90782e..e91a100 100644
--- a/cpu/mpc8xx/bedbug_860.c
+++ b/cpu/mpc8xx/bedbug_860.c
@@ -5,11 +5,10 @@
#include <common.h>
#include <command.h>
#include <linux/ctype.h>
-
-#include <cmd_bedbug.h>
#include <bedbug/bedbug.h>
#include <bedbug/regs.h>
#include <bedbug/ppc.h>
+#include <bedbug/type.h>
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) && defined(CONFIG_8xx)
@@ -64,7 +63,7 @@
* ====================================================================== */
void bedbug860_do_break (cmd_tbl_t *cmdtp, int flag, int argc,
- char *argv[])
+ char *argv[])
{
long addr = 0; /* Address to break at */
int which_bp; /* Breakpoint number */
@@ -315,4 +314,3 @@
/* ====================================================================== */
#endif
-
diff --git a/cpu/mpc8xx/cpu.c b/cpu/mpc8xx/cpu.c
index cc73305..4e23228 100644
--- a/cpu/mpc8xx/cpu.c
+++ b/cpu/mpc8xx/cpu.c
@@ -411,8 +411,7 @@
/* ------------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc,
- char *argv[])
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong msr, addr;
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c
index d2e8408..85ba6b2 100644
--- a/cpu/mpc8xx/fec.c
+++ b/cpu/mpc8xx/fec.c
@@ -411,7 +411,6 @@
}
-
static void fec_halt(struct eth_device* dev)
{
#if 0
diff --git a/cpu/mpc8xx/i2c.c b/cpu/mpc8xx/i2c.c
index 9e8b8c7..baa3552 100644
--- a/cpu/mpc8xx/i2c.c
+++ b/cpu/mpc8xx/i2c.c
@@ -215,7 +215,7 @@
volatile I2C_BD *rxbd, *txbd;
uint dpaddr;
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CFG_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
diff --git a/cpu/mpc8xx/lcd.c b/cpu/mpc8xx/lcd.c
index fad383f..9f4b210 100644
--- a/cpu/mpc8xx/lcd.c
+++ b/cpu/mpc8xx/lcd.c
@@ -890,7 +890,7 @@
* 4-bit wide passive dual scan LCD at 4/8 Bit color.
*/
lchcr_hpc_tmp =
- (panel_info.vl_col *
+ (panel_info.vl_col *
(panel_info.vl_tft ? 8 :
(((2 - panel_info.vl_lbw) << /* 4 bit=2, 8-bit = 1 */
/* use << to mult by: single scan = 1, dual scan = 2 */
@@ -955,7 +955,7 @@
debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %02X%02X\n",
regno, &(cp->lcd_cmap[regno * 2]),
red, green, blue,
- cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
+ cp->lcd_cmap[ regno * 2 ], cp->lcd_cmap[(regno * 2) + 1]);
}
#endif /* LCD_COLOR8 */
@@ -1031,9 +1031,9 @@
#if defined(CONFIG_LWMON)
{ uchar c = pic_read (0x60);
#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CFG_POST_SYSMON)
- c |= 0x04; /* Chip Enable LCD */
+ c |= 0x04; /* Chip Enable LCD */
#else
- c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
+ c |= 0x07; /* Power on CCFL, Enable CCFL, Chip Enable LCD */
#endif
pic_write (0x60, c);
}
@@ -1069,7 +1069,7 @@
#if defined(CONFIG_LWMON)
{ uchar c = pic_read (0x60);
- c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
+ c &= ~0x07; /* Power off CCFL, Disable CCFL, Chip Disable LCD */
pic_write (0x60, c);
}
#elif defined(CONFIG_R360MPI)
diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c
index f98aad4..d711a63 100644
--- a/cpu/mpc8xx/scc.c
+++ b/cpu/mpc8xx/scc.c
@@ -168,10 +168,10 @@
/* wrap around buffer index when necessary */
if ((rxIdx + 1) >= PKTBUFSRX) {
- rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+ rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
rxIdx = 0;
} else {
- rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+ rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
rxIdx++;
}
}
@@ -212,7 +212,7 @@
#ifdef CFG_ALLOC_DPRAM
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
- dpram_alloc_align(sizeof(RTXBD), 8));
+ dpram_alloc_align(sizeof(RTXBD), 8));
#else
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
#endif /* 0 */
@@ -406,7 +406,7 @@
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = ( SCC_GSMRL_TCI | \
- SCC_GSMRL_TPL_48 | \
+ SCC_GSMRL_TPL_48 | \
SCC_GSMRL_TPP_10 | \
SCC_GSMRL_MODE_ENET);
@@ -471,7 +471,7 @@
* Port B is used to control the PHY,MC68160.
*/
immr->im_cpm.cp_pbdir |=
- (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
+ (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
@@ -532,7 +532,6 @@
}
-
static void scc_halt(struct eth_device* dev)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c
index 4e5b408..81c0279 100644
--- a/cpu/mpc8xx/serial.c
+++ b/cpu/mpc8xx/serial.c
@@ -77,7 +77,7 @@
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -231,7 +231,7 @@
{
DECLARE_GLOBAL_DATA_PTR;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
/* Set up the baud rate generator.
@@ -266,7 +266,7 @@
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
#ifdef CONFIG_MODEM_SUPPORT
@@ -305,7 +305,7 @@
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
unsigned char c;
@@ -331,7 +331,7 @@
{
volatile cbd_t *rbdf;
volatile smc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
@@ -345,7 +345,7 @@
int serial_init (void)
{
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile scc_t *sp;
volatile scc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
@@ -508,7 +508,7 @@
{
DECLARE_GLOBAL_DATA_PTR;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
/* Set up the baud rate generator.
@@ -530,7 +530,7 @@
volatile cbd_t *tbdf;
volatile char *buf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
if (c == '\n')
@@ -562,7 +562,7 @@
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
unsigned char c;
@@ -588,7 +588,7 @@
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
- volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index ef32371..e1c3400 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -114,18 +114,18 @@
/*
* PIT setup:
*
- * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
- * so the count value would be SPEED_PITC_COUNTS - 1.
- * But there would be an uncertainty in the start time of 1/4
- * count since when we enable the PIT the count is not
- * synchronized to the 32768 Hz oscillator. The trick here is
- * to start the count higher and wait until the PIT count
- * changes to the required value before starting timer 2.
+ * We want to time for SPEED_PITC_COUNTS counts (of 8192 Hz),
+ * so the count value would be SPEED_PITC_COUNTS - 1.
+ * But there would be an uncertainty in the start time of 1/4
+ * count since when we enable the PIT the count is not
+ * synchronized to the 32768 Hz oscillator. The trick here is
+ * to start the count higher and wait until the PIT count
+ * changes to the required value before starting timer 2.
*
- * One count high should be enough, but occasionally the start
- * is off by 1 or 2 counts of 32768 Hz. With the start value
- * set two counts high it seems very reliable.
- */
+ * One count high should be enough, but occasionally the start
+ * is off by 1 or 2 counts of 32768 Hz. With the start value
+ * set two counts high it seems very reliable.
+ */
immr->im_sitk.sitk_pitck = KAPWR_KEY; /* PIT initialization */
immr->im_sit.sit_pitc = SPEED_PITC_INIT;
@@ -163,10 +163,10 @@
#else /* CONFIG_8xx_GCLK_FREQ */
/*
- * If for some reason measuring the gclk frequency won't
- * work, we return the hardwired value.
- * (For example, the cogent CMA286-60 CPU module has no
- * separate oscillator for PITRTCLK)
+ * If for some reason measuring the gclk frequency won't
+ * work, we return the hardwired value.
+ * (For example, the cogent CMA286-60 CPU module has no
+ * separate oscillator for PITRTCLK)
*/
gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
diff --git a/cpu/mpc8xx/spi.c b/cpu/mpc8xx/spi.c
index f04d88e..16b3f3a 100644
--- a/cpu/mpc8xx/spi.c
+++ b/cpu/mpc8xx/spi.c
@@ -223,12 +223,12 @@
/***********IMPORTANT******************/
- /*
- * Setting transmit and receive buffer descriptor pointers
- * initially to rbase and tbase. Only the microcode patches
- * documentation talks about initializing this pointer. This
- * is missing from the sample I2C driver. If you dont
- * initialize these pointers, the kernel hangs.
+ /*
+ * Setting transmit and receive buffer descriptor pointers
+ * initially to rbase and tbase. Only the microcode patches
+ * documentation talks about initializing this pointer. This
+ * is missing from the sample I2C driver. If you dont
+ * initialize these pointers, the kernel hangs.
*/
spi->spi_rbptr = spi->spi_rbase;
spi->spi_tbptr = spi->spi_tbase;
diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S
index 3cc4ecb..81a4dc0 100644
--- a/cpu/mpc8xx/start.S
+++ b/cpu/mpc8xx/start.S
@@ -209,7 +209,6 @@
bl board_init_f /* run 1st part of board init code (from Flash) */
-
.globl _start_of_vectors
_start_of_vectors:
@@ -650,8 +649,8 @@
/*
* Relocation Function, r14 point to got2+0x8000
*
- * Adjust got2 pointers, no need to check for 0, this code
- * already puts a few entries in the table.
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
*/
li r0,__got2_entries@sectoff@l
la r3,GOT(_GOT2_TABLE_)
@@ -665,7 +664,7 @@
bdnz 1b
/*
- * Now adjust the fixups and the pointers to the fixups
+ * Now adjust the fixups and the pointers to the fixups
* in case we need to move ourselves again.
*/
2: li r0,__fixup_entries@sectoff@l
diff --git a/cpu/mpc8xx/upatch.c b/cpu/mpc8xx/upatch.c
index 99bdf53..eccff64 100644
--- a/cpu/mpc8xx/upatch.c
+++ b/cpu/mpc8xx/upatch.c
@@ -33,8 +33,8 @@
#endif
/*
- * Enable DPRAM microcode to execute from the first 512 bytes
- * and a 256 byte extension of DPRAM.
+ * Enable DPRAM microcode to execute from the first 512 bytes
+ * and a 256 byte extension of DPRAM.
*/
immr->im_cpm.cp_rccr |= 0x0001;
}
diff --git a/cpu/mpc8xx/video.c b/cpu/mpc8xx/video.c
index 9db69e1..40e65d3 100644
--- a/cpu/mpc8xx/video.c
+++ b/cpu/mpc8xx/video.c
@@ -855,13 +855,13 @@
debug ("[VIDEO CTRL] Blanking the screen...\n");
video_fill (VIDEO_BG_COL);
- /*
- * Turns on Aggressive Mode. Normally, turning on the caches
- * will cause the screen to flicker when the caches try to
- * fill. This gives the FIFO's for the Video Controller
- * higher priority and prevents flickering because of
- * underrun. This may still be an issue when using FLASH,
- * since accessing data from Flash is so slow.
+ /*
+ * Turns on Aggressive Mode. Normally, turning on the caches
+ * will cause the screen to flicker when the caches try to
+ * fill. This gives the FIFO's for the Video Controller
+ * higher priority and prevents flickering because of
+ * underrun. This may still be an issue when using FLASH,
+ * since accessing data from Flash is so slow.
*/
debug ("[VIDEO CTRL] Turning on aggressive mode...\n");
immap->im_siu_conf.sc_sdcr = 0x40;
@@ -1252,6 +1252,4 @@
return (addr);
}
-
-
#endif
diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
index b7b03ed..9639c92 100644
--- a/cpu/ppc4xx/405gp_enet.c
+++ b/cpu/ppc4xx/405gp_enet.c
@@ -218,10 +218,10 @@
/* AS.HARNOIS
* We should have :
* packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
- * In the most cases packetHandled = packetReceived, but it
- * is possible that new packets (without relationship with
- * current transfer) have got the time to arrived before
- * netloop calls eth_halt
+ * In the most cases packetHandled = packetReceived, but it
+ * is possible that new packets (without relationship with
+ * current transfer) have got the time to arrived before
+ * netloop calls eth_halt
*/
printf ("About preceeding transfer:\n"
"- Sent packet number %d\n"
@@ -251,8 +251,8 @@
tx_u_index = 0; /* Transmit User Queue Index */
#if defined(CONFIG_440)
- /* set RMII mode */
- out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
+ /* set RMII mode */
+ out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#endif /* CONFIG_440 */
/* EMAC RESET */
@@ -426,8 +426,8 @@
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440GP has a 64 byte burst length */
- out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
- out32 (EMAC_TXM1, 0xf8640000);
+ out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
+ out32 (EMAC_TXM1, 0xf8640000);
#else /* CONFIG_440 */
/* 405s have a 16 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
@@ -530,8 +530,8 @@
/* loop until either TINT turns on or 3 seconds elapse */
if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
/* transmit is done, so now check for errors
- * If there is an error, an interrupt should
- * happen when we return
+ * If there is an error, an interrupt should
+ * happen when we return
*/
time_now = get_timer (0);
if ((time_now - time_start) > 3000) {
@@ -568,16 +568,16 @@
my_uic1msr = mfdcr (uic1msr);
if (!(my_uic0msr & UIC_MRE)
- && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
- /* not for us */
+ && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
+ /* not for us */
return (rc);
}
/* get and clear controller status interrupts */
/* look at Mal and EMAC interrupts */
if ((my_uic0msr & UIC_MRE)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
- /* we have a MAL interrupt */
+ || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+ /* we have a MAL interrupt */
mal_isr = mfdcr (malesr);
/* look for mal error */
if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
@@ -595,7 +595,7 @@
}
}
if ((emac_ier & emac_isr)
- || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
+ || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (uic0sr, UIC_MRE); /* Clear */
mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
return (rc); /* we had errors so get out */
@@ -614,8 +614,8 @@
rc = 0;
}
}
- mtdcr (uic0sr, UIC_MRE); /* Clear */
- mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
+ mtdcr (uic0sr, UIC_MRE); /* Clear */
+ mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
} while (serviced);
return (rc);
@@ -866,42 +866,42 @@
#if defined(CONFIG_NET_MULTI)
int ppc_4xx_eth_initialize(bd_t *bis)
{
- struct eth_device *dev;
- int eth_num = 0;
+ struct eth_device *dev;
+ int eth_num = 0;
- dev = malloc (sizeof *dev);
- if (dev == NULL) {
- printf(__FUNCTION__ ": Cannot allocate eth_device\n");
- return (-1);
- }
+ dev = malloc (sizeof *dev);
+ if (dev == NULL) {
+ printf(__FUNCTION__ ": Cannot allocate eth_device\n");
+ return (-1);
+ }
- sprintf(dev->name, "ppc_4xx_eth%d", eth_num);
- dev->priv = (void *) eth_num;
- dev->init = ppc_4xx_eth_init;
- dev->halt = ppc_4xx_eth_halt;
- dev->send = ppc_4xx_eth_send;
- dev->recv = ppc_4xx_eth_rx;
+ sprintf(dev->name, "ppc_4xx_eth%d", eth_num);
+ dev->priv = (void *) eth_num;
+ dev->init = ppc_4xx_eth_init;
+ dev->halt = ppc_4xx_eth_halt;
+ dev->send = ppc_4xx_eth_send;
+ dev->recv = ppc_4xx_eth_rx;
- eth_register (dev);
+ eth_register (dev);
}
#else /* !defined(CONFIG_NET_MULTI) */
void eth_halt (void)
{
- ppc_4xx_eth_halt(NULL);
+ ppc_4xx_eth_halt(NULL);
}
int eth_init (bd_t *bis)
{
- return (ppc_4xx_eth_init(NULL, bis));
+ return (ppc_4xx_eth_init(NULL, bis));
}
int eth_send(volatile void *packet, int length)
{
- return (ppc_4xx_eth_send(NULL, packet, length));
+ return (ppc_4xx_eth_send(NULL, packet, length));
}
int eth_rx(void)
{
- return (ppc_4xx_eth_rx(NULL));
+ return (ppc_4xx_eth_rx(NULL));
}
#endif /* !defined(CONFIG_NET_MULTI) */
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 82142a2..4b5472b 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -71,7 +71,6 @@
#include <common.h>
#include <command.h>
-#include <cmd_boot.h>
#if !defined(CONFIG_440)
#include <405gp_pci.h>
#endif
@@ -195,7 +194,7 @@
/*--------------------------------------------------------------------------+
* PMM2 is not used. Initialize them to zero.
*--------------------------------------------------------------------------*/
- out32r(PMM2MA, (pmmma[2]&~0x1));
+ out32r(PMM2MA, (pmmma[2]&~0x1));
out32r(PMM2LA, pmmla[2]);
out32r(PMM2PCILA, pmmpcila[2]);
out32r(PMM2PCIHA, pmmpciha[2]);
@@ -303,7 +302,7 @@
struct pci_config_table *entry)
{
#ifdef DEBUG
- printf("405gp_setup_bridge\n");
+ printf("405gp_setup_bridge\n");
#endif
}
@@ -409,9 +408,9 @@
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
if( (strap & 0x00040000) == 0 ){
- printf("PCI: CPC0_STRP1[PISE] not set.\n");
- printf("PCI: Configuration aborted.\n");
- return;
+ printf("PCI: CPC0_STRP1[PISE] not set.\n");
+ printf("PCI: Configuration aborted.\n");
+ return;
}
/*--------------------------------------------------------------------------+
@@ -438,9 +437,9 @@
#if defined(CFG_PCI_PRE_INIT)
/* Let board change/modify hose & do initial checks */
if( pci_pre_init (hose) == 0 ){
- printf("PCI: Board-specific initialization failed.\n");
- printf("PCI: Configuration aborted.\n");
- return;
+ printf("PCI: Board-specific initialization failed.\n");
+ printf("PCI: Configuration aborted.\n");
+ return;
}
#endif
@@ -486,10 +485,10 @@
*--------------------------------------------------------------------------*/
if( is_pci_host(hose) ){
#ifdef CONFIG_PCI_SCAN_SHOW
- printf("PCI: Bus Dev VenId DevId Class Int\n");
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
- out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
- hose->last_busno = pci_hose_scan(hose);
+ out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
+ hose->last_busno = pci_hose_scan(hose);
}
}
diff --git a/cpu/ppc4xx/bedbug_405.c b/cpu/ppc4xx/bedbug_405.c
index eabc583..23752f3 100644
--- a/cpu/ppc4xx/bedbug_405.c
+++ b/cpu/ppc4xx/bedbug_405.c
@@ -5,8 +5,7 @@
#include <common.h>
#include <command.h>
#include <linux/ctype.h>
-
-#include <cmd_bedbug.h>
+#include <bedbug/type.h>
#include <bedbug/bedbug.h>
#include <bedbug/regs.h>
#include <bedbug/ppc.h>
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index 095a0aa..1d7c0c9 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -165,20 +165,20 @@
puts("IBM PowerPC 440 Rev. ");
switch(pvr)
{
- case PVR_440GP_RB:
+ case PVR_440GP_RB:
putc('B');
- /* See errata 1.12: CHIP_4 */
- if( ( mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0) )
- ||( mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1) ) ){
- puts("\n\t CPC0_SYSx DCRs corrupted. Resetting chip ...\n");
- udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
- do_chip_reset( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) );
- }
+ /* See errata 1.12: CHIP_4 */
+ if( ( mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0) )
+ ||( mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1) ) ){
+ puts("\n\t CPC0_SYSx DCRs corrupted. Resetting chip ...\n");
+ udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
+ do_chip_reset( mfdcr(cpc0_strp0), mfdcr(cpc0_strp1) );
+ }
break;
- case PVR_440GP_RC:
+ case PVR_440GP_RC:
putc('C');
break;
- default:
+ default:
printf("UNKNOWN (PVR=%08x)", pvr);
break;
}
@@ -192,11 +192,11 @@
/* ------------------------------------------------------------------------- */
-int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- /*
- * Initiate system reset in debug control register DBCR
- */
+ /*
+ * Initiate system reset in debug control register DBCR
+ */
__asm__ __volatile__("lis 3, 0x3000" ::: "r3");
#if defined(CONFIG_440)
__asm__ __volatile__("mtspr 0x134, 3");
diff --git a/cpu/ppc4xx/i2c.c b/cpu/ppc4xx/i2c.c
index 4bf0bbd..099d30a 100644
--- a/cpu/ppc4xx/i2c.c
+++ b/cpu/ppc4xx/i2c.c
@@ -85,7 +85,7 @@
unsigned long freqOPB;
int val, divisor;
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CFG_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
@@ -134,19 +134,19 @@
__asm__ volatile ("eieio");
- val = in8(IIC_MDCNTL);
- __asm__ volatile ("eieio");
+ val = in8(IIC_MDCNTL);
+ __asm__ volatile ("eieio");
- /* Ignore General Call, slave transfers are ignored,
- disable interrupts, exit unknown bus state, enable hold
- SCL
- 100kHz normaly or FastMode for 400kHz and above
- */
+ /* Ignore General Call, slave transfers are ignored,
+ disable interrupts, exit unknown bus state, enable hold
+ SCL
+ 100kHz normaly or FastMode for 400kHz and above
+ */
- val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
- if( speed >= 400000 ){
- val |= IIC_MDCNTL_FSM;
- }
+ val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
+ if( speed >= 400000 ){
+ val |= IIC_MDCNTL_FSM;
+ }
out8 (IIC_MDCNTL, val);
/* clear control reg */
@@ -182,153 +182,153 @@
*/
static
int i2c_transfer(unsigned char cmd_type,
- unsigned char chip,
- unsigned char addr[],
- unsigned char addr_len,
- unsigned char data[],
+ unsigned char chip,
+ unsigned char addr[],
+ unsigned char addr_len,
+ unsigned char data[],
unsigned short data_len )
{
- unsigned char* ptr;
- int reading;
- int tran,cnt;
- int result;
- int status;
- int i;
- uchar creg;
+ unsigned char* ptr;
+ int reading;
+ int tran,cnt;
+ int result;
+ int status;
+ int i;
+ uchar creg;
- if( data == 0 || data_len == 0 ){
- /*Don't support data transfer of no length or to address 0*/
- printf( "i2c_transfer: bad call\n" );
- return IIC_NOK;
- }
- if( addr && addr_len ){
- ptr = addr;
- cnt = addr_len;
- reading = 0;
- }else{
- ptr = data;
- cnt = data_len;
- reading = cmd_type;
- }
+ if( data == 0 || data_len == 0 ){
+ /*Don't support data transfer of no length or to address 0*/
+ printf( "i2c_transfer: bad call\n" );
+ return IIC_NOK;
+ }
+ if( addr && addr_len ){
+ ptr = addr;
+ cnt = addr_len;
+ reading = 0;
+ }else{
+ ptr = data;
+ cnt = data_len;
+ reading = cmd_type;
+ }
- /*Clear Stop Complete Bit*/
- out8(IIC_STS,IIC_STS_SCMP);
- /* Check init */
- i=10;
- do {
- /* Get status */
- status = in8(IIC_STS);
- __asm__ volatile("eieio");
- i--;
- } while ((status & IIC_STS_PT) && (i>0));
+ /*Clear Stop Complete Bit*/
+ out8(IIC_STS,IIC_STS_SCMP);
+ /* Check init */
+ i=10;
+ do {
+ /* Get status */
+ status = in8(IIC_STS);
+ __asm__ volatile("eieio");
+ i--;
+ } while ((status & IIC_STS_PT) && (i>0));
- if (status & IIC_STS_PT) {
- result = IIC_NOK_TOUT;
- return(result);
- }
- /*flush the Master/Slave Databuffers*/
- out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
- /*need to wait 4 OPB clocks? code below should take that long*/
+ if (status & IIC_STS_PT) {
+ result = IIC_NOK_TOUT;
+ return(result);
+ }
+ /*flush the Master/Slave Databuffers*/
+ out8(IIC_MDCNTL, ((in8(IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
+ /*need to wait 4 OPB clocks? code below should take that long*/
- /* 7-bit adressing */
- out8(IIC_HMADR,0);
- out8(IIC_LMADR, chip);
- __asm__ volatile("eieio");
+ /* 7-bit adressing */
+ out8(IIC_HMADR,0);
+ out8(IIC_LMADR, chip);
+ __asm__ volatile("eieio");
- tran = 0;
- result = IIC_OK;
- creg = 0;
+ tran = 0;
+ result = IIC_OK;
+ creg = 0;
- while ( tran != cnt && (result == IIC_OK)) {
- int bc,j;
+ while ( tran != cnt && (result == IIC_OK)) {
+ int bc,j;
- /* Control register =
- Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
- Transfer is a sequence of transfers
- */
- creg |= IIC_CNTL_PT;
-
- bc = (cnt - tran) > 4 ? 4 :
- cnt - tran;
- creg |= (bc-1)<<4;
- /* if the real cmd type is write continue trans*/
- if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
- creg |= IIC_CNTL_CHT;
-
- if (reading)
- creg |= IIC_CNTL_READ;
- else {
- for(j=0; j<bc; j++) {
- /* Set buffer */
- out8(IIC_MDBUF,ptr[tran+j]);
- __asm__ volatile("eieio");
- }
- }
- out8(IIC_CNTL, creg );
- __asm__ volatile("eieio");
-
- /* Transfer is in progress
- we have to wait for upto 5 bytes of data
- 1 byte chip address+r/w bit then bc bytes
- of data.
- udelay(10) is 1 bit time at 100khz
- Doubled for slop. 20 is too small.
+ /* Control register =
+ Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
+ Transfer is a sequence of transfers
*/
- i=2*5*8;
- do {
- /* Get status */
- status = in8(IIC_STS);
- __asm__ volatile("eieio");
- udelay (10);
- i--;
- } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
+ creg |= IIC_CNTL_PT;
+
+ bc = (cnt - tran) > 4 ? 4 :
+ cnt - tran;
+ creg |= (bc-1)<<4;
+ /* if the real cmd type is write continue trans*/
+ if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) )
+ creg |= IIC_CNTL_CHT;
+
+ if (reading)
+ creg |= IIC_CNTL_READ;
+ else {
+ for(j=0; j<bc; j++) {
+ /* Set buffer */
+ out8(IIC_MDBUF,ptr[tran+j]);
+ __asm__ volatile("eieio");
+ }
+ }
+ out8(IIC_CNTL, creg );
+ __asm__ volatile("eieio");
+
+ /* Transfer is in progress
+ we have to wait for upto 5 bytes of data
+ 1 byte chip address+r/w bit then bc bytes
+ of data.
+ udelay(10) is 1 bit time at 100khz
+ Doubled for slop. 20 is too small.
+ */
+ i=2*5*8;
+ do {
+ /* Get status */
+ status = in8(IIC_STS);
+ __asm__ volatile("eieio");
+ udelay (10);
+ i--;
+ } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR)
&& (i>0));
- if (status & IIC_STS_ERR) {
- result = IIC_NOK;
- status = in8 (IIC_EXTSTS);
- /* Lost arbitration? */
- if (status & IIC_EXTSTS_LA)
- result = IIC_NOK_LA;
- /* Incomplete transfer? */
- if (status & IIC_EXTSTS_ICT)
- result = IIC_NOK_ICT;
- /* Transfer aborted? */
- if (status & IIC_EXTSTS_XFRA)
- result = IIC_NOK_XFRA;
- } else if ( status & IIC_STS_PT) {
- result = IIC_NOK_TOUT;
- }
- /* Command is reading => get buffer */
- if ((reading) && (result == IIC_OK)) {
- /* Are there data in buffer */
- if (status & IIC_STS_MDBS) {
- /*
- even if we have data we have to wait 4OPB clocks
- for it to hit the front of the FIFO, after that
- we can just read. We should check XFCNT here and
- if the FIFO is full there is no need to wait.
+ if (status & IIC_STS_ERR) {
+ result = IIC_NOK;
+ status = in8 (IIC_EXTSTS);
+ /* Lost arbitration? */
+ if (status & IIC_EXTSTS_LA)
+ result = IIC_NOK_LA;
+ /* Incomplete transfer? */
+ if (status & IIC_EXTSTS_ICT)
+ result = IIC_NOK_ICT;
+ /* Transfer aborted? */
+ if (status & IIC_EXTSTS_XFRA)
+ result = IIC_NOK_XFRA;
+ } else if ( status & IIC_STS_PT) {
+ result = IIC_NOK_TOUT;
+ }
+ /* Command is reading => get buffer */
+ if ((reading) && (result == IIC_OK)) {
+ /* Are there data in buffer */
+ if (status & IIC_STS_MDBS) {
+ /*
+ even if we have data we have to wait 4OPB clocks
+ for it to hit the front of the FIFO, after that
+ we can just read. We should check XFCNT here and
+ if the FIFO is full there is no need to wait.
*/
- udelay (1);
- for(j=0;j<bc;j++) {
- ptr[tran+j] = in8(IIC_MDBUF);
- __asm__ volatile("eieio");
- }
- } else
- result = IIC_NOK_DATA;
- }
- creg = 0;
- tran+=bc;
- if( ptr == addr && tran == cnt ) {
- ptr = data;
- cnt = data_len;
- tran = 0;
- reading = cmd_type;
- if( reading )
- creg = IIC_CNTL_RPST;
- }
- }
- return (result);
+ udelay (1);
+ for(j=0;j<bc;j++) {
+ ptr[tran+j] = in8(IIC_MDBUF);
+ __asm__ volatile("eieio");
+ }
+ } else
+ result = IIC_NOK_DATA;
+ }
+ creg = 0;
+ tran+=bc;
+ if( ptr == addr && tran == cnt ) {
+ ptr = data;
+ cnt = data_len;
+ tran = 0;
+ reading = cmd_type;
+ if( reading )
+ creg = IIC_CNTL_RPST;
+ }
+ }
+ return (result);
}
int i2c_probe (uchar chip)
@@ -337,89 +337,88 @@
buf[0] = 0;
- /*
- * What is needed is to send the chip address and verify that the
- * address was <ACK>ed (i.e. there was a chip at that address which
- * drove the data line low).
- */
- return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
+ /*
+ * What is needed is to send the chip address and verify that the
+ * address was <ACK>ed (i.e. there was a chip at that address which
+ * drove the data line low).
+ */
+ return(i2c_transfer (1, chip << 1, 0,0, buf, 1) != 0);
}
-
int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
- uchar xaddr[4];
- int ret;
+ uchar xaddr[4];
+ int ret;
if ( alen > 4 ) {
printf ("I2C read: addr len %d not supported\n", alen);
return 1;
}
- if ( alen > 0 ) {
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
- }
+ if ( alen > 0 ) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
+ }
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
/*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- * address and the extra bits end up in the "chip address"
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
- * four 256 byte chips.
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
*
- * Note that we consider the length of the address field to
- * still be one byte because the extra address bits are
- * hidden in the chip address.
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
*/
- if( alen > 0 )
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ if( alen > 0 )
+ chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif
- if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
- printf( "I2c read: failed %d\n", ret);
- return 1;
- }
- return 0;
+ if( (ret = i2c_transfer( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
+ printf( "I2c read: failed %d\n", ret);
+ return 1;
+ }
+ return 0;
}
int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
- uchar xaddr[4];
+ uchar xaddr[4];
if ( alen > 4 ) {
printf ("I2C write: addr len %d not supported\n", alen);
return 1;
}
- if ( alen > 0 ) {
- xaddr[0] = (addr >> 24) & 0xFF;
- xaddr[1] = (addr >> 16) & 0xFF;
- xaddr[2] = (addr >> 8) & 0xFF;
- xaddr[3] = addr & 0xFF;
- }
+ if ( alen > 0 ) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
+ }
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
/*
- * EEPROM chips that implement "address overflow" are ones
- * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
- * address and the extra bits end up in the "chip address"
- * bit slots. This makes a 24WC08 (1Kbyte) chip look like
- * four 256 byte chips.
+ * EEPROM chips that implement "address overflow" are ones
+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
+ * address and the extra bits end up in the "chip address"
+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
+ * four 256 byte chips.
*
- * Note that we consider the length of the address field to
- * still be one byte because the extra address bits are
- * hidden in the chip address.
+ * Note that we consider the length of the address field to
+ * still be one byte because the extra address bits are
+ * hidden in the chip address.
*/
- if( alen > 0 )
- chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+ if( alen > 0 )
+ chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif
- return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
+ return (i2c_transfer( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
}
/*-----------------------------------------------------------------------
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 0867de4..b6a956c 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -27,7 +27,6 @@
#include <common.h>
#include <watchdog.h>
#include <command.h>
-#include <cmd_boot.h>
#include <asm/processor.h>
#include <ppc4xx.h>
#include <ppc_asm.tmpl>
diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S
index 78681cd..be28340 100644
--- a/cpu/ppc4xx/kgdb.S
+++ b/cpu/ppc4xx/kgdb.S
@@ -45,13 +45,13 @@
iccci r0,r0 /* iccci invalidates the entire I cache */
/* dcache */
addi r6,0,0x0000 /* clear GPR 6 */
- addi r7,r0, 128 /* do loop for # of dcache lines */
+ addi r7,r0, 128 /* do loop for # of dcache lines */
/* NOTE: dccci invalidates both */
- mtctr r7 /* ways in the D cache */
+ mtctr r7 /* ways in the D cache */
..dcloop:
- dccci 0,r6 /* invalidate line */
- addi r6,r6, 32 /* bump to next line */
- bdnz ..dcloop
+ dccci 0,r6 /* invalidate line */
+ addi r6,r6, 32 /* bump to next line */
+ bdnz ..dcloop
blr
.globl kgdb_flush_cache_range
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index c5a90a9..0606ebe 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -76,7 +76,6 @@
} /* end dump */
-
/***********************************************************/
/* read a phy reg and return the value with a rc */
/***********************************************************/
diff --git a/cpu/ppc4xx/resetvec.S b/cpu/ppc4xx/resetvec.S
index e058bf0..b3308bd 100644
--- a/cpu/ppc4xx/resetvec.S
+++ b/cpu/ppc4xx/resetvec.S
@@ -10,4 +10,3 @@
b _start
#endif
#endif
-
diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index e35a1d0..d4552a1 100644
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -128,7 +128,7 @@
* Now test for 64 MByte...
*/
- /*
+ /*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
@@ -179,7 +179,7 @@
* Now test for 32 MByte...
*/
- /*
+ /*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
@@ -221,7 +221,7 @@
/*
* Now test for 16 MByte...
*/
- /*
+ /*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
@@ -266,7 +266,7 @@
* Setup for 4 MByte...
*/
- /*
+ /*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c
index 76aee2e..289ad12 100644
--- a/cpu/ppc4xx/spd_sdram.c
+++ b/cpu/ppc4xx/spd_sdram.c
@@ -156,7 +156,7 @@
* way to minimize stack utilization.
*/
#ifndef CONFIG_405EP
- tmp = (mfdcr(pllmd) >> (31-6)) & 0xf; /* get FBDV bits */
+ tmp = (mfdcr(pllmd) >> (31-6)) & 0xf; /* get FBDV bits */
tmp = CONFIG_SYS_CLK_FREQ * tmp; /* get plb freq */
#else
{
@@ -197,10 +197,10 @@
#endif
bus_period = sdram_HZ_to_ns(tmp); /* get sdram speed */
- /* Make shure we are using SDRAM */
+ /* Make shure we are using SDRAM */
if (read_spd(2) != 0x04){
- SPD_ERR("SDRAM - non SDRAM memory module found\n");
- }
+ SPD_ERR("SDRAM - non SDRAM memory module found\n");
+ }
/*------------------------------------------------------------------
configure memory timing register
@@ -218,17 +218,17 @@
tmp = read_spd(127) & 0x6;
if(tmp == 0x02){ /* only cas = 2 supported */
- min_cas = 2;
+ min_cas = 2;
/* t_ck = read_spd(9); */
/* t_ac = read_spd(10); */
}
else if (tmp == 0x04){ /* only cas = 3 supported */
- min_cas = 3;
+ min_cas = 3;
/* t_ck = read_spd(9); */
/* t_ac = read_spd(10); */
}
else if (tmp == 0x06){ /* 2,3 supported, so use 2 */
- min_cas = 2;
+ min_cas = 2;
/* t_ck = read_spd(23); */
/* t_ac = read_spd(24); */
}
@@ -292,7 +292,7 @@
tmp=15625*8;
break;
default:
- SPD_ERR("SDRAM - Bad refresh period \n");
+ SPD_ERR("SDRAM - Bad refresh period \n");
}
/* convert from nsec to bus cycles */
tmp = tmp/bus_period;
@@ -332,11 +332,11 @@
if ( (read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) ){
sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
ecc_on = 1;
- }
+ }
else{
sdram0_ecccfg=0;
ecc_on = 0;
- }
+ }
/*------------------------------------------------------------------
calculate total size
@@ -369,7 +369,7 @@
mode=0; /* mode 1 */
break;
default:
- SPD_ERR("SDRAM - unsupported mode\n");
+ SPD_ERR("SDRAM - unsupported mode\n");
}
break;
case 12:
@@ -383,7 +383,7 @@
mode=1; /* mode 2 */
break;
default:
- SPD_ERR("SDRAM - unsupported mode\n");
+ SPD_ERR("SDRAM - unsupported mode\n");
}
break;
case 13:
@@ -403,7 +403,7 @@
mode=2; /* mode 3 */
break;
default:
- SPD_ERR("SDRAM - unsupported mode\n");
+ SPD_ERR("SDRAM - unsupported mode\n");
}
break;
default:
@@ -431,10 +431,10 @@
bank_code-=22; /* subtract 22 to get the code */
tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
- sdram0_b0cr = (bank_size) * 0 | tmp;
- if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
- if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
- if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
+ sdram0_b0cr = (bank_size) * 0 | tmp;
+ if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
+ if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
+ if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
/*
@@ -684,34 +684,34 @@
unsigned char spd_read(uchar chip, uint addr);
void get_spd_info(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void check_mem_type
- (unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ (unsigned long* dimm_populated,
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void check_volt_type
- (unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ (unsigned long* dimm_populated,
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void program_cfg0(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void program_cfg1(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void program_rtr (unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void program_tr0 (unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
void program_tr1 (void);
@@ -719,8 +719,8 @@
unsigned
long program_bxcr(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks);
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks);
/*
* This function is reading data from the DIMM module EEPROM over the SPD bus
@@ -788,7 +788,7 @@
* program the BxCR registers to find out total sdram installed
*/
total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
- num_dimm_banks);
+ num_dimm_banks);
/*
* program SDRAM Clock Timing Register (SDRAM0_CLKTR)
@@ -810,10 +810,10 @@
* wait for SDRAM_CFG0_DC_EN to complete
*/
while(1) {
- mfsdram(mem_mcsts, mcsts);
- if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
- break;
- }
+ mfsdram(mem_mcsts, mcsts);
+ if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
+ break;
+ }
}
/*
@@ -838,8 +838,8 @@
}
void get_spd_info(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long dimm_found;
@@ -848,90 +848,90 @@
dimm_found = FALSE;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- num_of_bytes = 0;
- total_size = 0;
+ num_of_bytes = 0;
+ total_size = 0;
- num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
- total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
+ num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
+ total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
- if ((num_of_bytes != 0) && (total_size != 0)) {
- dimm_populated[dimm_num] = TRUE;
- dimm_found = TRUE;
+ if ((num_of_bytes != 0) && (total_size != 0)) {
+ dimm_populated[dimm_num] = TRUE;
+ dimm_found = TRUE;
#if 0
- printf("DIMM slot %lu: populated\n", dimm_num);
+ printf("DIMM slot %lu: populated\n", dimm_num);
#endif
- }
- else {
- dimm_populated[dimm_num] = FALSE;
+ }
+ else {
+ dimm_populated[dimm_num] = FALSE;
#if 0
- printf("DIMM slot %lu: Not populated\n", dimm_num);
+ printf("DIMM slot %lu: Not populated\n", dimm_num);
#endif
- }
+ }
}
if (dimm_found == FALSE) {
- printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
- hang();
+ printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
+ hang();
}
}
void check_mem_type(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned char dimm_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
- switch (dimm_type) {
- case 7:
+ if (dimm_populated[dimm_num] == TRUE) {
+ dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
+ switch (dimm_type) {
+ case 7:
#if 0
- printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
+ printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
#endif
- break;
- default:
- printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
- dimm_num);
- printf("Only DDR SDRAM DIMMs are supported.\n");
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
- break;
- }
- }
+ break;
+ default:
+ printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
+ dimm_num);
+ printf("Only DDR SDRAM DIMMs are supported.\n");
+ printf("Replace the DIMM module with a supported DIMM.\n\n");
+ hang();
+ break;
+ }
+ }
}
}
void check_volt_type(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long voltage_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
- if (voltage_type != 0x04) {
- printf("ERROR: DIMM %lu with unsupported voltage level.\n",
- dimm_num);
- hang();
- }
- else {
+ if (dimm_populated[dimm_num] == TRUE) {
+ voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
+ if (voltage_type != 0x04) {
+ printf("ERROR: DIMM %lu with unsupported voltage level.\n",
+ dimm_num);
+ hang();
+ }
+ else {
#if 0
- printf("DIMM %lu voltage level supported.\n", dimm_num);
+ printf("DIMM %lu voltage level supported.\n", dimm_num);
#endif
- }
- break;
- }
+ }
+ break;
+ }
}
}
void program_cfg0(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long cfg0;
@@ -951,9 +951,9 @@
* clear bits
*/
cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
- SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
- SDRAM_CFG0_DMWD_MASK |
- SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
+ SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
+ SDRAM_CFG0_DMWD_MASK |
+ SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
/*
@@ -961,52 +961,52 @@
*/
ecc_enabled = TRUE;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
- if (ecc != 0x02) {
- ecc_enabled = FALSE;
- }
+ if (dimm_populated[dimm_num] == TRUE) {
+ ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
+ if (ecc != 0x02) {
+ ecc_enabled = FALSE;
+ }
- /*
- * program Registered DIMM Enable
- */
- attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
- if ((attributes & 0x02) != 0x00) {
- cfg0 |= SDRAM_CFG0_RDEN;
- }
+ /*
+ * program Registered DIMM Enable
+ */
+ attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
+ if ((attributes & 0x02) != 0x00) {
+ cfg0 |= SDRAM_CFG0_RDEN;
+ }
- /*
- * program DDR SDRAM Data Width
- */
- data_width =
- (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
- (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
- if (data_width == 64 || data_width == 72) {
- dimm_64bit = TRUE;
- cfg0 |= SDRAM_CFG0_DMWD_64;
- }
- else if (data_width == 32 || data_width == 40) {
- dimm_32bit = TRUE;
- cfg0 |= SDRAM_CFG0_DMWD_32;
- }
- else {
- printf("WARNING: DIMM with datawidth of %lu bits.\n",
- data_width);
- printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
- hang();
- }
- break;
- }
+ /*
+ * program DDR SDRAM Data Width
+ */
+ data_width =
+ (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
+ (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
+ if (data_width == 64 || data_width == 72) {
+ dimm_64bit = TRUE;
+ cfg0 |= SDRAM_CFG0_DMWD_64;
+ }
+ else if (data_width == 32 || data_width == 40) {
+ dimm_32bit = TRUE;
+ cfg0 |= SDRAM_CFG0_DMWD_32;
+ }
+ else {
+ printf("WARNING: DIMM with datawidth of %lu bits.\n",
+ data_width);
+ printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
+ hang();
+ }
+ break;
+ }
}
/*
* program Memory Data Error Checking
*/
if (ecc_enabled == TRUE) {
- cfg0 |= SDRAM_CFG0_MCHK_GEN;
+ cfg0 |= SDRAM_CFG0_MCHK_GEN;
}
else {
- cfg0 |= SDRAM_CFG0_MCHK_NON;
+ cfg0 |= SDRAM_CFG0_MCHK_NON;
}
/*
@@ -1023,8 +1023,8 @@
}
void program_cfg1(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks)
{
unsigned long cfg1;
mfsdram(mem_cfg1, cfg1);
@@ -1041,8 +1041,8 @@
}
void program_rtr (unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long bus_period_x_10;
@@ -1060,36 +1060,36 @@
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
- switch (refresh_rate_type) {
- case 0x00:
- refresh_rate = 15625;
- break;
- case 0x011:
- refresh_rate = 15625/4;
- break;
- case 0x02:
- refresh_rate = 15625/2;
- break;
- case 0x03:
- refresh_rate = 15626*2;
- break;
- case 0x04:
- refresh_rate = 15625*4;
- break;
- case 0x05:
- refresh_rate = 15625*8;
- break;
- default:
- printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
- dimm_num);
- printf("Replace the DIMM module with a supported DIMM.\n");
- break;
- }
+ if (dimm_populated[dimm_num] == TRUE) {
+ refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
+ switch (refresh_rate_type) {
+ case 0x00:
+ refresh_rate = 15625;
+ break;
+ case 0x011:
+ refresh_rate = 15625/4;
+ break;
+ case 0x02:
+ refresh_rate = 15625/2;
+ break;
+ case 0x03:
+ refresh_rate = 15626*2;
+ break;
+ case 0x04:
+ refresh_rate = 15625*4;
+ break;
+ case 0x05:
+ refresh_rate = 15625*8;
+ break;
+ default:
+ printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
+ dimm_num);
+ printf("Replace the DIMM module with a supported DIMM.\n");
+ break;
+ }
- break;
- }
+ break;
+ }
}
refresh_interval = refresh_rate * 10 / bus_period_x_10;
@@ -1102,8 +1102,8 @@
}
void program_tr0 (unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long tr0;
@@ -1141,9 +1141,9 @@
*/
mfsdram(mem_tr0, tr0);
tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
- SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
- SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
- SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
+ SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
+ SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
+ SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
/*
* initialization
@@ -1160,83 +1160,83 @@
tcyc_3_0_ns_x_10 = 0;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
- t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
- t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
- t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
- cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
+ if (dimm_populated[dimm_num] == TRUE) {
+ wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
+ t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
+ t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
+ t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
+ cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
- for (cas_index = 0; cas_index < 3; cas_index++) {
- switch (cas_index) {
- case 0:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
- break;
- case 1:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
- break;
- default:
- tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
- break;
- }
+ for (cas_index = 0; cas_index < 3; cas_index++) {
+ switch (cas_index) {
+ case 0:
+ tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
+ break;
+ case 1:
+ tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
+ break;
+ default:
+ tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
+ break;
+ }
- if ((tcyc_reg & 0x0F) >= 10) {
- printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
- dimm_num);
- hang();
- }
+ if ((tcyc_reg & 0x0F) >= 10) {
+ printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
+ dimm_num);
+ hang();
+ }
- cycle_time_ns_x_10[cas_index] =
- (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
- }
+ cycle_time_ns_x_10[cas_index] =
+ (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
+ }
- cas_index = 0;
+ cas_index = 0;
- if ((cas_bit & 0x80) != 0) {
- cas_index += 3;
- }
- else if ((cas_bit & 0x40) != 0) {
- cas_index += 2;
- }
- else if ((cas_bit & 0x20) != 0) {
- cas_index += 1;
- }
+ if ((cas_bit & 0x80) != 0) {
+ cas_index += 3;
+ }
+ else if ((cas_bit & 0x40) != 0) {
+ cas_index += 2;
+ }
+ else if ((cas_bit & 0x20) != 0) {
+ cas_index += 1;
+ }
- if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
- tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- }
- else {
- if (cas_index != 0) {
- cas_index++;
- }
- cas_3_0_available = FALSE;
- }
+ if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
+ tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
+ cas_index++;
+ }
+ else {
+ if (cas_index != 0) {
+ cas_index++;
+ }
+ cas_3_0_available = FALSE;
+ }
- if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
- tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- }
- else {
- if (cas_index != 0) {
- cas_index++;
- }
- cas_2_5_available = FALSE;
- }
+ if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
+ tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
+ cas_index++;
+ }
+ else {
+ if (cas_index != 0) {
+ cas_index++;
+ }
+ cas_2_5_available = FALSE;
+ }
- if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
- tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
- cas_index++;
- }
- else {
- if (cas_index != 0) {
- cas_index++;
- }
- cas_2_0_available = FALSE;
- }
+ if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
+ tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
+ cas_index++;
+ }
+ else {
+ if (cas_index != 0) {
+ cas_index++;
+ }
+ cas_2_0_available = FALSE;
+ }
- break;
- }
+ break;
+ }
}
/*
@@ -1245,33 +1245,33 @@
tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
switch (wcsbc) {
case 0:
- tr0 |= SDRAM_TR0_SDWD_0_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDWD_0_CLK;
+ break;
default:
- tr0 |= SDRAM_TR0_SDWD_1_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDWD_1_CLK;
+ break;
}
/*
* Program SD_CASL field
*/
if ((cas_2_0_available == TRUE) &&
- (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
+ (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
+ tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
}
else if((cas_2_5_available == TRUE) &&
- (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
+ (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
+ tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
}
else if((cas_3_0_available == TRUE) &&
- (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
- tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
+ (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
+ tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
}
else {
- printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
- printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
- printf("Make sure the PLB speed is within the supported range.\n");
- hang();
+ printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
+ printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
+ printf("Make sure the PLB speed is within the supported range.\n");
+ hang();
}
/*
@@ -1281,20 +1281,20 @@
t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
if (sys_info.freqPLB != plb_check) {
- t_rp_clk++;
+ t_rp_clk++;
}
switch ((unsigned long)t_rp_clk) {
case 0:
case 1:
case 2:
- tr0 |= SDRAM_TR0_SDPA_2_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDPA_2_CLK;
+ break;
case 3:
- tr0 |= SDRAM_TR0_SDPA_3_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDPA_3_CLK;
+ break;
default:
- tr0 |= SDRAM_TR0_SDPA_4_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDPA_4_CLK;
+ break;
}
/*
@@ -1303,7 +1303,7 @@
t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
if (sys_info.freqPLB != plb_check) {
- t_ras_rcd_clk++;
+ t_ras_rcd_clk++;
}
switch (t_ras_rcd_clk) {
case 0:
@@ -1334,7 +1334,7 @@
t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
residue = sys_info.freqPLB % (ONE_BILLION / 75);
if (residue >= (ONE_BILLION / 150)) {
- t_rfc_clk++;
+ t_rfc_clk++;
}
switch (t_rfc_clk) {
case 0:
@@ -1344,29 +1344,29 @@
case 4:
case 5:
case 6:
- tr0 |= SDRAM_TR0_SDRA_6_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRA_6_CLK;
+ break;
case 7:
- tr0 |= SDRAM_TR0_SDRA_7_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRA_7_CLK;
+ break;
case 8:
- tr0 |= SDRAM_TR0_SDRA_8_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRA_8_CLK;
+ break;
case 9:
- tr0 |= SDRAM_TR0_SDRA_9_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRA_9_CLK;
+ break;
case 10:
- tr0 |= SDRAM_TR0_SDRA_10_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRA_10_CLK;
+ break;
case 11:
- tr0 |= SDRAM_TR0_SDRA_11_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRA_11_CLK;
+ break;
case 12:
- tr0 |= SDRAM_TR0_SDRA_12_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRA_12_CLK;
+ break;
default:
- tr0 |= SDRAM_TR0_SDRA_13_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRA_13_CLK;
+ break;
}
/*
@@ -1375,20 +1375,20 @@
t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
if (sys_info.freqPLB != plb_check) {
- t_rcd_clk++;
+ t_rcd_clk++;
}
switch (t_rcd_clk) {
case 0:
case 1:
case 2:
- tr0 |= SDRAM_TR0_SDRD_2_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRD_2_CLK;
+ break;
case 3:
- tr0 |= SDRAM_TR0_SDRD_3_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRD_3_CLK;
+ break;
default:
- tr0 |= SDRAM_TR0_SDRD_4_CLK;
- break;
+ tr0 |= SDRAM_TR0_SDRD_4_CLK;
+ break;
}
#if 0
@@ -1432,19 +1432,19 @@
*/
mfsdram(mem_tr1, tr1);
tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
- SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
+ SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
mfsdram(mem_tr0, tr0);
if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
(sys_info.freqPLB > 100000000)) {
- tr1 |= SDRAM_TR1_RDSS_TR2;
- tr1 |= SDRAM_TR1_RDSL_STAGE3;
- tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
+ tr1 |= SDRAM_TR1_RDSS_TR2;
+ tr1 |= SDRAM_TR1_RDSL_STAGE3;
+ tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
}
else {
- tr1 |= SDRAM_TR1_RDSS_TR1;
- tr1 |= SDRAM_TR1_RDSL_STAGE2;
- tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
+ tr1 |= SDRAM_TR1_RDSS_TR1;
+ tr1 |= SDRAM_TR1_RDSL_STAGE2;
+ tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
}
/*
@@ -1474,91 +1474,91 @@
printf("Starting memory test ");
#endif
for (k = 0; k < NUMHALFCYCLES; k++) {
- for (rdclt = 0; rdclt < dly_val; rdclt++) {
- /*
- * Set the timing reg for the test.
- */
- mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
+ for (rdclt = 0; rdclt < dly_val; rdclt++) {
+ /*
+ * Set the timing reg for the test.
+ */
+ mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
- for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
- if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
- /* Bank is enabled */
- membase = (unsigned long*)
- (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
+ for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
+ mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
+ if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
+ /* Bank is enabled */
+ membase = (unsigned long*)
+ (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
- /*
- * Run the short memory test
- */
- for (i = 0; i < NUMMEMTESTS; i++) {
- for (j = 0; j < NUMMEMWORDS; j++) {
- membase[j] = test[i][j];
- ppcDcbf((unsigned long)&(membase[j]));
- }
+ /*
+ * Run the short memory test
+ */
+ for (i = 0; i < NUMMEMTESTS; i++) {
+ for (j = 0; j < NUMMEMWORDS; j++) {
+ membase[j] = test[i][j];
+ ppcDcbf((unsigned long)&(membase[j]));
+ }
- for (j = 0; j < NUMMEMWORDS; j++) {
- if (membase[j] != test[i][j]) {
- ppcDcbf((unsigned long)&(membase[j]));
- break;
- }
- ppcDcbf((unsigned long)&(membase[j]));
- }
+ for (j = 0; j < NUMMEMWORDS; j++) {
+ if (membase[j] != test[i][j]) {
+ ppcDcbf((unsigned long)&(membase[j]));
+ break;
+ }
+ ppcDcbf((unsigned long)&(membase[j]));
+ }
- if (j < NUMMEMWORDS) {
- break;
- }
- }
+ if (j < NUMMEMWORDS) {
+ break;
+ }
+ }
- /*
- * see if the rdclt value passed
- */
- if (i < NUMMEMTESTS) {
- break;
- }
- }
- }
+ /*
+ * see if the rdclt value passed
+ */
+ if (i < NUMMEMTESTS) {
+ break;
+ }
+ }
+ }
- if (bxcr_num == MAXBXCR) {
- if (fail_found == TRUE) {
- pass_found = TRUE;
- if (current_pass_length == 0) {
- current_start = rdclt_offset + rdclt;
- }
+ if (bxcr_num == MAXBXCR) {
+ if (fail_found == TRUE) {
+ pass_found = TRUE;
+ if (current_pass_length == 0) {
+ current_start = rdclt_offset + rdclt;
+ }
- current_fail_length = 0;
- current_pass_length++;
+ current_fail_length = 0;
+ current_pass_length++;
- if (current_pass_length > max_pass_length) {
- max_pass_length = current_pass_length;
- max_start = current_start;
- max_end = rdclt_offset + rdclt;
- }
- }
- }
- else {
- current_pass_length = 0;
- current_fail_length++;
+ if (current_pass_length > max_pass_length) {
+ max_pass_length = current_pass_length;
+ max_start = current_start;
+ max_end = rdclt_offset + rdclt;
+ }
+ }
+ }
+ else {
+ current_pass_length = 0;
+ current_fail_length++;
- if (current_fail_length >= (dly_val>>2)) {
- if (fail_found == FALSE) {
- fail_found = TRUE;
- }
- else if (pass_found == TRUE) {
- window_found = TRUE;
- break;
- }
- }
- }
- }
+ if (current_fail_length >= (dly_val>>2)) {
+ if (fail_found == FALSE) {
+ fail_found = TRUE;
+ }
+ else if (pass_found == TRUE) {
+ window_found = TRUE;
+ break;
+ }
+ }
+ }
+ }
#ifdef DEBUG
- printf(".");
+ printf(".");
#endif
- if (window_found == TRUE) {
- break;
- }
+ if (window_found == TRUE) {
+ break;
+ }
- tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
- rdclt_offset += dly_val;
+ tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
+ rdclt_offset += dly_val;
}
#ifdef DEBUG
printf("\n");
@@ -1582,10 +1582,10 @@
*/
tr1 &= ~SDRAM_TR1_RDCD_MASK;
if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
- tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
+ tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
}
else {
- tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
+ tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
}
/*
@@ -1593,21 +1593,21 @@
*/
tr1 &= ~SDRAM_TR1_RDCT_MASK;
while (max_end >= (dly_val<<1)) {
- max_end -= (dly_val<<1);
- max_start -= (dly_val<<1);
+ max_end -= (dly_val<<1);
+ max_start -= (dly_val<<1);
}
rdclt_average = ((max_start + max_end) >> 1);
if (rdclt_average >= 0x60)
- while(1);
+ while(1);
if (rdclt_average < 0) {
- rdclt_average = 0;
+ rdclt_average = 0;
}
if (rdclt_average >= dly_val) {
- rdclt_average -= dly_val;
- tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
+ rdclt_average -= dly_val;
+ tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
}
tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
@@ -1621,8 +1621,8 @@
}
unsigned long program_bxcr(unsigned long* dimm_populated,
- unsigned char* iic0_dimm_addr,
- unsigned long num_dimm_banks)
+ unsigned char* iic0_dimm_addr,
+ unsigned long num_dimm_banks)
{
unsigned long dimm_num;
unsigned long bxcr_num;
@@ -1641,8 +1641,8 @@
* Set the BxCR regs. First, wipe out the bank config registers.
*/
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
- mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
- mtdcr(memcfgd, 0x00000000);
+ mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
+ mtdcr(memcfgd, 0x00000000);
}
/*
@@ -1651,106 +1651,106 @@
bank_base_addr = CFG_SDRAM_BASE;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
- if (dimm_populated[dimm_num] == TRUE) {
- num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
- num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
- num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
- bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
+ if (dimm_populated[dimm_num] == TRUE) {
+ num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
+ num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
+ num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
+ bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
- /*
- * Set the SDRAM0_BxCR regs
- */
- cr = 0;
- bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
- switch (bank_size_id) {
- case 0x02:
- cr |= SDRAM_BXCR_SDSZ_8;
- break;
- case 0x04:
- cr |= SDRAM_BXCR_SDSZ_16;
- break;
- case 0x08:
- cr |= SDRAM_BXCR_SDSZ_32;
- break;
- case 0x10:
- cr |= SDRAM_BXCR_SDSZ_64;
- break;
- case 0x20:
- cr |= SDRAM_BXCR_SDSZ_128;
- break;
- case 0x40:
- cr |= SDRAM_BXCR_SDSZ_256;
- break;
- case 0x80:
- cr |= SDRAM_BXCR_SDSZ_512;
- break;
- default:
- printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
- dimm_num);
- printf("ERROR: Unsupported value for the banksize: %d.\n",
- bank_size_id);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
- }
+ /*
+ * Set the SDRAM0_BxCR regs
+ */
+ cr = 0;
+ bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
+ switch (bank_size_id) {
+ case 0x02:
+ cr |= SDRAM_BXCR_SDSZ_8;
+ break;
+ case 0x04:
+ cr |= SDRAM_BXCR_SDSZ_16;
+ break;
+ case 0x08:
+ cr |= SDRAM_BXCR_SDSZ_32;
+ break;
+ case 0x10:
+ cr |= SDRAM_BXCR_SDSZ_64;
+ break;
+ case 0x20:
+ cr |= SDRAM_BXCR_SDSZ_128;
+ break;
+ case 0x40:
+ cr |= SDRAM_BXCR_SDSZ_256;
+ break;
+ case 0x80:
+ cr |= SDRAM_BXCR_SDSZ_512;
+ break;
+ default:
+ printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
+ dimm_num);
+ printf("ERROR: Unsupported value for the banksize: %d.\n",
+ bank_size_id);
+ printf("Replace the DIMM module with a supported DIMM.\n\n");
+ hang();
+ }
- switch (num_col_addr) {
- case 0x08:
- cr |= SDRAM_BXCR_SDAM_1;
- break;
- case 0x09:
- cr |= SDRAM_BXCR_SDAM_2;
- break;
- case 0x0A:
- cr |= SDRAM_BXCR_SDAM_3;
- break;
- case 0x0B:
- cr |= SDRAM_BXCR_SDAM_4;
- break;
- default:
- printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
- dimm_num);
- printf("ERROR: Unsupported value for number of "
- "column addresses: %d.\n", num_col_addr);
- printf("Replace the DIMM module with a supported DIMM.\n\n");
- hang();
- }
+ switch (num_col_addr) {
+ case 0x08:
+ cr |= SDRAM_BXCR_SDAM_1;
+ break;
+ case 0x09:
+ cr |= SDRAM_BXCR_SDAM_2;
+ break;
+ case 0x0A:
+ cr |= SDRAM_BXCR_SDAM_3;
+ break;
+ case 0x0B:
+ cr |= SDRAM_BXCR_SDAM_4;
+ break;
+ default:
+ printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
+ dimm_num);
+ printf("ERROR: Unsupported value for number of "
+ "column addresses: %d.\n", num_col_addr);
+ printf("Replace the DIMM module with a supported DIMM.\n\n");
+ hang();
+ }
- /*
- * enable the bank
- */
- cr |= SDRAM_BXCR_SDBE;
+ /*
+ * enable the bank
+ */
+ cr |= SDRAM_BXCR_SDBE;
- /*------------------------------------------------------------------
- | This next section is hardware dependent and must be programmed
- | to match the hardware.
- +-----------------------------------------------------------------*/
- if (dimm_num == 0) {
- for (i = 0; i < num_banks; i++) {
- mtdcr(memcfga, mem_b0cr + (i << 2));
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
- SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK |
- SDRAM_BXCR_SDBE);
- cr |= temp;
- cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
- mtdcr(memcfgd, cr);
- bank_base_addr += bank_size_bytes;
- }
- }
- else {
- for (i = 0; i < num_banks; i++) {
- mtdcr(memcfga, mem_b2cr + (i << 2));
- temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
- SDRAM_BXCR_SDSZ_MASK |
- SDRAM_BXCR_SDAM_MASK |
- SDRAM_BXCR_SDBE);
- cr |= temp;
- cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
- mtdcr(memcfgd, cr);
- bank_base_addr += bank_size_bytes;
- }
- }
- }
+ /*------------------------------------------------------------------
+ | This next section is hardware dependent and must be programmed
+ | to match the hardware.
+ +-----------------------------------------------------------------*/
+ if (dimm_num == 0) {
+ for (i = 0; i < num_banks; i++) {
+ mtdcr(memcfga, mem_b0cr + (i << 2));
+ temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
+ SDRAM_BXCR_SDSZ_MASK |
+ SDRAM_BXCR_SDAM_MASK |
+ SDRAM_BXCR_SDBE);
+ cr |= temp;
+ cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
+ mtdcr(memcfgd, cr);
+ bank_base_addr += bank_size_bytes;
+ }
+ }
+ else {
+ for (i = 0; i < num_banks; i++) {
+ mtdcr(memcfga, mem_b2cr + (i << 2));
+ temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
+ SDRAM_BXCR_SDSZ_MASK |
+ SDRAM_BXCR_SDAM_MASK |
+ SDRAM_BXCR_SDBE);
+ cr |= temp;
+ cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
+ mtdcr(memcfgd, cr);
+ bank_base_addr += bank_size_bytes;
+ }
+ }
+ }
}
return(bank_base_addr);
@@ -1775,26 +1775,26 @@
bank_base_addr = CFG_SDRAM_BASE;
if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
- SDRAM_CFG0_MCHK_GEN);
+ mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
+ SDRAM_CFG0_MCHK_GEN);
- if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
- address_increment = 4;
- }
- else {
- address_increment = 8;
- }
+ if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
+ address_increment = 4;
+ }
+ else {
+ address_increment = 8;
+ }
- current_address = (unsigned long)(bank_base_addr);
- end_address = (unsigned long)(bank_base_addr) + num_bytes;
+ current_address = (unsigned long)(bank_base_addr);
+ end_address = (unsigned long)(bank_base_addr) + num_bytes;
- while (current_address < end_address) {
- *((unsigned long*)current_address) = 0x00000000;
- current_address += address_increment;
- }
+ while (current_address < end_address) {
+ *((unsigned long*)current_address) = 0x00000000;
+ current_address += address_increment;
+ }
- mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
- SDRAM_CFG0_MCHK_CHK);
+ mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
+ SDRAM_CFG0_MCHK_CHK);
}
}
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c
index fdefbb6..7263227 100644
--- a/cpu/ppc4xx/speed.c
+++ b/cpu/ppc4xx/speed.c
@@ -232,7 +232,7 @@
sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
- sysInfo->freqPLB >>= 1;
+ sysInfo->freqPLB >>= 1;
sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index c6a9eda..aa857d0 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -556,9 +556,9 @@
/*----------------------------------------------------------------------- */
/* DMA Status, clear to come up clean */
/*----------------------------------------------------------------------- */
- addis r3,r0, 0xFFFF /* Clear all existing DMA status */
- ori r3,r3, 0xFFFF
- mtdcr dmasr, r3
+ addis r3,r0, 0xFFFF /* Clear all existing DMA status */
+ ori r3,r3, 0xFFFF
+ mtdcr dmasr, r3
bl ppc405ep_init /* do ppc405ep specific init */
#endif /* CONFIG_405EP */
@@ -568,21 +568,21 @@
* Setup OCM - On Chip Memory
*******************************************************************/
/* Setup OCM */
- lis r0, 0x7FFF
- ori r0, r0, 0xFFFF
- mfdcr r3, ocmiscntl /* get instr-side IRAM config */
- mfdcr r4, ocmdscntl /* get data-side IRAM config */
- and r3, r3, r0 /* disable data-side IRAM */
- and r4, r4, r0 /* disable data-side IRAM */
- mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
- mtdcr ocmdscntl, r4 /* set data-side IRAM config */
- isync
+ lis r0, 0x7FFF
+ ori r0, r0, 0xFFFF
+ mfdcr r3, ocmiscntl /* get instr-side IRAM config */
+ mfdcr r4, ocmdscntl /* get data-side IRAM config */
+ and r3, r3, r0 /* disable data-side IRAM */
+ and r4, r4, r0 /* disable data-side IRAM */
+ mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
+ mtdcr ocmdscntl, r4 /* set data-side IRAM config */
+ isync
addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
mtdcr ocmdsarc, r3
addis r4, 0, 0xC000 /* OCM data area enabled */
mtdcr ocmdscntl, r4
- isync
+ isync
#endif
/*----------------------------------------------------------------------- */
@@ -697,7 +697,7 @@
GET_GOT /* initialize GOT access */
- bl cpu_init_f /* run low-level CPU init code (from Flash) */
+ bl cpu_init_f /* run low-level CPU init code (from Flash) */
/* NEVER RETURNS! */
bl board_init_f /* run first part of init code (from Flash) */
@@ -1451,100 +1451,100 @@
/**************************************************************************/
#ifdef CONFIG_405EP
ppc405ep_init:
- /*
- !-----------------------------------------------------------------------
- ! Check FPGA for PCI internal/external arbitration
- ! If board is set to internal arbitration, update cpc0_pci
- !-----------------------------------------------------------------------
+ /*
+ !-----------------------------------------------------------------------
+ ! Check FPGA for PCI internal/external arbitration
+ ! If board is set to internal arbitration, update cpc0_pci
+ !-----------------------------------------------------------------------
*/
- addi r3,0,CPC0_PCI_HOST_CFG_EN
+ addi r3,0,CPC0_PCI_HOST_CFG_EN
#ifdef CONFIG_BUBINGA405EP
- addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
- ori r5,r5,FPGA_REG1@l
- lbz r5,0x0(r5) /* read to get PCI arb selection */
- andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
- beq ..pci_cfg_set /* if not set, then bypass reg write*/
+ addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */
+ ori r5,r5,FPGA_REG1@l
+ lbz r5,0x0(r5) /* read to get PCI arb selection */
+ andi. r6,r5,FPGA_REG1_PCI_INT_ARB /* using internal arbiter ?*/
+ beq ..pci_cfg_set /* if not set, then bypass reg write*/
#endif
- ori r3,r3,CPC0_PCI_ARBIT_EN
+ ori r3,r3,CPC0_PCI_ARBIT_EN
..pci_cfg_set:
- mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
+ mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
- /*
- !-----------------------------------------------------------------------
- ! Check to see if chip is in bypass mode.
- ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
- ! CPU reset Otherwise, skip this step and keep going.
- ! Note: Running BIOS in bypass mode is not supported since PLB speed
- ! will not be fast enough for the SDRAM (min 66MHz)
- !-----------------------------------------------------------------------
+ /*
+ !-----------------------------------------------------------------------
+ ! Check to see if chip is in bypass mode.
+ ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
+ ! CPU reset Otherwise, skip this step and keep going.
+ ! Note: Running BIOS in bypass mode is not supported since PLB speed
+ ! will not be fast enough for the SDRAM (min 66MHz)
+ !-----------------------------------------------------------------------
*/
- mfdcr r5, CPC0_PLLMR1
- rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
- cmpi cr0,0,r4,0x1
+ mfdcr r5, CPC0_PLLMR1
+ rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
+ cmpi cr0,0,r4,0x1
- beq pll_done /* if SSCS =b'1' then PLL has */
- /* already been set */
- /* and CPU has been reset */
- /* so skip to next section */
+ beq pll_done /* if SSCS =b'1' then PLL has */
+ /* already been set */
+ /* and CPU has been reset */
+ /* so skip to next section */
#ifdef CONFIG_BUBINGA405EP
/*
- !-----------------------------------------------------------------------
- ! Read NVRAM to get value to write in PLLMR.
- ! If value has not been correctly saved, write default value
- ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
- ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
- !
- ! WARNING: This code assumes the first three words in the nvram_t
- ! structure in openbios.h. Changing the beginning of
- ! the structure will break this code.
- !
- !-----------------------------------------------------------------------
+ !-----------------------------------------------------------------------
+ ! Read NVRAM to get value to write in PLLMR.
+ ! If value has not been correctly saved, write default value
+ ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
+ ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
+ !
+ ! WARNING: This code assumes the first three words in the nvram_t
+ ! structure in openbios.h. Changing the beginning of
+ ! the structure will break this code.
+ !
+ !-----------------------------------------------------------------------
*/
- addis r3,0,NVRAM_BASE@h
- addi r3,r3,NVRAM_BASE@l
+ addis r3,0,NVRAM_BASE@h
+ addi r3,r3,NVRAM_BASE@l
- lwz r4, 0(r3)
- addis r5,0,NVRVFY1@h
- addi r5,r5,NVRVFY1@l
- cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
- bne ..no_pllset
- addi r3,r3,4
- lwz r4, 0(r3)
- addis r5,0,NVRVFY2@h
- addi r5,r5,NVRVFY2@l
- cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
- bne ..no_pllset
- addi r3,r3,8 /* Skip over conf_size */
- lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
- lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
- rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
- cmpi cr0,0,r5,1 /* See if PLL is locked */
- beq pll_write
+ lwz r4, 0(r3)
+ addis r5,0,NVRVFY1@h
+ addi r5,r5,NVRVFY1@l
+ cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
+ bne ..no_pllset
+ addi r3,r3,4
+ lwz r4, 0(r3)
+ addis r5,0,NVRVFY2@h
+ addi r5,r5,NVRVFY2@l
+ cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
+ bne ..no_pllset
+ addi r3,r3,8 /* Skip over conf_size */
+ lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
+ lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
+ rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
+ cmpi cr0,0,r5,1 /* See if PLL is locked */
+ beq pll_write
..no_pllset:
#endif /* CONFIG_BUBINGA405EP */
- addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
- ori r3,r3,PLLMR0_DEFAULT@l /* */
- addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
- ori r4,r4,PLLMR1_DEFAULT@l /* */
+ addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
+ ori r3,r3,PLLMR0_DEFAULT@l /* */
+ addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
+ ori r4,r4,PLLMR1_DEFAULT@l /* */
- b pll_write /* Write the CPC0_PLLMR with new value */
+ b pll_write /* Write the CPC0_PLLMR with new value */
pll_done:
- /*
- !-----------------------------------------------------------------------
- ! Clear Soft Reset Register
- ! This is needed to enable PCI if not booting from serial EPROM
- !-----------------------------------------------------------------------
+ /*
+ !-----------------------------------------------------------------------
+ ! Clear Soft Reset Register
+ ! This is needed to enable PCI if not booting from serial EPROM
+ !-----------------------------------------------------------------------
*/
- addi r3, 0, 0x0
- mtdcr CPC0_SRR, r3
+ addi r3, 0, 0x0
+ mtdcr CPC0_SRR, r3
- addis r3,0,0x0010
- mtctr r3
+ addis r3,0,0x0010
+ mtctr r3
pci_wait:
- bdnz pci_wait
+ bdnz pci_wait
blr /* return to main code */
@@ -1565,43 +1565,43 @@
!-----------------------------------------------------------------------------
*/
pll_write:
- mfdcr r5, CPC0_UCR
- andis. r5,r5,0xFFFF
- ori r5,r5,0x0101 /* Stop the UART clocks */
- mtdcr CPC0_UCR,r5 /* Before changing PLL */
+ mfdcr r5, CPC0_UCR
+ andis. r5,r5,0xFFFF
+ ori r5,r5,0x0101 /* Stop the UART clocks */
+ mtdcr CPC0_UCR,r5 /* Before changing PLL */
- mfdcr r5, CPC0_PLLMR1
- rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
- mtdcr CPC0_PLLMR1,r5
- oris r5,r5,0x4000 /* Set PLL Reset */
- mtdcr CPC0_PLLMR1,r5
+ mfdcr r5, CPC0_PLLMR1
+ rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
+ mtdcr CPC0_PLLMR1,r5
+ oris r5,r5,0x4000 /* Set PLL Reset */
+ mtdcr CPC0_PLLMR1,r5
- mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
- rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
- oris r5,r5,0x4000 /* Set PLL Reset */
- mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
- rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
- mtdcr CPC0_PLLMR1,r5
+ mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
+ rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
+ oris r5,r5,0x4000 /* Set PLL Reset */
+ mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
+ rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
+ mtdcr CPC0_PLLMR1,r5
/*
- ! Wait min of 100us for PLL to lock.
- ! See CMOS 27E databook for more info.
- ! At 200MHz, that means waiting 20,000 instructions
+ ! Wait min of 100us for PLL to lock.
+ ! See CMOS 27E databook for more info.
+ ! At 200MHz, that means waiting 20,000 instructions
*/
- addi r3,0,20000 /* 2000 = 0x4e20 */
- mtctr r3
+ addi r3,0,20000 /* 2000 = 0x4e20 */
+ mtctr r3
pll_wait:
- bdnz pll_wait
+ bdnz pll_wait
- oris r5,r5,0x8000 /* Enable PLL */
- mtdcr CPC0_PLLMR1,r5 /* Engage */
+ oris r5,r5,0x8000 /* Enable PLL */
+ mtdcr CPC0_PLLMR1,r5 /* Engage */
- /*
- * Reset CPU to guarantee timings are OK
- * Not sure if this is needed...
- */
- addis r3,0,0x1000
- mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
- /* execution will continue from the poweron */
- /* vector of 0xfffffffc */
+ /*
+ * Reset CPU to guarantee timings are OK
+ * Not sure if this is needed...
+ */
+ addis r3,0,0x1000
+ mtspr dbcr0,r3 /* This will cause a CPU core reset, and */
+ /* execution will continue from the poweron */
+ /* vector of 0xfffffffc */
#endif /* CONFIG_405EP */
diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c
index 85f2ea4..1cf899e 100644
--- a/cpu/ppc4xx/traps.c
+++ b/cpu/ppc4xx/traps.c
@@ -203,7 +203,7 @@
void
ProgramCheckException(struct pt_regs *regs)
{
- long esr_val;
+ long esr_val;
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -212,12 +212,12 @@
show_regs(regs);
- esr_val = get_esr();
- if( esr_val & ESR_PIL )
+ esr_val = get_esr();
+ if( esr_val & ESR_PIL )
printf( "** Illegal Instruction **\n" );
- else if( esr_val & ESR_PPR )
+ else if( esr_val & ESR_PPR )
printf( "** Privileged Instruction **\n" );
- else if( esr_val & ESR_PTR )
+ else if( esr_val & ESR_PTR )
printf( "** Trap Instruction **\n" );
print_backtrace((unsigned long *)regs->gpr[1]);
@@ -227,15 +227,15 @@
void
PITException(struct pt_regs *regs)
{
- /*
- * Reset PIT interrupt
- */
- set_tsr(0x08000000);
+ /*
+ * Reset PIT interrupt
+ */
+ set_tsr(0x08000000);
- /*
- * Call timer_interrupt routine in interrupts.c
- */
- timer_interrupt(NULL);
+ /*
+ * Call timer_interrupt routine in interrupts.c
+ */
+ timer_interrupt(NULL);
}
diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c
index 406f825..cc2c49c 100644
--- a/cpu/pxa/i2c.c
+++ b/cpu/pxa/i2c.c
@@ -36,16 +36,16 @@
#ifdef CONFIG_HARD_I2C
-/*
- * - CFG_I2C_SPEED
- * - I2C_PXA_SLAVE_ADDR
+/*
+ * - CFG_I2C_SPEED
+ * - I2C_PXA_SLAVE_ADDR
*/
#include <asm/arch/hardware.h>
#include <asm/arch/pxa-regs.h>
#include <i2c.h>
-//#define DEBUG_I2C 1 /* activate local debugging output */
+/*#define DEBUG_I2C 1 /###* activate local debugging output */
#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */
#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
#define I2C_ISR_INIT 0x7FF
@@ -63,7 +63,7 @@
#define I2C_COND_STOP 2
/* Shall the current transfer be ack/nacked or being waited for it? */
-#define I2C_ACKNAK_WAITACK 1
+#define I2C_ACKNAK_WAITACK 1
#define I2C_ACKNAK_SENDACK 2
#define I2C_ACKNAK_SENDNAK 4
@@ -74,37 +74,37 @@
/* All transfers are described by this data structure */
struct i2c_msg {
u8 condition;
- u8 acknack;
- u8 direction;
+ u8 acknack;
+ u8 direction;
u8 data;
};
/**
- * i2c_pxa_reset: - reset the host controller
+ * i2c_pxa_reset: - reset the host controller
*
*/
static void i2c_reset( void )
{
ICR &= ~ICR_IUE; /* disable unit */
- ICR |= ICR_UR; /* reset the unit */
- udelay(100);
- ICR &= ~ICR_IUE; /* disable unit */
- CKEN |= CKEN14_I2C; /* set the global I2C clock on */
- ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
- ICR = I2C_ICR_INIT; /* set control register values */
- ISR = I2C_ISR_INIT; /* set clear interrupt bits */
- ICR |= ICR_IUE; /* enable unit */
- udelay(100);
+ ICR |= ICR_UR; /* reset the unit */
+ udelay(100);
+ ICR &= ~ICR_IUE; /* disable unit */
+ CKEN |= CKEN14_I2C; /* set the global I2C clock on */
+ ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
+ ICR = I2C_ICR_INIT; /* set control register values */
+ ISR = I2C_ISR_INIT; /* set clear interrupt bits */
+ ICR |= ICR_IUE; /* enable unit */
+ udelay(100);
}
/**
- * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
+ * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
* are set and cleared
*
- * @return: 0 in case of success, 1 means timeout (no match within 10 ms).
+ * @return: 0 in case of success, 1 means timeout (no match within 10 ms).
*/
static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
@@ -116,15 +116,15 @@
if( timeout-- < 0 ) return 0;
}
- return 1;
+ return 1;
}
/**
* i2c_transfer: - Transfer one byte over the i2c bus
*
- * This function can tranfer a byte over the i2c bus in both directions.
- * It is used by the public API functions.
+ * This function can tranfer a byte over the i2c bus in both directions.
+ * It is used by the public API functions.
*
* @return: 0: transfer successful
* -1: message is empty
@@ -133,12 +133,12 @@
* -4: receive timeout
* -5: illegal parameters
* -6: bus is busy and couldn't be aquired
- */
+ */
int i2c_transfer(struct i2c_msg *msg)
{
int ret;
- if (!msg)
+ if (!msg)
goto transfer_error_msg_empty;
switch(msg->direction) {
@@ -154,14 +154,14 @@
ICR &= ~ICR_STOP;
IDBR = msg->data;
if (msg->condition == I2C_COND_START) ICR |= ICR_START;
- if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
+ if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
ICR &= ~ICR_ALDIE;
- ICR |= ICR_TB;
+ ICR |= ICR_TB;
/* transmit register empty? */
- if (!i2c_isr_set_cleared(ISR_ITE,0))
+ if (!i2c_isr_set_cleared(ISR_ITE,0))
goto transfer_error_transmit_timeout;
/* clear 'transmit empty' state */
@@ -169,7 +169,7 @@
/* wait for ACK from slave */
if (msg->acknack == I2C_ACKNAK_WAITACK)
- if (!i2c_isr_set_cleared(0,ISR_ACKNAK))
+ if (!i2c_isr_set_cleared(0,ISR_ACKNAK))
goto transfer_error_ack_missing;
break;
@@ -190,8 +190,8 @@
ICR |= ICR_TB;
/* receive register full? */
- if (!i2c_isr_set_cleared(ISR_IRF,0))
- goto transfer_error_receive_timeout;
+ if (!i2c_isr_set_cleared(ISR_IRF,0))
+ goto transfer_error_receive_timeout;
msg->data = IDBR;
@@ -206,9 +206,9 @@
}
- return 0;
+ return 0;
-transfer_error_msg_empty:
+transfer_error_msg_empty:
PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
ret = -1; goto i2c_transfer_finish;
@@ -245,7 +245,7 @@
void i2c_init(int speed, int slaveaddr)
{
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CFG_I2C_INIT_BOARD
/* call board specific i2c bus reset routine before accessing the */
/* environment, which might be in a chip on that bus. For details */
/* about this problem see doc/I2C_Edge_Conditions. */
@@ -257,7 +257,7 @@
/**
* i2c_probe: - Test if a chip answers for a given i2c address
*
- * @chip: address of the chip which is searched for
+ * @chip: address of the chip which is searched for
* @return: 0 if a chip was found, -1 otherwhise
*/
@@ -287,7 +287,7 @@
* i2c_read: - Read multiple bytes from an i2c device
*
* The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
+ * called with len < page length of the device (see configuration file)
*
* @chip: address of the chip which is to be read
* @addr: i2c data address within the chip
@@ -315,12 +315,12 @@
msg.data = (chip << 1);
msg.data &= 0xFE;
if ((ret=i2c_transfer(&msg))) return -1;
-
+
/*
- * send memory address bytes;
- * alen defines how much bytes we have to send.
+ * send memory address bytes;
+ * alen defines how much bytes we have to send.
*/
- //addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1);
+ /*addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); */
addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
@@ -334,7 +334,7 @@
msg.data = addr_bytes[alen];
if ((ret=i2c_transfer(&msg))) return -1;
}
-
+
/* start read sequence */
PRINTD(("i2c_read: start read sequence\n"));
@@ -348,7 +348,7 @@
/* read bytes; send NACK at last byte */
while (len--) {
- if (len==0) {
+ if (len==0) {
msg.condition = I2C_COND_STOP;
msg.acknack = I2C_ACKNAK_SENDNAK;
} else {
@@ -376,12 +376,12 @@
* i2c_write: - Write multiple bytes to an i2c device
*
* The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
+ * called with len < page length of the device (see configuration file)
*
* @chip: address of the chip which is to be written
* @addr: i2c data address within the chip
* @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to find the data to be written
+ * @buffer: where to find the data to be written
* @len: how much byte do we want to read
* @return: 0 in case of success
*/
@@ -403,10 +403,10 @@
msg.data = (chip << 1);
msg.data &= 0xFE;
if (i2c_transfer(&msg)) return -1;
-
+
/*
- * send memory address bytes;
- * alen defines how much bytes we have to send.
+ * send memory address bytes;
+ * alen defines how much bytes we have to send.
*/
addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
@@ -421,13 +421,13 @@
msg.data = addr_bytes[alen];
if (i2c_transfer(&msg)) return -1;
}
-
+
/* write bytes; send NACK at last byte */
while (len--) {
PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
- if (len==0)
+ if (len==0)
msg.condition = I2C_COND_STOP;
else
msg.condition = I2C_COND_NORMAL;
@@ -435,7 +435,7 @@
msg.acknack = I2C_ACKNAK_WAITACK;
msg.direction = I2C_WRITE;
msg.data = *(buffer++);
-
+
if (i2c_transfer(&msg)) return -1;
}
diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c
index af7d634..cf529f4 100644
--- a/cpu/pxa/interrupts.c
+++ b/cpu/pxa/interrupts.c
@@ -59,7 +59,6 @@
#endif
-
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c
index 783e90c..9e6e1e3 100644
--- a/cpu/pxa/mmc.c
+++ b/cpu/pxa/mmc.c
@@ -32,7 +32,7 @@
extern int
fat_register_read(int(*block_read)(int device, ulong blknr, ulong blkcnt, uchar *buffer));
-/*
+/*
* FIXME needs to read cid and csd info to determine block size
* and other parameters
*/
@@ -41,7 +41,7 @@
static int mmc_ready = 0;
-static uchar *
+static uchar *
/****************************************************/
mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat)
/****************************************************/
@@ -54,7 +54,7 @@
MMC_STRPCL = MMC_STRPCL_STOP_CLK;
MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF;
while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF));
- MMC_CMD = cmd;
+ MMC_CMD = cmd;
MMC_ARGH = argh;
MMC_ARGL = argl;
MMC_CMDAT = cmdat;
@@ -73,11 +73,11 @@
{
case MMC_CMDAT_R1:
case MMC_CMDAT_R3:
- words = 3;
+ words = 3;
break;
case MMC_CMDAT_R2:
- words = 8;
+ words = 8;
break;
default:
@@ -130,10 +130,10 @@
MMC_RDTO = 0xffff;
MMC_NOB = 1;
MMC_BLKLEN = len;
- resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl,
+ resp = mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl,
MMC_CMDAT_R1|MMC_CMDAT_READ|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);
-
+
MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ;
while (len)
{
@@ -188,9 +188,9 @@
MMC_STRPCL = MMC_STRPCL_STOP_CLK;
MMC_NOB = 1;
MMC_BLKLEN = len;
- resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl,
+ resp = mmc_cmd(MMC_CMD_WRITE_BLOCK, argh, argl,
MMC_CMDAT_R1|MMC_CMDAT_WRITE|MMC_CMDAT_BLOCK|MMC_CMDAT_DATA_EN);
-
+
MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ;
while (len)
{
@@ -379,7 +379,7 @@
return 0;
}
-int
+int
/****************************************************/
mmc_bread(int dev_num, ulong blknr, ulong blkcnt, uchar *dst)
/****************************************************/
@@ -408,7 +408,7 @@
mmc_csd.c_size = 0;
MMC_CLKRT = MMC_CLKRT_0_3125MHZ;
- MMC_RESTO = MMC_RES_TO_MAX;
+ MMC_RESTO = MMC_RES_TO_MAX;
MMC_SPI = MMC_SPI_DISABLE;
/* reset */
@@ -431,12 +431,12 @@
if (verbose)
{
printf("MMC found. Card desciption is:\n");
- printf("Manufacturer ID = %02x%02x%02x\n",
+ printf("Manufacturer ID = %02x%02x%02x\n",
cid->id[0], cid->id[1], cid->id[2]);
printf("HW/FW Revision = %x %x\n",cid->hwrev, cid->fwrev);
cid->hwrev = cid->fwrev = 0; /* null terminate string */
printf("Product Name = %s\n",cid->name);
- printf("Serial Number = %02x%02x%02x\n",
+ printf("Serial Number = %02x%02x%02x\n",
cid->sn[0], cid->sn[1], cid->sn[2]);
printf("Month = %d\n",cid->month);
printf("Year = %d\n",1997 + cid->year);
diff --git a/cpu/pxa/pxafb.c b/cpu/pxa/pxafb.c
index f6a2575..ef60d4a 100644
--- a/cpu/pxa/pxafb.c
+++ b/cpu/pxa/pxafb.c
@@ -52,7 +52,7 @@
#undef CONFIG_LCD_LOGO
-#define LCD_TEST_PATTERN
+#define LCD_TEST_PATTERN
/* #define LCD_TEST_PATTERN */ /* color backgnd for frame/color adjust */
/* #define CFG_INVERT_COLORS */ /* Not needed - adjust vl_dp instead */
/************************************************************************/
@@ -163,31 +163,31 @@
/* you have to set lccr0 and lccr3 (including pcd) */
#define REG_LCCR0 0x003008f8
-#define REG_LCCR3 0x0300FF01
+#define REG_LCCR3 0x0300FF01
/* 640x480x16 @ 61 Hz */
static vidinfo_t panel_info = {
- vl_col: 640,
+ vl_col: 640,
vl_row: 480,
vl_width: 640,
vl_height: 480,
vl_clkp: CFG_HIGH,
- vl_oep: CFG_HIGH,
+ vl_oep: CFG_HIGH,
vl_hsp: CFG_HIGH,
- vl_vsp: CFG_HIGH,
- vl_dp: CFG_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
+ vl_vsp: CFG_HIGH,
+ vl_dp: CFG_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
vl_splt: 0,
- vl_clor: 0,
+ vl_clor: 0,
vl_lcdac: 0,
- vl_tft: 1,
- vl_hpw: 40,
- vl_blw: 56,
- vl_elw: 56,
- vl_vpw: 20,
- vl_bfw: 8,
- vl_efw: 8,
+ vl_tft: 1,
+ vl_hpw: 40,
+ vl_blw: 56,
+ vl_elw: 56,
+ vl_vpw: 20,
+ vl_bfw: 8,
+ vl_efw: 8,
};
#endif /* CONFIG_PXA_VIDEO */
@@ -198,30 +198,30 @@
/* you have to set lccr0 and lccr3 (including pcd) */
#define REG_LCCR0 0x0030087C
-#define REG_LCCR3 0x0340FF08
+#define REG_LCCR3 0x0340FF08
static vidinfo_t panel_info = {
- vl_col: 640,
+ vl_col: 640,
vl_row: 480,
vl_width: 157,
vl_height: 118,
vl_clkp: CFG_HIGH,
- vl_oep: CFG_HIGH,
+ vl_oep: CFG_HIGH,
vl_hsp: CFG_HIGH,
- vl_vsp: CFG_HIGH,
- vl_dp: CFG_HIGH,
- vl_bpix: LCD_BPP,
- vl_lbw: 0,
+ vl_vsp: CFG_HIGH,
+ vl_dp: CFG_HIGH,
+ vl_bpix: LCD_BPP,
+ vl_lbw: 0,
vl_splt: 1,
- vl_clor: 1,
+ vl_clor: 1,
vl_lcdac: 0,
- vl_tft: 0,
- vl_hpw: 1,
- vl_blw: 3,
- vl_elw: 3,
- vl_vpw: 1,
- vl_bfw: 0,
- vl_efw: 0,
+ vl_tft: 0,
+ vl_hpw: 1,
+ vl_blw: 3,
+ vl_elw: 3,
+ vl_vpw: 1,
+ vl_bfw: 0,
+ vl_efw: 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
@@ -721,7 +721,7 @@
static void lcd_ctrl_init (void *lcdbase)
{
- pxafb_init_mem(lcdbase, &panel_info);
+ pxafb_init_mem(lcdbase, &panel_info);
pxafb_init(&panel_info);
pxafb_setup_gpio(&panel_info);
pxafb_enable_controller(&panel_info);
@@ -745,7 +745,7 @@
struct pxafb_info *fbi = &panel_info.pxa;
unsigned short *palette = (unsigned short *)fbi->palette;
u_int val;
-
+
if (regno < fbi->palette_size) {
val = ((red << 8) & 0xf800);
val |= ((green << 4) & 0x07e0);
@@ -1011,18 +1011,18 @@
LCCR1_HorSnchWdth(vid->vl_hpw) +
LCCR1_BegLnDel(vid->vl_blw) +
LCCR1_EndLnDel(vid->vl_elw);
-
+
fbi->reg_lccr2 =
LCCR2_DisHght(vid->vl_row) +
LCCR2_VrtSnchWdth(vid->vl_vpw) +
LCCR2_BegFrmDel(vid->vl_bfw) +
LCCR2_EndFrmDel(vid->vl_efw);
- fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
- fbi->reg_lccr3 |=
- (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
+ fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
+ fbi->reg_lccr3 |=
+ (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
-
+
/* setup dma descriptors */
fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
@@ -1030,9 +1030,9 @@
fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
#define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
- (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
- (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
-
+ (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
+ (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
+
/* populate descriptors */
fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
@@ -1040,7 +1040,7 @@
fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
-
+
fbi->dmadesc_fbhigh->fsadr = fbi->screen;
fbi->dmadesc_fbhigh->fidr = 0;
fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
@@ -1055,7 +1055,7 @@
fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
/* flips back and forth between pal and fbhigh */
- fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
+ fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
}
else
{
@@ -1079,7 +1079,7 @@
debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
-
+
return 0;
}
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
index 95b30e4..c2b75da 100644
--- a/cpu/pxa/start.S
+++ b/cpu/pxa/start.S
@@ -86,8 +86,8 @@
/*
* This is defined in the board specific linker script
*/
-.globl _bss_start
-_bss_start:
+.globl _bss_start
+_bss_start:
.word bss_start
.globl _bss_end
@@ -138,7 +138,7 @@
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
- ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
@@ -172,7 +172,7 @@
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
- bne clbss_l
+ bne clbss_l
ldr pc, _start_armboot
@@ -471,4 +471,3 @@
reset_endless:
b reset_endless
-
diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c
index be52849..75f939c 100644
--- a/cpu/sa1100/interrupts.c
+++ b/cpu/sa1100/interrupts.c
@@ -75,7 +75,6 @@
#endif
-
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
diff --git a/cpu/sa1100/start.S b/cpu/sa1100/start.S
index c0f30f5..82f094a 100644
--- a/cpu/sa1100/start.S
+++ b/cpu/sa1100/start.S
@@ -26,7 +26,6 @@
*/
-
#include <config.h>
#include <version.h>
@@ -242,8 +241,6 @@
mov pc, lr
-
-
/*
*************************************************************************
*