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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
David Feng12916822013-12-14 11:47:37 +08002/*
3 * Configuration for Versatile Express. Parts were derived from other ARM
4 * configurations.
David Feng12916822013-12-14 11:47:37 +08005 */
6
7#ifndef __VEXPRESS_AEMV8A_H
8#define __VEXPRESS_AEMV8A_H
9
David Feng12916822013-12-14 11:47:37 +080010#define CONFIG_REMAKE_ELF
11
David Feng12916822013-12-14 11:47:37 +080012/* Link Definitions */
Tom Rini00179312021-09-03 10:40:28 -040013#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
Darwin Rambo261d2762014-06-09 11:12:59 -070014/* ATF loads u-boot here for BASE_FVP model */
Darwin Rambo261d2762014-06-09 11:12:59 -070015#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
Tom Rini00179312021-09-03 10:40:28 -040016#elif CONFIG_TARGET_VEXPRESS64_JUNO
17#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
Darwin Rambo261d2762014-06-09 11:12:59 -070018#endif
David Feng12916822013-12-14 11:47:37 +080019
Ryan Harkin0d3012a2015-10-09 17:18:01 +010020#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
21
David Feng12916822013-12-14 11:47:37 +080022/* CS register bases for the original memory map. */
Tom Rini00179312021-09-03 10:40:28 -040023#define V2M_PA_CS0 0x00000000
24#define V2M_PA_CS1 0x14000000
25#define V2M_PA_CS2 0x18000000
26#define V2M_PA_CS3 0x1c000000
27#define V2M_PA_CS4 0x0c000000
28#define V2M_PA_CS5 0x10000000
David Feng12916822013-12-14 11:47:37 +080029
30#define V2M_PERIPH_OFFSET(x) (x << 16)
31#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
32#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
33#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
34
Tom Rini00179312021-09-03 10:40:28 -040035#define V2M_BASE 0x80000000
36
David Feng12916822013-12-14 11:47:37 +080037/* Common peripherals relative to CS7. */
38#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
39#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
40#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
41#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
42
Linus Walleijffc10372015-01-23 14:41:10 +010043#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
44#define V2M_UART0 0x7ff80000
45#define V2M_UART1 0x7ff70000
46#else /* Not Juno */
David Feng12916822013-12-14 11:47:37 +080047#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
48#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
49#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
50#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
Linus Walleijffc10372015-01-23 14:41:10 +010051#endif
David Feng12916822013-12-14 11:47:37 +080052
53#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
54
55#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
56#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
57
58#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
59#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
60
61#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
62
63#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
64
65/* System register offsets. */
66#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
67#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
68#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
69
70/* Generic Timer Definitions */
Tom Rini00179312021-09-03 10:40:28 -040071#define COUNTER_FREQUENCY 24000000 /* 24MHz */
David Feng12916822013-12-14 11:47:37 +080072
73/* Generic Interrupt Controller Definitions */
David Fengc71645a2014-03-14 14:26:27 +080074#ifdef CONFIG_GICV3
Tom Rini00179312021-09-03 10:40:28 -040075#define GICD_BASE (0x2f000000)
76#define GICR_BASE (0x2f100000)
David Fengc71645a2014-03-14 14:26:27 +080077#else
Darwin Rambo261d2762014-06-09 11:12:59 -070078
Tom Rini00179312021-09-03 10:40:28 -040079#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
80#define GICD_BASE (0x2f000000)
81#define GICC_BASE (0x2c000000)
82#elif CONFIG_TARGET_VEXPRESS64_JUNO
Linus Walleijffc10372015-01-23 14:41:10 +010083#define GICD_BASE (0x2C010000)
84#define GICC_BASE (0x2C02f000)
David Fengc71645a2014-03-14 14:26:27 +080085#endif
Linus Walleij03314f02015-03-23 11:06:14 +010086#endif /* !CONFIG_GICV3 */
David Feng12916822013-12-14 11:47:37 +080087
Adam Ford8daec2d2017-09-05 15:20:44 -050088#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
Linus Walleijb31f9d72015-02-17 11:35:25 +010089/* The Vexpress64 simulators use SMSC91C111 */
Bhupesh Sharma3865ceb2014-01-16 09:47:40 -060090#define CONFIG_SMC91111 1
Tom Rini00179312021-09-03 10:40:28 -040091#define CONFIG_SMC91111_BASE (0x01A000000)
Linus Walleijb31f9d72015-02-17 11:35:25 +010092#endif
David Feng12916822013-12-14 11:47:37 +080093
94/* PL011 Serial Configuration */
Linus Walleijffc10372015-01-23 14:41:10 +010095#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywaradeaa5112020-04-27 19:18:00 +010096#define CONFIG_PL011_CLOCK 7372800
Linus Walleijffc10372015-01-23 14:41:10 +010097#else
David Feng12916822013-12-14 11:47:37 +080098#define CONFIG_PL011_CLOCK 24000000
Linus Walleijffc10372015-01-23 14:41:10 +010099#endif
David Feng12916822013-12-14 11:47:37 +0800100
David Feng12916822013-12-14 11:47:37 +0800101/* BOOTP options */
102#define CONFIG_BOOTP_BOOTFILESIZE
David Feng12916822013-12-14 11:47:37 +0800103
104/* Miscellaneous configurable options */
David Feng12916822013-12-14 11:47:37 +0800105
106/* Physical Memory Map */
David Feng12916822013-12-14 11:47:37 +0800107#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
Linus Walleij30355702015-05-11 10:03:57 +0200108/* Top 16MB reserved for secure world use */
109#define DRAM_SEC_SIZE 0x01000000
110#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
111#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
112
Ryan Harkin2c2b2182015-11-18 10:39:07 +0000113#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Ryan Harkin2c2b2182015-11-18 10:39:07 +0000114#define PHYS_SDRAM_2 (0x880000000)
115#define PHYS_SDRAM_2_SIZE 0x180000000
Tom Rini00179312021-09-03 10:40:28 -0400116#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
Diego Sueiro9abe5e62021-02-15 07:27:57 +0000117#define PHYS_SDRAM_2 (0x880000000)
118#define PHYS_SDRAM_2_SIZE 0x80000000
Ryan Harkin2c2b2182015-11-18 10:39:07 +0000119#endif
120
Linus Walleij30355702015-05-11 10:03:57 +0200121/* Enable memtest */
David Feng12916822013-12-14 11:47:37 +0800122
123/* Initial environment variables */
Linus Walleij10d14912015-04-05 01:48:32 +0200124#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywarad3c1b512021-07-12 00:25:15 +0100125/* Copy the kernel and FDT to DRAM memory and boot */
126#define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
127 "bootcmd_afs=" \
128 "afs load ${kernel_name} ${kernel_addr_r} ;"\
129 "if test $? -eq 1; then "\
130 " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
131 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
132 "fi ; "\
133 "afs load ${fdtfile} ${fdt_addr_r} ;"\
134 "if test $? -eq 1; then "\
135 " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
136 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
137 "fi ; "\
138 "fdt addr ${fdt_addr_r}; fdt resize; " \
139 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
140 "then "\
141 " setenv ramdisk_param ${ramdisk_addr_r}; "\
142 "else "\
143 " setenv ramdisk_param -; "\
144 "fi ; " \
145 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
146#define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
147
148#define BOOT_TARGET_DEVICES(func) \
149 func(USB, usb, 0) \
150 func(SATA, sata, 0) \
151 func(SATA, sata, 1) \
152 func(PXE, pxe, na) \
153 func(DHCP, dhcp, na) \
154 func(AFS, afs, na)
155
156#include <config_distro_bootcmd.h>
157
Linus Walleij10d14912015-04-05 01:48:32 +0200158/*
159 * Defines where the kernel and FDT exist in NOR flash and where it will
160 * be copied into DRAM
161 */
162#define CONFIG_EXTRA_ENV_SETTINGS \
Ryan Harkinecbed5d2015-10-09 17:18:07 +0100163 "kernel_name=norkern\0" \
164 "kernel_alt_name=Image\0" \
Andre Przywara7d6dae02020-04-27 19:17:58 +0100165 "kernel_addr_r=0x80080000\0" \
166 "ramdisk_name=ramdisk.img\0" \
167 "ramdisk_addr_r=0x88000000\0" \
Alexander Grafda3e6202016-03-04 01:10:11 +0100168 "fdtfile=board.dtb\0" \
Ryan Harkinecbed5d2015-10-09 17:18:07 +0100169 "fdt_alt_name=juno\0" \
Andre Przywara7d6dae02020-04-27 19:17:58 +0100170 "fdt_addr_r=0x80000000\0" \
Andre Przywarad3c1b512021-07-12 00:25:15 +0100171 BOOTENV
Linus Walleij10d14912015-04-05 01:48:32 +0200172
173#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
David Feng12916822013-12-14 11:47:37 +0800174#define CONFIG_EXTRA_ENV_SETTINGS \
Linus Walleij1fd0f922015-05-27 09:45:39 +0200175 "kernel_name=Image\0" \
Andre Przywara7babe482016-01-04 15:43:36 +0000176 "kernel_addr=0x80080000\0" \
Darwin Rambo261d2762014-06-09 11:12:59 -0700177 "initrd_name=ramdisk.img\0" \
Linus Walleij49995ff2015-03-23 11:06:12 +0100178 "initrd_addr=0x88000000\0" \
Alexander Grafda3e6202016-03-04 01:10:11 +0100179 "fdtfile=devtree.dtb\0" \
Linus Walleij49995ff2015-03-23 11:06:12 +0100180 "fdt_addr=0x83000000\0" \
Peter Collingbourneec8eef52020-04-03 19:58:24 -0700181 "boot_name=boot.img\0" \
182 "boot_addr=0x8007f800\0"
Darwin Rambo261d2762014-06-09 11:12:59 -0700183
Stanislav Pinchukef7db7a2021-01-20 21:54:53 +0300184#ifndef CONFIG_BOOTCOMMAND
Peter Collingbourneec8eef52020-04-03 19:58:24 -0700185#define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \
186 " set bootargs; " \
187 " abootimg addr ${boot_addr}; " \
188 " abootimg get dtb --index=0 fdt_addr; " \
189 " bootm ${boot_addr} ${boot_addr} " \
190 " ${fdt_addr}; " \
191 "else; " \
192 " set fdt_high 0xffffffffffffffff; " \
193 " set initrd_high 0xffffffffffffffff; " \
194 " smhload ${kernel_name} ${kernel_addr}; " \
195 " smhload ${fdtfile} ${fdt_addr}; " \
196 " smhload ${initrd_name} ${initrd_addr} "\
197 " initrd_end; " \
198 " fdt addr ${fdt_addr}; fdt resize; " \
199 " fdt chosen ${initrd_addr} ${initrd_end}; " \
200 " booti $kernel_addr - $fdt_addr; " \
201 "fi"
Stanislav Pinchukef7db7a2021-01-20 21:54:53 +0300202#endif
Darwin Rambo261d2762014-06-09 11:12:59 -0700203#endif
David Feng12916822013-12-14 11:47:37 +0800204
David Feng12916822013-12-14 11:47:37 +0800205/* Monitor Command Prompt */
206#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
David Feng12916822013-12-14 11:47:37 +0800207#define CONFIG_SYS_MAXARGS 64 /* max command args */
208
Ryan Harkinf3c71c92015-11-18 10:39:09 +0000209#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
210#define CONFIG_SYS_FLASH_BASE 0x08000000
211/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
212#define CONFIG_SYS_MAX_FLASH_SECT 259
213/* Store environment at top of flash in the same location as blank.img */
214/* in the Juno firmware. */
Linus Walleij14f264e2015-02-19 17:19:37 +0100215#else
Tom Rini00179312021-09-03 10:40:28 -0400216#define CONFIG_SYS_FLASH_BASE 0x0C000000
Ryan Harkinf3c71c92015-11-18 10:39:09 +0000217/* 256 x 256KiB sectors */
218#define CONFIG_SYS_MAX_FLASH_SECT 256
219/* Store environment at top of flash */
Ryan Harkinf3c71c92015-11-18 10:39:09 +0000220#endif
221
Ryan Harkinf19f3892015-05-08 18:07:52 +0100222#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
Ryan Harkinf3c71c92015-11-18 10:39:09 +0000223#define CONFIG_SYS_MAX_FLASH_BANKS 1
Linus Walleij14f264e2015-02-19 17:19:37 +0100224
Andre Przywara56e403d2020-04-27 19:18:03 +0100225#ifdef CONFIG_USB_EHCI_HCD
226#define CONFIG_USB_OHCI_NEW
227#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
228#endif
229
Linus Walleij14f264e2015-02-19 17:19:37 +0100230#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
Ryan Harkinf3c71c92015-11-18 10:39:09 +0000231#define FLASH_MAX_SECTOR_SIZE 0x00040000
Linus Walleij14f264e2015-02-19 17:19:37 +0100232
David Feng12916822013-12-14 11:47:37 +0800233#endif /* __VEXPRESS_AEMV8A_H */