blob: 67caa063c9a38f93f6399d442462efe25924d9ca [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk3d3befa2004-03-14 15:06:13 +00002/*
3 * (C) Copyright 2000
4 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
5 *
6 * (C) Copyright 2004
7 * ARM Ltd.
8 * Philippe Robin, <philippe.robin@arm.com>
wdenk3d3befa2004-03-14 15:06:13 +00009 */
10
Andreas Engel48d01922008-09-08 14:30:53 +020011/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
wdenk3d3befa2004-03-14 15:06:13 +000012
13#include <common.h>
Simon Glass401d1c42020-10-30 21:38:53 -060014#include <asm/global_data.h>
Andre Przywarae3e2d662020-04-27 19:17:59 +010015/* For get_bus_freq() */
16#include <clock_legacy.h>
Simon Glass8a9cd5a2014-09-22 17:30:58 -060017#include <dm.h>
Andre Przywarae3e2d662020-04-27 19:17:59 +010018#include <clk.h>
Simon Glassaed2fbe2014-09-22 17:30:57 -060019#include <errno.h>
Stuart Wood8b616ed2008-06-02 16:42:19 -040020#include <watchdog.h>
Matt Waddel249d5212010-10-07 15:48:46 -060021#include <asm/io.h>
Marek Vasut39f61472012-09-14 22:38:46 +020022#include <serial.h>
Michal Simek6c9662d2020-10-13 15:00:24 +020023#include <dm/device_compat.h>
Masahiro Yamada86256b72014-10-24 12:41:19 +090024#include <dm/platform_data/serial_pl01x.h>
Marek Vasut39f61472012-09-14 22:38:46 +020025#include <linux/compiler.h>
Simon Glassaed2fbe2014-09-22 17:30:57 -060026#include "serial_pl01x_internal.h"
Vikas Manocha69751722015-05-06 11:46:29 -070027
28DECLARE_GLOBAL_DATA_PTR;
wdenk3d3befa2004-03-14 15:06:13 +000029
Simon Glass8a9cd5a2014-09-22 17:30:58 -060030#ifndef CONFIG_DM_SERIAL
31
wdenk6705d812004-08-02 23:22:59 +000032static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
Marek BehĂșn236f2ec2021-05-20 13:23:52 +020033static enum pl01x_type pl01x_type __section(".data");
34static struct pl01x_regs *base_regs __section(".data");
wdenk6705d812004-08-02 23:22:59 +000035#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
wdenk3d3befa2004-03-14 15:06:13 +000036
Simon Glass8a9cd5a2014-09-22 17:30:58 -060037#endif
wdenk3d3befa2004-03-14 15:06:13 +000038
Simon Glassaed2fbe2014-09-22 17:30:57 -060039static int pl01x_putc(struct pl01x_regs *regs, char c)
Rabin Vincent72d5e442010-05-05 09:23:07 +053040{
wdenk42dfe7a2004-03-14 22:25:36 +000041 /* Wait until there is space in the FIFO */
Simon Glassaed2fbe2014-09-22 17:30:57 -060042 if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
43 return -EAGAIN;
wdenk42dfe7a2004-03-14 22:25:36 +000044
45 /* Send the character */
Rabin Vincent72d5e442010-05-05 09:23:07 +053046 writel(c, &regs->dr);
Simon Glassaed2fbe2014-09-22 17:30:57 -060047
48 return 0;
wdenk3d3befa2004-03-14 15:06:13 +000049}
50
Simon Glassaed2fbe2014-09-22 17:30:57 -060051static int pl01x_getc(struct pl01x_regs *regs)
wdenk3d3befa2004-03-14 15:06:13 +000052{
wdenk42dfe7a2004-03-14 22:25:36 +000053 unsigned int data;
wdenk3d3befa2004-03-14 15:06:13 +000054
wdenk42dfe7a2004-03-14 22:25:36 +000055 /* Wait until there is data in the FIFO */
Simon Glassaed2fbe2014-09-22 17:30:57 -060056 if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
57 return -EAGAIN;
wdenk42dfe7a2004-03-14 22:25:36 +000058
Rabin Vincent72d5e442010-05-05 09:23:07 +053059 data = readl(&regs->dr);
wdenk42dfe7a2004-03-14 22:25:36 +000060
61 /* Check for an error flag */
62 if (data & 0xFFFFFF00) {
63 /* Clear the error */
Rabin Vincent72d5e442010-05-05 09:23:07 +053064 writel(0xFFFFFFFF, &regs->ecr);
wdenk42dfe7a2004-03-14 22:25:36 +000065 return -1;
66 }
67
68 return (int) data;
wdenk3d3befa2004-03-14 15:06:13 +000069}
70
Simon Glassaed2fbe2014-09-22 17:30:57 -060071static int pl01x_tstc(struct pl01x_regs *regs)
wdenk3d3befa2004-03-14 15:06:13 +000072{
Stuart Wood8b616ed2008-06-02 16:42:19 -040073 WATCHDOG_RESET();
Rabin Vincent72d5e442010-05-05 09:23:07 +053074 return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
wdenk3d3befa2004-03-14 15:06:13 +000075}
Marek Vasut39f61472012-09-14 22:38:46 +020076
Simon Glassaed2fbe2014-09-22 17:30:57 -060077static int pl01x_generic_serial_init(struct pl01x_regs *regs,
78 enum pl01x_type type)
79{
Simon Glassaed2fbe2014-09-22 17:30:57 -060080 switch (type) {
81 case TYPE_PL010:
Vikas Manochaf7e517b2014-11-21 10:34:22 -080082 /* disable everything */
83 writel(0, &regs->pl010_cr);
Simon Glassaed2fbe2014-09-22 17:30:57 -060084 break;
Vikas Manochad2ca9fd2014-11-21 10:34:21 -080085 case TYPE_PL011:
Vikas Manochaf7e517b2014-11-21 10:34:22 -080086 /* disable everything */
87 writel(0, &regs->pl011_cr);
Vikas Manochad2ca9fd2014-11-21 10:34:21 -080088 break;
89 default:
90 return -EINVAL;
91 }
92
93 return 0;
94}
95
Linus Walleijd77447f2015-04-21 15:10:06 +020096static int pl011_set_line_control(struct pl01x_regs *regs)
Vikas Manochad2ca9fd2014-11-21 10:34:21 -080097{
98 unsigned int lcr;
99 /*
100 * Internal update of baud rate register require line
101 * control register write
102 */
103 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
Vikas Manochad2ca9fd2014-11-21 10:34:21 -0800104 writel(lcr, &regs->pl011_lcrh);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600105 return 0;
106}
107
108static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
109 int clock, int baudrate)
110{
111 switch (type) {
112 case TYPE_PL010: {
113 unsigned int divisor;
114
Linus Walleijd77447f2015-04-21 15:10:06 +0200115 /* disable everything */
116 writel(0, &regs->pl010_cr);
117
Simon Glassaed2fbe2014-09-22 17:30:57 -0600118 switch (baudrate) {
119 case 9600:
120 divisor = UART_PL010_BAUD_9600;
121 break;
122 case 19200:
Alyssa Rosenzweigb2aa8892017-04-07 09:48:22 -0700123 divisor = UART_PL010_BAUD_19200;
Simon Glassaed2fbe2014-09-22 17:30:57 -0600124 break;
125 case 38400:
126 divisor = UART_PL010_BAUD_38400;
127 break;
128 case 57600:
129 divisor = UART_PL010_BAUD_57600;
130 break;
131 case 115200:
132 divisor = UART_PL010_BAUD_115200;
133 break;
134 default:
135 divisor = UART_PL010_BAUD_38400;
136 }
137
138 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
139 writel(divisor & 0xff, &regs->pl010_lcrl);
140
Linus Walleijd77447f2015-04-21 15:10:06 +0200141 /*
142 * Set line control for the PL010 to be 8 bits, 1 stop bit,
143 * no parity, fifo enabled
144 */
145 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
146 &regs->pl010_lcrh);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600147 /* Finally, enable the UART */
148 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
149 break;
150 }
151 case TYPE_PL011: {
152 unsigned int temp;
153 unsigned int divider;
154 unsigned int remainder;
155 unsigned int fraction;
156
Andre Przywarae3e2d662020-04-27 19:17:59 +0100157 /* Without a valid clock rate we cannot set up the baudrate. */
158 if (clock) {
159 /*
160 * Set baud rate
161 *
162 * IBRD = UART_CLK / (16 * BAUD_RATE)
163 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
164 * / (16 * BAUD_RATE))
165 */
166 temp = 16 * baudrate;
167 divider = clock / temp;
168 remainder = clock % temp;
169 temp = (8 * remainder) / baudrate;
170 fraction = (temp >> 1) + (temp & 1);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600171
Andre Przywarae3e2d662020-04-27 19:17:59 +0100172 writel(divider, &regs->pl011_ibrd);
173 writel(fraction, &regs->pl011_fbrd);
174 }
Simon Glassaed2fbe2014-09-22 17:30:57 -0600175
Linus Walleijd77447f2015-04-21 15:10:06 +0200176 pl011_set_line_control(regs);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600177 /* Finally, enable the UART */
178 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
179 UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
180 break;
181 }
182 default:
183 return -EINVAL;
184 }
185
186 return 0;
187}
188
189#ifndef CONFIG_DM_SERIAL
190static void pl01x_serial_init_baud(int baudrate)
191{
192 int clock = 0;
193
Tom Rinibc08dc52021-05-22 08:47:08 -0400194#if defined(CONFIG_PL011_SERIAL)
Simon Glassaed2fbe2014-09-22 17:30:57 -0600195 pl01x_type = TYPE_PL011;
196 clock = CONFIG_PL011_CLOCK;
197#endif
198 base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
199
200 pl01x_generic_serial_init(base_regs, pl01x_type);
Vikas Manochaa7deea62014-11-21 10:34:19 -0800201 pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
Simon Glassaed2fbe2014-09-22 17:30:57 -0600202}
203
204/*
205 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
206 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
207 * Versatile PB has four UARTs.
208 */
209int pl01x_serial_init(void)
210{
211 pl01x_serial_init_baud(CONFIG_BAUDRATE);
212
213 return 0;
214}
215
216static void pl01x_serial_putc(const char c)
217{
218 if (c == '\n')
219 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
220
221 while (pl01x_putc(base_regs, c) == -EAGAIN);
222}
223
224static int pl01x_serial_getc(void)
225{
226 while (1) {
227 int ch = pl01x_getc(base_regs);
228
229 if (ch == -EAGAIN) {
230 WATCHDOG_RESET();
231 continue;
232 }
233
234 return ch;
235 }
236}
237
238static int pl01x_serial_tstc(void)
239{
240 return pl01x_tstc(base_regs);
241}
242
243static void pl01x_serial_setbrg(void)
244{
245 /*
246 * Flush FIFO and wait for non-busy before changing baudrate to avoid
247 * crap in console
248 */
249 while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
250 WATCHDOG_RESET();
251 while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
252 WATCHDOG_RESET();
253 pl01x_serial_init_baud(gd->baudrate);
254}
255
Marek Vasut39f61472012-09-14 22:38:46 +0200256static struct serial_device pl01x_serial_drv = {
257 .name = "pl01x_serial",
258 .start = pl01x_serial_init,
259 .stop = NULL,
260 .setbrg = pl01x_serial_setbrg,
261 .putc = pl01x_serial_putc,
Marek Vasutec3fd682012-10-06 14:07:02 +0000262 .puts = default_serial_puts,
Marek Vasut39f61472012-09-14 22:38:46 +0200263 .getc = pl01x_serial_getc,
264 .tstc = pl01x_serial_tstc,
265};
266
267void pl01x_serial_initialize(void)
268{
269 serial_register(&pl01x_serial_drv);
270}
271
272__weak struct serial_device *default_serial_console(void)
273{
274 return &pl01x_serial_drv;
275}
Simon Glassaed2fbe2014-09-22 17:30:57 -0600276
277#endif /* nCONFIG_DM_SERIAL */
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600278
279#ifdef CONFIG_DM_SERIAL
280
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100281int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600282{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700283 struct pl01x_serial_plat *plat = dev_get_plat(dev);
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600284 struct pl01x_priv *priv = dev_get_priv(dev);
285
Eric Anholtcd0fa5b2016-03-13 18:16:54 -0700286 if (!plat->skip_init) {
287 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
288 baudrate);
289 }
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600290
291 return 0;
292}
293
Alexander Graf60019852018-01-25 12:05:55 +0100294int pl01x_serial_probe(struct udevice *dev)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600295{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700296 struct pl01x_serial_plat *plat = dev_get_plat(dev);
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600297 struct pl01x_priv *priv = dev_get_priv(dev);
298
299 priv->regs = (struct pl01x_regs *)plat->base;
300 priv->type = plat->type;
Eric Anholtcd0fa5b2016-03-13 18:16:54 -0700301 if (!plat->skip_init)
302 return pl01x_generic_serial_init(priv->regs, priv->type);
303 else
304 return 0;
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600305}
306
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100307int pl01x_serial_getc(struct udevice *dev)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600308{
309 struct pl01x_priv *priv = dev_get_priv(dev);
310
311 return pl01x_getc(priv->regs);
312}
313
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100314int pl01x_serial_putc(struct udevice *dev, const char ch)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600315{
316 struct pl01x_priv *priv = dev_get_priv(dev);
317
318 return pl01x_putc(priv->regs, ch);
319}
320
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100321int pl01x_serial_pending(struct udevice *dev, bool input)
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600322{
323 struct pl01x_priv *priv = dev_get_priv(dev);
324 unsigned int fr = readl(&priv->regs->fr);
325
326 if (input)
327 return pl01x_tstc(priv->regs);
328 else
329 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
330}
331
Alexander Grafc9bf43d2018-03-07 22:08:25 +0100332static const struct dm_serial_ops pl01x_serial_ops = {
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600333 .putc = pl01x_serial_putc,
334 .pending = pl01x_serial_pending,
335 .getc = pl01x_serial_getc,
336 .setbrg = pl01x_serial_setbrg,
337};
338
Masahiro Yamada0f925822015-08-12 07:31:55 +0900339#if CONFIG_IS_ENABLED(OF_CONTROL)
Vikas Manocha69751722015-05-06 11:46:29 -0700340static const struct udevice_id pl01x_serial_id[] ={
341 {.compatible = "arm,pl011", .data = TYPE_PL011},
342 {.compatible = "arm,pl010", .data = TYPE_PL010},
343 {}
344};
345
Andre Przywarae3e2d662020-04-27 19:17:59 +0100346#ifndef CONFIG_PL011_CLOCK
347#define CONFIG_PL011_CLOCK 0
348#endif
349
Simon Glassd1998a92020-12-03 16:55:21 -0700350int pl01x_serial_of_to_plat(struct udevice *dev)
Vikas Manocha69751722015-05-06 11:46:29 -0700351{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700352 struct pl01x_serial_plat *plat = dev_get_plat(dev);
Andre Przywarae3e2d662020-04-27 19:17:59 +0100353 struct clk clk;
Vikas Manocha69751722015-05-06 11:46:29 -0700354 fdt_addr_t addr;
Andre Przywarae3e2d662020-04-27 19:17:59 +0100355 int ret;
Vikas Manocha69751722015-05-06 11:46:29 -0700356
Masahiro Yamada25484932020-07-17 14:36:48 +0900357 addr = dev_read_addr(dev);
Vikas Manocha69751722015-05-06 11:46:29 -0700358 if (addr == FDT_ADDR_T_NONE)
359 return -EINVAL;
360
361 plat->base = addr;
Andre Przywarae3e2d662020-04-27 19:17:59 +0100362 plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
363 ret = clk_get_by_index(dev, 0, &clk);
364 if (!ret) {
Michal Simek6c9662d2020-10-13 15:00:24 +0200365 ret = clk_enable(&clk);
366 if (ret && ret != -ENOSYS) {
367 dev_err(dev, "failed to enable clock\n");
368 return ret;
369 }
370
Andre Przywarae3e2d662020-04-27 19:17:59 +0100371 plat->clock = clk_get_rate(&clk);
Michal Simek6c9662d2020-10-13 15:00:24 +0200372 if (IS_ERR_VALUE(plat->clock)) {
373 dev_err(dev, "failed to get rate\n");
374 return plat->clock;
375 }
376 debug("%s: CLK %d\n", __func__, plat->clock);
Andre Przywarae3e2d662020-04-27 19:17:59 +0100377 }
Vikas Manocha69751722015-05-06 11:46:29 -0700378 plat->type = dev_get_driver_data(dev);
Alexander Grafb3111632018-01-25 12:05:49 +0100379 plat->skip_init = dev_read_bool(dev, "skip-init");
380
Vikas Manocha69751722015-05-06 11:46:29 -0700381 return 0;
382}
383#endif
384
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600385U_BOOT_DRIVER(serial_pl01x) = {
386 .name = "serial_pl01x",
387 .id = UCLASS_SERIAL,
Vikas Manocha69751722015-05-06 11:46:29 -0700388 .of_match = of_match_ptr(pl01x_serial_id),
Simon Glassd1998a92020-12-03 16:55:21 -0700389 .of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
Simon Glass8a8d24b2020-12-03 16:55:23 -0700390 .plat_auto = sizeof(struct pl01x_serial_plat),
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600391 .probe = pl01x_serial_probe,
392 .ops = &pl01x_serial_ops,
393 .flags = DM_FLAG_PRE_RELOC,
Simon Glass41575d82020-12-03 16:55:17 -0700394 .priv_auto = sizeof(struct pl01x_priv),
Simon Glass8a9cd5a2014-09-22 17:30:58 -0600395};
396
397#endif
Sergey Temerkhanovb81406d2015-10-14 09:54:23 -0700398
399#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
400
401#include <debug_uart.h>
402
403static void _debug_uart_init(void)
404{
405#ifndef CONFIG_DEBUG_UART_SKIP_INIT
406 struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
Chen Baozi91a04382021-07-21 14:11:26 +0800407 enum pl01x_type type;
408
409 if (IS_ENABLED(CONFIG_DEBUG_UART_PL011))
410 type = TYPE_PL011;
411 else
412 type = TYPE_PL010;
Sergey Temerkhanovb81406d2015-10-14 09:54:23 -0700413
414 pl01x_generic_serial_init(regs, type);
415 pl01x_generic_setbrg(regs, type,
416 CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
417#endif
418}
419
420static inline void _debug_uart_putc(int ch)
421{
422 struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
423
Chen Baozi19820152021-07-19 15:36:04 +0800424 while (pl01x_putc(regs, ch) == -EAGAIN)
425 ;
Sergey Temerkhanovb81406d2015-10-14 09:54:23 -0700426}
427
428DEBUG_UART_FUNCS
429
430#endif