blob: dacc3406bb84ce55cb312a0a523b1da1050d7407 [file] [log] [blame]
wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
wdenkae3af052003-08-07 22:18:11 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkf4675562002-10-02 14:20:15 +000046
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000048
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
51#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010052 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk6aff3112002-12-17 01:51:00 +000053 "echo"
wdenkf4675562002-10-02 14:20:15 +000054
55#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000056
57#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000058 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000059 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000065 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000067 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000070 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020071 "hostname=TQM860L\0" \
72 "bootfile=TQM860L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020073 "fdt_addr=40040000\0" \
74 "kernel_addr=40060000\0" \
75 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020076 "u-boot=TQM860L/u-image.bin\0" \
77 "load=tftp 200000 ${u-boot}\0" \
78 "update=prot off 40000000 +${filesize};" \
79 "era 40000000 +${filesize};" \
80 "cp.b 200000 40000000 ${filesize};" \
81 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000082 ""
83#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000084
85#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
86#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
87
88#undef CONFIG_WATCHDOG /* watchdog disabled */
89
90#define CONFIG_STATUS_LED 1 /* Status LED enabled */
91
92#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93
Jon Loeliger37d4bb72007-07-09 21:38:02 -050094/*
95 * BOOTP options
96 */
97#define CONFIG_BOOTP_SUBNETMASK
98#define CONFIG_BOOTP_GATEWAY
99#define CONFIG_BOOTP_HOSTNAME
100#define CONFIG_BOOTP_BOOTPATH
101#define CONFIG_BOOTP_BOOTFILESIZE
102
wdenkf4675562002-10-02 14:20:15 +0000103
104#define CONFIG_MAC_PARTITION
105#define CONFIG_DOS_PARTITION
106
107#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
108
Jon Loeliger26946902007-07-04 22:30:50 -0500109
110/*
111 * Command line configuration.
112 */
113#include <config_cmd_default.h>
114
115#define CONFIG_CMD_ASKENV
116#define CONFIG_CMD_DATE
117#define CONFIG_CMD_DHCP
118#define CONFIG_CMD_ELF
119#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200120#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500121#define CONFIG_CMD_NFS
122#define CONFIG_CMD_SNTP
123
wdenkf4675562002-10-02 14:20:15 +0000124
wdenk68ceb292004-08-02 21:11:11 +0000125#define CONFIG_NETCONSOLE
126
wdenkf4675562002-10-02 14:20:15 +0000127/*
128 * Miscellaneous configurable options
129 */
130#define CFG_LONGHELP /* undef to save memory */
131#define CFG_PROMPT "=> " /* Monitor Command Prompt */
132
Wolfgang Denk2751a952006-10-28 02:29:14 +0200133#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
134#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf4675562002-10-02 14:20:15 +0000135#ifdef CFG_HUSH_PARSER
136#define CFG_PROMPT_HUSH_PS2 "> "
137#endif
138
Jon Loeliger26946902007-07-04 22:30:50 -0500139#if defined(CONFIG_CMD_KGDB)
wdenkf4675562002-10-02 14:20:15 +0000140#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
141#else
142#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
143#endif
144#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
145#define CFG_MAXARGS 16 /* max number of command args */
146#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
147
148#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
149#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
150
151#define CFG_LOAD_ADDR 0x100000 /* default load address */
152
153#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
154
155#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
156
157/*
158 * Low Level Configuration Settings
159 * (address mappings, register initial values, etc.)
160 * You should know what you are doing if you make changes here.
161 */
162/*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register
164 */
165#define CFG_IMMR 0xFFF00000
166
167/*-----------------------------------------------------------------------
168 * Definitions for initial stack pointer and data area (in DPRAM)
169 */
170#define CFG_INIT_RAM_ADDR CFG_IMMR
171#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
172#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
173#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
174#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175
176/*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
179 * Please note that CFG_SDRAM_BASE _must_ start at 0
180 */
181#define CFG_SDRAM_BASE 0x00000000
182#define CFG_FLASH_BASE 0x40000000
183#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
184#define CFG_MONITOR_BASE CFG_FLASH_BASE
185#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
186
187/*
188 * For booting Linux, the board info and command line data
189 * have to be in the first 8 MB of memory, since this is
190 * the maximum mapped by the Linux kernel during initialization.
191 */
192#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
193
194/*-----------------------------------------------------------------------
195 * FLASH organization
196 */
wdenkf4675562002-10-02 14:20:15 +0000197
Martin Krausee318d9e2007-09-27 11:10:08 +0200198/* use CFI flash driver */
199#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200200#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Wolfgang Denk3b8d17f2008-08-08 16:41:56 +0200201#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE+flash_info[0].size }
Martin Krausee318d9e2007-09-27 11:10:08 +0200202#define CFG_FLASH_EMPTY_INFO
203#define CFG_FLASH_USE_BUFFER_WRITE 1
204#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
205#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000206
207#define CFG_ENV_IS_IN_FLASH 1
208#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
209#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
210
211/* Address and size of Redundant Environment Sector */
212#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
213#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
214
Wolfgang Denk67c31032007-09-16 17:10:04 +0200215#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
216
wdenkf4675562002-10-02 14:20:15 +0000217/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200218 * Dynamic MTD partition support
219 */
220#define CONFIG_JFFS2_CMDLINE
221#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
222
223#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
224 "128k(dtb)," \
225 "1664k(kernel)," \
226 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200227 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200228
229/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000230 * Hardware Information Block
231 */
232#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
233#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
234#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
235
236/*-----------------------------------------------------------------------
237 * Cache Configuration
238 */
239#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500240#if defined(CONFIG_CMD_KGDB)
wdenkf4675562002-10-02 14:20:15 +0000241#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
242#endif
243
244/*-----------------------------------------------------------------------
245 * SYPCR - System Protection Control 11-9
246 * SYPCR can only be written once after reset!
247 *-----------------------------------------------------------------------
248 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
249 */
250#if defined(CONFIG_WATCHDOG)
251#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
252 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
253#else
254#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
255#endif
256
257/*-----------------------------------------------------------------------
258 * SIUMCR - SIU Module Configuration 11-6
259 *-----------------------------------------------------------------------
260 * PCMCIA config., multi-function pin tri-state
261 */
262#ifndef CONFIG_CAN_DRIVER
263#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
264#else /* we must activate GPL5 in the SIUMCR for CAN */
265#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
266#endif /* CONFIG_CAN_DRIVER */
267
268/*-----------------------------------------------------------------------
269 * TBSCR - Time Base Status and Control 11-26
270 *-----------------------------------------------------------------------
271 * Clear Reference Interrupt Status, Timebase freezing enabled
272 */
273#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
274
275/*-----------------------------------------------------------------------
276 * RTCSC - Real-Time Clock Status and Control Register 11-27
277 *-----------------------------------------------------------------------
278 */
279#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
280
281/*-----------------------------------------------------------------------
282 * PISCR - Periodic Interrupt Status and Control 11-31
283 *-----------------------------------------------------------------------
284 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
285 */
286#define CFG_PISCR (PISCR_PS | PISCR_PITF)
287
288/*-----------------------------------------------------------------------
289 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
290 *-----------------------------------------------------------------------
291 * Reset PLL lock status sticky bit, timer expired status bit and timer
292 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000293 */
wdenkf4675562002-10-02 14:20:15 +0000294#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000295
296/*-----------------------------------------------------------------------
297 * SCCR - System Clock and reset Control Register 15-27
298 *-----------------------------------------------------------------------
299 * Set clock output, timebase and RTC source and divider,
300 * power management and some other internal clocks
301 */
302#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000303#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000304 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
305 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000306
307/*-----------------------------------------------------------------------
308 * PCMCIA stuff
309 *-----------------------------------------------------------------------
310 *
311 */
312#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
313#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
314#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
315#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
316#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
317#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
318#define CFG_PCMCIA_IO_ADDR (0xEC000000)
319#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
320
321/*-----------------------------------------------------------------------
322 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
323 *-----------------------------------------------------------------------
324 */
325
326#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
327
328#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
329#undef CONFIG_IDE_LED /* LED for ide not supported */
330#undef CONFIG_IDE_RESET /* reset for ide not supported */
331
332#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
333#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
334
335#define CFG_ATA_IDE0_OFFSET 0x0000
336
337#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
338
339/* Offset for data I/O */
340#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
341
342/* Offset for normal register accesses */
343#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
344
345/* Offset for alternate registers */
346#define CFG_ATA_ALT_OFFSET 0x0100
347
348/*-----------------------------------------------------------------------
349 *
350 *-----------------------------------------------------------------------
351 *
352 */
wdenkf4675562002-10-02 14:20:15 +0000353#define CFG_DER 0
354
355/*
356 * Init Memory Controller:
357 *
358 * BR0/1 and OR0/1 (FLASH)
359 */
360
361#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
362#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
363
364/* used to re-map FLASH both when starting from SRAM or FLASH:
365 * restrict access enough to keep SRAM working (if any)
366 * but not too much to meddle with FLASH accesses
367 */
368#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
369#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
370
371/*
372 * FLASH timing:
373 */
wdenkf4675562002-10-02 14:20:15 +0000374#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
375 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000376
377#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
378#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
379#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
380
381#define CFG_OR1_REMAP CFG_OR0_REMAP
382#define CFG_OR1_PRELIM CFG_OR0_PRELIM
383#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
384
385/*
386 * BR2/3 and OR2/3 (SDRAM)
387 *
388 */
389#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
390#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
391#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
392
393/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
394#define CFG_OR_TIMING_SDRAM 0x00000A00
395
396#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
397#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
398
399#ifndef CONFIG_CAN_DRIVER
400#define CFG_OR3_PRELIM CFG_OR2_PRELIM
401#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
402#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
403#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
404#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
405#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
406#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
407 BR_PS_8 | BR_MS_UPMB | BR_V )
408#endif /* CONFIG_CAN_DRIVER */
409
410/*
411 * Memory Periodic Timer Prescaler
412 *
413 * The Divider for PTA (refresh timer) configuration is based on an
414 * example SDRAM configuration (64 MBit, one bank). The adjustment to
415 * the number of chip selects (NCS) and the actually needed refresh
416 * rate is done by setting MPTPR.
417 *
418 * PTA is calculated from
419 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
420 *
421 * gclk CPU clock (not bus clock!)
422 * Trefresh Refresh cycle * 4 (four word bursts used)
423 *
424 * 4096 Rows from SDRAM example configuration
425 * 1000 factor s -> ms
426 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
427 * 4 Number of refresh cycles per period
428 * 64 Refresh cycle in ms per number of rows
429 * --------------------------------------------
430 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
431 *
432 * 50 MHz => 50.000.000 / Divider = 98
433 * 66 Mhz => 66.000.000 / Divider = 129
434 * 80 Mhz => 80.000.000 / Divider = 156
435 */
wdenke9132ea2004-04-24 23:23:30 +0000436
437#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
438#define CFG_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000439
440/*
441 * For 16 MBit, refresh rates could be 31.3 us
442 * (= 64 ms / 2K = 125 / quad bursts).
443 * For a simpler initialization, 15.6 us is used instead.
444 *
445 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
446 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
447 */
448#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
449#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
450
451/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
452#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
453#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
454
455/*
456 * MAMR settings for SDRAM
457 */
458
459/* 8 column SDRAM */
460#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
461 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
462 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
463/* 9 column SDRAM */
464#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
465 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
466 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
467
468
469/*
470 * Internal Definitions
471 *
472 * Boot Flags
473 */
474#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
475#define BOOTFLAG_WARM 0x02 /* Software reboot */
476
477#define CONFIG_SCC1_ENET
478#define CONFIG_FEC_ENET
479#define CONFIG_ETHPRIME "SCC ETHERNET"
480
481#endif /* __CONFIG_H */