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Rafal Jaworowski8993e542007-07-27 14:43:59 +02001/*
Wolfgang Denk843efb12009-05-16 10:47:43 +02002 * (C) Copyright 2007-2009 DENX Software Engineering
Rafal Jaworowski8993e542007-07-27 14:43:59 +02003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Rafal Jaworowski8993e542007-07-27 14:43:59 +02005 */
6
7#include <common.h>
Rafal Jaworowski8993e542007-07-27 14:43:59 +02008#include <asm/bitops.h>
9#include <command.h>
Wolfgang Denk843efb12009-05-16 10:47:43 +020010#include <asm/io.h>
John Rigby8a490422008-08-28 13:17:07 -060011#include <asm/processor.h>
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020012#include <asm/mpc512x.h>
Wolfgang Denke343ab82008-01-13 00:55:47 +010013#include <fdt_support.h>
Martha Marxf31c49d2008-05-29 14:23:25 -040014#ifdef CONFIG_MISC_INIT_R
15#include <i2c.h>
16#endif
Martha M Stana5aa3992009-09-21 14:08:00 -040017#include <net.h>
Wolfgang Denk9b55a252008-07-11 01:16:00 +020018
Stefan Roese229549a2009-06-09 16:57:47 +020019#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21
Ralph Kondziella70a4da42009-01-26 12:34:36 -070022DECLARE_GLOBAL_DATA_PTR;
23
Stefan Roese229549a2009-06-09 16:57:47 +020024void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
25
26/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
27extern int mpc5121_nfc_chip;
28
29/* Control chips select signal on MPC5121ADS board */
30void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
31{
32 unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
33 u8 v;
34
35 v = in_8(csreg);
36 v |= 0x0F;
37
38 if (chip >= 0) {
39 __mpc5121_nfc_select_chip(mtd, 0);
40 v &= ~(1 << mpc5121_nfc_chip);
41 } else {
42 __mpc5121_nfc_select_chip(mtd, -1);
43 }
44
45 out_8(csreg, v);
46}
Rafal Jaworowski8993e542007-07-27 14:43:59 +020047
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020048int board_early_init_f(void)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020049{
Rafal Jaworowski8993e542007-07-27 14:43:59 +020050 /*
51 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
52 *
53 * Without this the flash identification routine fails, as it needs to issue
54 * write commands in order to establish the device ID.
55 */
Rafal Jaworowski8993e542007-07-27 14:43:59 +020056
mark.vels@team-embedded.nl812493a2010-10-05 17:46:19 +020057#ifdef CONFIG_MPC5121ADS_REV2
Wolfgang Denk843efb12009-05-16 10:47:43 +020058 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
Martha Marxf31c49d2008-05-29 14:23:25 -040059#else
Wolfgang Denk843efb12009-05-16 10:47:43 +020060 if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
61 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
Martha Marxf31c49d2008-05-29 14:23:25 -040062 } else {
63 /* running from Backup flash */
Wolfgang Denk843efb12009-05-16 10:47:43 +020064 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
Martha Marxf31c49d2008-05-29 14:23:25 -040065 }
66#endif
Rafal Jaworowski8993e542007-07-27 14:43:59 +020067 return 0;
68}
69
Martha M Stana5aa3992009-09-21 14:08:00 -040070int is_micron(void){
71
72 ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
73 uchar macaddr[6];
74 u32 brddate, macchk, ismicron;
75
76 /*
77 * MAC address has serial number with date of manufacture
78 * Boards made before Nov-08 #1180 use Micron memory;
79 * 001e59 is the STx vendor #
80 * Default is Elpida since it works for both but is slightly slower
81 */
82 ismicron = 0;
83 if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
84 brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
85 macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
86 debug("brddate = %d\n\t", brddate);
87
88 if (macchk == 0x001e59 && brddate <= 8111180)
89 ismicron = 1;
90 } else if (brd_rev < 0x400) {
91 ismicron = 1;
92 }
93 debug("Using %s Memory settings\n\t",
94 ismicron ? "Micron" : "Elpida");
95 return(ismicron);
96}
97
Wolfgang Denk7629f1c2009-06-14 20:58:47 +020098phys_size_t initdram(int board_type)
Rafal Jaworowski8993e542007-07-27 14:43:59 +020099{
100 u32 msize = 0;
Martha M Stana5aa3992009-09-21 14:08:00 -0400101 /*
102 * Elpida MDDRC and initialization settings are an alternative
103 * to the Default Micron ones for all but the earliest Rev 4 boards
104 */
Wolfgang Denkda01f532009-10-04 22:56:08 +0200105 ddr512x_config_t elpida_mddrc_config = {
106 .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
107 .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
108 .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
109 .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
Martha M Stana5aa3992009-09-21 14:08:00 -0400110 };
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200111
Martha M Stana5aa3992009-09-21 14:08:00 -0400112 u32 elpida_init_sequence[] = {
113 CONFIG_SYS_DDRCMD_NOP,
114 CONFIG_SYS_DDRCMD_NOP,
115 CONFIG_SYS_DDRCMD_NOP,
116 CONFIG_SYS_DDRCMD_NOP,
117 CONFIG_SYS_DDRCMD_NOP,
118 CONFIG_SYS_DDRCMD_NOP,
119 CONFIG_SYS_DDRCMD_NOP,
120 CONFIG_SYS_DDRCMD_NOP,
121 CONFIG_SYS_DDRCMD_NOP,
122 CONFIG_SYS_DDRCMD_NOP,
123 CONFIG_SYS_DDRCMD_PCHG_ALL,
124 CONFIG_SYS_DDRCMD_NOP,
125 CONFIG_SYS_DDRCMD_RFSH,
126 CONFIG_SYS_DDRCMD_NOP,
127 CONFIG_SYS_DDRCMD_RFSH,
128 CONFIG_SYS_DDRCMD_NOP,
129 CONFIG_SYS_DDRCMD_EM2,
130 CONFIG_SYS_DDRCMD_EM3,
131 CONFIG_SYS_DDRCMD_EN_DLL,
132 CONFIG_SYS_ELPIDA_RES_DLL,
133 CONFIG_SYS_DDRCMD_PCHG_ALL,
134 CONFIG_SYS_DDRCMD_RFSH,
135 CONFIG_SYS_DDRCMD_RFSH,
136 CONFIG_SYS_DDRCMD_RFSH,
137 CONFIG_SYS_ELPIDA_INIT_DEV_OP,
138 CONFIG_SYS_DDRCMD_NOP,
139 CONFIG_SYS_DDRCMD_NOP,
140 CONFIG_SYS_DDRCMD_NOP,
141 CONFIG_SYS_DDRCMD_NOP,
142 CONFIG_SYS_DDRCMD_NOP,
143 CONFIG_SYS_DDRCMD_NOP,
144 CONFIG_SYS_DDRCMD_NOP,
145 CONFIG_SYS_DDRCMD_NOP,
146 CONFIG_SYS_DDRCMD_NOP,
147 CONFIG_SYS_DDRCMD_NOP,
148 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
149 CONFIG_SYS_ELPIDA_OCD_EXIT,
150 CONFIG_SYS_DDRCMD_NOP,
151 CONFIG_SYS_DDRCMD_NOP,
152 CONFIG_SYS_DDRCMD_NOP,
153 CONFIG_SYS_DDRCMD_NOP,
154 CONFIG_SYS_DDRCMD_NOP,
155 CONFIG_SYS_DDRCMD_NOP,
156 CONFIG_SYS_DDRCMD_NOP,
157 CONFIG_SYS_DDRCMD_NOP,
158 CONFIG_SYS_DDRCMD_NOP,
159 CONFIG_SYS_DDRCMD_NOP
160 };
161
162 if (is_micron()) {
163 msize = fixed_sdram(NULL, NULL, 0);
164 } else {
Wolfgang Denkda01f532009-10-04 22:56:08 +0200165 msize = fixed_sdram(&elpida_mddrc_config,
Martha M Stana5aa3992009-09-21 14:08:00 -0400166 elpida_init_sequence,
167 sizeof(elpida_init_sequence)/sizeof(u32));
168 }
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200169
170 return msize;
171}
172
York Sun0e1bad42008-05-05 10:20:01 -0500173int misc_init_r(void)
174{
175 u8 tmp_val;
176
177 /* Using this for DIU init before the driver in linux takes over
178 * Enable the TFP410 Encoder (I2C address 0x38)
179 */
180
181 i2c_set_bus_num(2);
182 tmp_val = 0xBF;
183 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
184 /* Verify if enabled */
185 tmp_val = 0;
186 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
Marek Vasutdffe06f2011-10-21 14:17:03 +0000187 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
York Sun0e1bad42008-05-05 10:20:01 -0500188
189 tmp_val = 0x10;
190 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
191 /* Verify if enabled */
192 tmp_val = 0;
193 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
Marek Vasutdffe06f2011-10-21 14:17:03 +0000194 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
York Sun0e1bad42008-05-05 10:20:01 -0500195
York Sun0e1bad42008-05-05 10:20:01 -0500196 return 0;
197}
Wolfgang Denk72601d02009-05-16 10:47:41 +0200198
Kenneth Johansson66894842008-07-15 12:13:38 +0200199static iopin_t ioregs_init[] = {
200 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
201 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200202 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200203 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
204 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
205 },
206 /* Set highest Slew on 9 PATA pins */
207 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200208 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
Kenneth Johansson66894842008-07-15 12:13:38 +0200209 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
210 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
211 },
212 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
213 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200214 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200215 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
216 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
217 },
218 /* FUNC1=SPDIF_TXCLK */
219 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200220 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200221 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
222 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
223 },
224 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
225 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200226 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200227 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
228 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
229 },
230 /* FUNC2=DIU CLK */
231 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200232 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200233 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
234 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
235 },
236 /* FUNC2=DIU_HSYNC */
237 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200238 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200239 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
240 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
241 },
242 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
243 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200244 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
Kenneth Johansson66894842008-07-15 12:13:38 +0200245 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
246 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
247 }
248};
York Sun0e1bad42008-05-05 10:20:01 -0500249
John Rigby14d19cd2009-01-23 10:33:15 -0700250static iopin_t rev2_silicon_pci_ioregs_init[] = {
251 /* FUNC0=PCI Sets next 54 to PCI pads */
252 {
Wolfgang Denk843efb12009-05-16 10:47:43 +0200253 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
John Rigby14d19cd2009-01-23 10:33:15 -0700254 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
255 }
256};
257
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200258int checkboard (void)
259{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260 ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
261 uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
John Rigby14d19cd2009-01-23 10:33:15 -0700262 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk843efb12009-05-16 10:47:43 +0200263 u32 spridr = in_be32(&im->sysconf.spridr);
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200264
mark.vels@team-embedded.nl812493a2010-10-05 17:46:19 +0200265 printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
Wolfgang Denkb1b54e32007-08-02 21:27:46 +0200266 brd_rev, cpld_rev);
Kenneth Johansson66894842008-07-15 12:13:38 +0200267
Wolfgang Denk72601d02009-05-16 10:47:41 +0200268 /* initialize function mux & slew rate IO inter alia on IO Pins */
269 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
270
Wolfgang Denk843efb12009-05-16 10:47:43 +0200271 if (SVR_MJREV (spridr) >= 2)
John Rigby14d19cd2009-01-23 10:33:15 -0700272 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
John Rigby51b67d02007-08-24 18:18:43 -0600273
Rafal Jaworowski8993e542007-07-27 14:43:59 +0200274 return 0;
275}
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100276
277#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
278void ft_board_setup(void *blob, bd_t *bd)
279{
280 ft_cpu_setup(blob, bd);
Grzegorz Bernacki281ff9a2008-01-08 17:16:15 +0100281}
282#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */