blob: cbce43dbe3f9c286055b35dd10f6dbffb8bdc4c0 [file] [log] [blame]
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
Tom Rinifa09b122021-09-10 17:37:43 -04008#include <dt-bindings/mux/ti-serdes.h>
9#include <dt-bindings/phy/phy.h>
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +053010#include <dt-bindings/gpio/gpio.h>
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +053011#include <dt-bindings/net/ti-dp83867.h>
Roger Quadrosffefc722023-01-24 11:43:25 +020012#include <dt-bindings/leds/common.h>
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +053013#include "k3-am642.dtsi"
14
15/ {
Roger Quadrosffefc722023-01-24 11:43:25 +020016 compatible = "ti,am642-sk", "ti,am642";
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +053017 model = "Texas Instruments AM642 SK";
18
19 chosen {
Roger Quadros01f573e2023-08-05 11:14:40 +030020 stdout-path = &main_uart0;
21 };
22
23 aliases {
24 serial0 = &mcu_uart0;
25 serial1 = &main_uart1;
26 serial2 = &main_uart0;
27 i2c0 = &main_i2c0;
28 i2c1 = &main_i2c1;
29 mmc0 = &sdhci0;
30 mmc1 = &sdhci1;
31 ethernet0 = &cpsw_port1;
32 ethernet1 = &cpsw_port2;
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +053033 };
34
35 memory@80000000 {
36 device_type = "memory";
37 /* 2G RAM */
38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +053039 };
40
41 reserved-memory {
42 #address-cells = <2>;
43 #size-cells = <2>;
44 ranges;
45
46 secure_ddr: optee@9e800000 {
47 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
48 alignment = <0x1000>;
49 no-map;
50 };
Tom Rinifa09b122021-09-10 17:37:43 -040051
52 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
53 compatible = "shared-dma-pool";
54 reg = <0x00 0xa0000000 0x00 0x100000>;
55 no-map;
56 };
57
58 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
59 compatible = "shared-dma-pool";
60 reg = <0x00 0xa0100000 0x00 0xf00000>;
61 no-map;
62 };
63
64 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
65 compatible = "shared-dma-pool";
66 reg = <0x00 0xa1000000 0x00 0x100000>;
67 no-map;
68 };
69
70 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
71 compatible = "shared-dma-pool";
72 reg = <0x00 0xa1100000 0x00 0xf00000>;
73 no-map;
74 };
75
76 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
77 compatible = "shared-dma-pool";
78 reg = <0x00 0xa2000000 0x00 0x100000>;
79 no-map;
80 };
81
82 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
83 compatible = "shared-dma-pool";
84 reg = <0x00 0xa2100000 0x00 0xf00000>;
85 no-map;
86 };
87
88 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
89 compatible = "shared-dma-pool";
90 reg = <0x00 0xa3000000 0x00 0x100000>;
91 no-map;
92 };
93
94 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
95 compatible = "shared-dma-pool";
96 reg = <0x00 0xa3100000 0x00 0xf00000>;
97 no-map;
98 };
99
100 rtos_ipc_memory_region: ipc-memories@a5000000 {
101 reg = <0x00 0xa5000000 0x00 0x00800000>;
102 alignment = <0x1000>;
103 no-map;
104 };
105 };
106
Roger Quadros01f573e2023-08-05 11:14:40 +0300107 vusb_main: regulator-0 {
Tom Rinifa09b122021-09-10 17:37:43 -0400108 /* USB MAIN INPUT 5V DC */
109 compatible = "regulator-fixed";
110 regulator-name = "vusb_main5v0";
111 regulator-min-microvolt = <5000000>;
112 regulator-max-microvolt = <5000000>;
113 regulator-always-on;
114 regulator-boot-on;
115 };
116
Roger Quadros01f573e2023-08-05 11:14:40 +0300117 vcc_3v3_sys: regulator-1 {
Tom Rinifa09b122021-09-10 17:37:43 -0400118 /* output of LP8733xx */
119 compatible = "regulator-fixed";
120 regulator-name = "vcc_3v3_sys";
121 regulator-min-microvolt = <3300000>;
122 regulator-max-microvolt = <3300000>;
123 vin-supply = <&vusb_main>;
124 regulator-always-on;
125 regulator-boot-on;
126 };
127
Roger Quadros01f573e2023-08-05 11:14:40 +0300128 vdd_mmc1: regulator-2 {
Tom Rinifa09b122021-09-10 17:37:43 -0400129 /* TPS2051BD */
130 compatible = "regulator-fixed";
131 regulator-name = "vdd_mmc1";
132 regulator-min-microvolt = <3300000>;
133 regulator-max-microvolt = <3300000>;
134 regulator-boot-on;
135 enable-active-high;
136 vin-supply = <&vcc_3v3_sys>;
137 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530138 };
Roger Quadrosffefc722023-01-24 11:43:25 +0200139
Roger Quadros01f573e2023-08-05 11:14:40 +0300140 com8_ls_en: regulator-3 {
Roger Quadrosffefc722023-01-24 11:43:25 +0200141 compatible = "regulator-fixed";
142 regulator-name = "com8_ls_en";
143 regulator-min-microvolt = <3300000>;
144 regulator-max-microvolt = <3300000>;
145 regulator-always-on;
146 regulator-boot-on;
147 pinctrl-0 = <&main_com8_ls_en_pins_default>;
148 pinctrl-names = "default";
149 gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
150 };
151
Roger Quadros01f573e2023-08-05 11:14:40 +0300152 wlan_en: regulator-4 {
Roger Quadrosffefc722023-01-24 11:43:25 +0200153 /* output of SN74AVC4T245RSVR */
154 compatible = "regulator-fixed";
155 regulator-name = "wlan_en";
156 regulator-min-microvolt = <1800000>;
157 regulator-max-microvolt = <1800000>;
158 enable-active-high;
159 pinctrl-0 = <&main_wlan_en_pins_default>;
160 pinctrl-names = "default";
161 vin-supply = <&com8_ls_en>;
162 gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
163 };
164
165 led-controller {
166 compatible = "gpio-leds";
167
168 led-0 {
169 color = <LED_COLOR_ID_GREEN>;
170 function = LED_FUNCTION_INDICATOR;
171 function-enumerator = <1>;
172 gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
173 default-state = "off";
174 };
175
176 led-1 {
177 color = <LED_COLOR_ID_RED>;
178 function = LED_FUNCTION_INDICATOR;
179 function-enumerator = <2>;
180 gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
181 default-state = "off";
182 };
183
184 led-2 {
185 color = <LED_COLOR_ID_GREEN>;
186 function = LED_FUNCTION_INDICATOR;
187 function-enumerator = <3>;
188 gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
189 default-state = "off";
190 };
191
192 led-3 {
193 color = <LED_COLOR_ID_AMBER>;
194 function = LED_FUNCTION_INDICATOR;
195 function-enumerator = <4>;
196 gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
197 default-state = "off";
198 };
199
200 led-4 {
201 color = <LED_COLOR_ID_GREEN>;
202 function = LED_FUNCTION_INDICATOR;
203 function-enumerator = <5>;
204 gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
205 default-state = "off";
206 };
207
208 led-5 {
209 color = <LED_COLOR_ID_RED>;
210 function = LED_FUNCTION_INDICATOR;
211 function-enumerator = <6>;
212 gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
213 default-state = "off";
214 };
215
216 led-6 {
217 color = <LED_COLOR_ID_GREEN>;
218 function = LED_FUNCTION_INDICATOR;
219 function-enumerator = <7>;
220 gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
221 default-state = "off";
222 };
223
224 led-7 {
225 color = <LED_COLOR_ID_AMBER>;
226 function = LED_FUNCTION_HEARTBEAT;
227 function-enumerator = <8>;
228 linux,default-trigger = "heartbeat";
229 gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
230 };
231 };
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530232};
233
234&main_pmx0 {
Roger Quadros01f573e2023-08-05 11:14:40 +0300235 main_mmc1_pins_default: main-mmc1-default-pins {
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530236 pinctrl-single,pins = <
Roger Quadros01f573e2023-08-05 11:14:40 +0300237 AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
238 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
239 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530240 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
Roger Quadros01f573e2023-08-05 11:14:40 +0300241 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
242 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
243 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
244 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
245 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530246 >;
247 };
248
Roger Quadros01f573e2023-08-05 11:14:40 +0300249 main_uart0_pins_default: main-uart0-default-pins {
Roger Quadrosffefc722023-01-24 11:43:25 +0200250 pinctrl-single,pins = <
251 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
252 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
253 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
254 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
255 >;
256 };
257
Roger Quadros01f573e2023-08-05 11:14:40 +0300258 main_uart1_pins_default: main-uart1-default-pins {
259 pinctrl-single,pins = <
260 AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
261 AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
262 AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
263 AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
264 >;
265 };
266
267 main_usb0_pins_default: main-usb0-default-pins {
Tom Rinifa09b122021-09-10 17:37:43 -0400268 pinctrl-single,pins = <
269 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
270 >;
271 };
272
Roger Quadros01f573e2023-08-05 11:14:40 +0300273 main_i2c0_pins_default: main-i2c0-default-pins {
274 pinctrl-single,pins = <
275 AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
276 AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
277 >;
278 };
279
280 main_i2c1_pins_default: main-i2c1-default-pins {
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530281 pinctrl-single,pins = <
282 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
283 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
284 >;
285 };
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530286
Roger Quadros01f573e2023-08-05 11:14:40 +0300287 mdio1_pins_default: mdio1-default-pins {
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530288 pinctrl-single,pins = <
289 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
290 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
291 >;
292 };
293
Roger Quadros01f573e2023-08-05 11:14:40 +0300294 rgmii1_pins_default: rgmii1-default-pins {
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530295 pinctrl-single,pins = <
296 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
297 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
298 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
299 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
300 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
301 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
302 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
303 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
304 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
305 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
306 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
307 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
308 >;
309 };
310
Roger Quadros01f573e2023-08-05 11:14:40 +0300311 rgmii2_pins_default: rgmii2-default-pins {
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530312 pinctrl-single,pins = <
313 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
314 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
315 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
316 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
317 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
318 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
319 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
320 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
321 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
322 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
323 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
324 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
325 >;
326 };
Tom Rinifa09b122021-09-10 17:37:43 -0400327
Roger Quadros01f573e2023-08-05 11:14:40 +0300328 ospi0_pins_default: ospi0-default-pins {
Tom Rinifa09b122021-09-10 17:37:43 -0400329 pinctrl-single,pins = <
330 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
331 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
332 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
333 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
334 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
335 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
336 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
337 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
338 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
339 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
340 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
341 >;
342 };
Roger Quadrosffefc722023-01-24 11:43:25 +0200343
Roger Quadros01f573e2023-08-05 11:14:40 +0300344 main_ecap0_pins_default: main-ecap0-default-pins {
Roger Quadrosffefc722023-01-24 11:43:25 +0200345 pinctrl-single,pins = <
346 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
347 >;
348 };
Roger Quadros01f573e2023-08-05 11:14:40 +0300349 main_wlan_en_pins_default: main-wlan-en-default-pins {
Roger Quadrosffefc722023-01-24 11:43:25 +0200350 pinctrl-single,pins = <
351 AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
352 >;
353 };
354
Roger Quadros01f573e2023-08-05 11:14:40 +0300355 main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
Roger Quadrosffefc722023-01-24 11:43:25 +0200356 pinctrl-single,pins = <
357 AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
358 >;
359 };
360
Roger Quadros01f573e2023-08-05 11:14:40 +0300361 main_wlan_pins_default: main-wlan-default-pins {
Roger Quadrosffefc722023-01-24 11:43:25 +0200362 pinctrl-single,pins = <
363 AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
364 >;
365 };
Tom Rinifa09b122021-09-10 17:37:43 -0400366};
367
Roger Quadrosffefc722023-01-24 11:43:25 +0200368&main_uart0 {
369 status = "okay";
370 pinctrl-names = "default";
371 pinctrl-0 = <&main_uart0_pins_default>;
Roger Quadros01f573e2023-08-05 11:14:40 +0300372 current-speed = <115200>;
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530373};
374
375&main_uart1 {
376 /* main_uart1 is reserved for firmware usage */
377 status = "reserved";
Roger Quadros01f573e2023-08-05 11:14:40 +0300378 pinctrl-names = "default";
379 pinctrl-0 = <&main_uart1_pins_default>;
380};
381
382&main_i2c0 {
383 status = "okay";
384 pinctrl-names = "default";
385 pinctrl-0 = <&main_i2c0_pins_default>;
386 clock-frequency = <400000>;
387
388 eeprom@51 {
389 compatible = "atmel,24c512";
390 reg = <0x51>;
391 };
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530392};
393
Tom Rinifa09b122021-09-10 17:37:43 -0400394&main_i2c1 {
Roger Quadrosffefc722023-01-24 11:43:25 +0200395 status = "okay";
Tom Rinifa09b122021-09-10 17:37:43 -0400396 pinctrl-names = "default";
397 pinctrl-0 = <&main_i2c1_pins_default>;
398 clock-frequency = <400000>;
399
400 exp1: gpio@70 {
401 compatible = "nxp,pca9538";
402 reg = <0x70>;
403 gpio-controller;
404 #gpio-cells = <2>;
405 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
406 "PRU_DETECT", "MMC1_SD_EN",
407 "VPP_LDO_EN", "RPI_PS_3V3_En",
408 "RPI_PS_5V0_En", "RPI_HAT_DETECT";
409 };
Tom Rinifa09b122021-09-10 17:37:43 -0400410
Roger Quadrosffefc722023-01-24 11:43:25 +0200411 exp2: gpio@60 {
412 compatible = "ti,tpic2810";
413 reg = <0x60>;
414 gpio-controller;
415 #gpio-cells = <2>;
416 gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
417 };
Tom Rinifa09b122021-09-10 17:37:43 -0400418};
419
420/* mcu_gpio0 is reserved for mcu firmware usage */
421&mcu_gpio0 {
422 status = "reserved";
423};
424
Roger Quadrosffefc722023-01-24 11:43:25 +0200425&sdhci0 {
426 vmmc-supply = <&wlan_en>;
427 bus-width = <4>;
428 non-removable;
429 cap-power-off-card;
430 keep-power-in-suspend;
431 ti,driver-strength-ohm = <50>;
432
433 #address-cells = <1>;
434 #size-cells = <0>;
435 wlcore: wlcore@2 {
436 compatible = "ti,wl1837";
437 reg = <2>;
438 pinctrl-0 = <&main_wlan_pins_default>;
439 pinctrl-names = "default";
440 interrupt-parent = <&main_gpio0>;
441 interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
442 };
443};
444
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530445&sdhci1 {
446 /* SD/MMC */
Tom Rinifa09b122021-09-10 17:37:43 -0400447 vmmc-supply = <&vdd_mmc1>;
Lokesh Vutlac88a9ae2021-05-06 16:44:59 +0530448 pinctrl-names = "default";
449 bus-width = <4>;
450 pinctrl-0 = <&main_mmc1_pins_default>;
451 ti,driver-strength-ohm = <50>;
452 disable-wp;
453};
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530454
Tom Rinifa09b122021-09-10 17:37:43 -0400455&serdes_ln_ctrl {
456 idle-states = <AM64_SERDES0_LANE0_USB>;
457};
458
459&serdes0 {
460 serdes0_usb_link: phy@0 {
461 reg = <0>;
462 cdns,num-lanes = <1>;
463 #phy-cells = <0>;
464 cdns,phy-type = <PHY_TYPE_USB3>;
465 resets = <&serdes_wiz0 1>;
466 };
467};
468
469&usbss0 {
470 ti,vbus-divider;
471};
472
473&usb0 {
474 dr_mode = "host";
475 maximum-speed = "super-speed";
476 pinctrl-names = "default";
477 pinctrl-0 = <&main_usb0_pins_default>;
478 phys = <&serdes0_usb_link>;
479 phy-names = "cdns3,usb3-phy";
480};
481
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530482&cpsw3g {
483 pinctrl-names = "default";
Roger Quadros01f573e2023-08-05 11:14:40 +0300484 pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530485};
486
487&cpsw_port1 {
488 phy-mode = "rgmii-rxid";
489 phy-handle = <&cpsw3g_phy0>;
490};
491
Tom Rinifa09b122021-09-10 17:37:43 -0400492&cpsw_port2 {
493 phy-mode = "rgmii-rxid";
494 phy-handle = <&cpsw3g_phy1>;
495};
496
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530497&cpsw3g_mdio {
Roger Quadrosffefc722023-01-24 11:43:25 +0200498 status = "okay";
499 pinctrl-names = "default";
500 pinctrl-0 = <&mdio1_pins_default>;
501
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530502 cpsw3g_phy0: ethernet-phy@0 {
503 reg = <0>;
504 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
505 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
506 };
Tom Rinifa09b122021-09-10 17:37:43 -0400507
508 cpsw3g_phy1: ethernet-phy@1 {
509 reg = <1>;
510 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
511 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
512 };
513};
514
515&tscadc0 {
516 status = "disabled";
517};
518
519&ospi0 {
520 pinctrl-names = "default";
521 pinctrl-0 = <&ospi0_pins_default>;
522
Roger Quadrosffefc722023-01-24 11:43:25 +0200523 flash@0 {
Tom Rinifa09b122021-09-10 17:37:43 -0400524 compatible = "jedec,spi-nor";
525 reg = <0x0>;
526 spi-tx-bus-width = <8>;
527 spi-rx-bus-width = <8>;
528 spi-max-frequency = <25000000>;
529 cdns,tshsl-ns = <60>;
530 cdns,tsd2d-ns = <60>;
531 cdns,tchsh-ns = <60>;
532 cdns,tslch-ns = <60>;
533 cdns,read-delay = <4>;
Roger Quadros01f573e2023-08-05 11:14:40 +0300534
535 partitions {
536 compatible = "fixed-partitions";
537 #address-cells = <1>;
538 #size-cells = <1>;
539
540 partition@0 {
541 label = "ospi.tiboot3";
542 reg = <0x0 0x100000>;
543 };
544
545 partition@100000 {
546 label = "ospi.tispl";
547 reg = <0x100000 0x200000>;
548 };
549
550 partition@300000 {
551 label = "ospi.u-boot";
552 reg = <0x300000 0x400000>;
553 };
554
555 partition@700000 {
556 label = "ospi.env";
557 reg = <0x700000 0x40000>;
558 };
559
560 partition@740000 {
561 label = "ospi.env.backup";
562 reg = <0x740000 0x40000>;
563 };
564
565 partition@800000 {
566 label = "ospi.rootfs";
567 reg = <0x800000 0x37c0000>;
568 };
569
570 partition@3fc0000 {
571 label = "ospi.phypattern";
572 reg = <0x3fc0000 0x40000>;
573 };
574 };
Tom Rinifa09b122021-09-10 17:37:43 -0400575 };
576};
577
578&mailbox0_cluster2 {
Roger Quadros01f573e2023-08-05 11:14:40 +0300579 status = "okay";
580
Tom Rinifa09b122021-09-10 17:37:43 -0400581 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
582 ti,mbox-rx = <0 0 2>;
583 ti,mbox-tx = <1 0 2>;
584 };
585
586 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
587 ti,mbox-rx = <2 0 2>;
588 ti,mbox-tx = <3 0 2>;
589 };
590};
591
Tom Rinifa09b122021-09-10 17:37:43 -0400592&mailbox0_cluster4 {
Roger Quadros01f573e2023-08-05 11:14:40 +0300593 status = "okay";
594
Tom Rinifa09b122021-09-10 17:37:43 -0400595 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
596 ti,mbox-rx = <0 0 2>;
597 ti,mbox-tx = <1 0 2>;
598 };
599
600 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
601 ti,mbox-rx = <2 0 2>;
602 ti,mbox-tx = <3 0 2>;
603 };
604};
605
Tom Rinifa09b122021-09-10 17:37:43 -0400606&mailbox0_cluster6 {
Roger Quadros01f573e2023-08-05 11:14:40 +0300607 status = "okay";
608
Tom Rinifa09b122021-09-10 17:37:43 -0400609 mbox_m4_0: mbox-m4-0 {
610 ti,mbox-rx = <0 0 2>;
611 ti,mbox-tx = <1 0 2>;
612 };
613};
614
Tom Rinifa09b122021-09-10 17:37:43 -0400615&main_r5fss0_core0 {
Roger Quadros01f573e2023-08-05 11:14:40 +0300616 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
Tom Rinifa09b122021-09-10 17:37:43 -0400617 memory-region = <&main_r5fss0_core0_dma_memory_region>,
618 <&main_r5fss0_core0_memory_region>;
619};
620
621&main_r5fss0_core1 {
Roger Quadros01f573e2023-08-05 11:14:40 +0300622 mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
Tom Rinifa09b122021-09-10 17:37:43 -0400623 memory-region = <&main_r5fss0_core1_dma_memory_region>,
624 <&main_r5fss0_core1_memory_region>;
625};
626
627&main_r5fss1_core0 {
Roger Quadros01f573e2023-08-05 11:14:40 +0300628 mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
Tom Rinifa09b122021-09-10 17:37:43 -0400629 memory-region = <&main_r5fss1_core0_dma_memory_region>,
630 <&main_r5fss1_core0_memory_region>;
631};
632
633&main_r5fss1_core1 {
Roger Quadros01f573e2023-08-05 11:14:40 +0300634 mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
Tom Rinifa09b122021-09-10 17:37:43 -0400635 memory-region = <&main_r5fss1_core1_dma_memory_region>,
636 <&main_r5fss1_core1_memory_region>;
637};
638
Roger Quadrosffefc722023-01-24 11:43:25 +0200639&ecap0 {
640 status = "okay";
641 /* PWM is available on Pin 1 of header J3 */
642 pinctrl-names = "default";
643 pinctrl-0 = <&main_ecap0_pins_default>;
Vignesh Raghavendrabbc9da52021-05-10 20:06:13 +0530644};