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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala129ba612008-08-12 11:13:08 -05002/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06003 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
Kumar Gala129ba612008-08-12 11:13:08 -05004 */
5
6/*
7 * mpc8572ds board configuration file
8 *
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Kumar Gala509c4c42010-05-21 04:05:14 -050013#include "../board/freescale/common/ics307_clk.h"
14
Kumar Gala7a577fd2011-01-12 02:48:53 -060015#ifndef CONFIG_RESET_VECTOR_ADDRESS
16#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
17#endif
18
Kumar Galacb14e932010-11-12 08:22:01 -060019#ifndef CONFIG_SYS_MONITOR_BASE
20#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
21#endif
22
Kumar Gala129ba612008-08-12 11:13:08 -050023/* High Level Configuration Options */
Kumar Gala129ba612008-08-12 11:13:08 -050024
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040025#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
26#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
27#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
Kumar Gala129ba612008-08-12 11:13:08 -050028#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000029#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala0151cba2008-10-21 11:33:58 -050030#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala129ba612008-08-12 11:13:08 -050031
Kumar Gala129ba612008-08-12 11:13:08 -050032#define CONFIG_ENV_OVERWRITE
33
Kumar Gala509c4c42010-05-21 04:05:14 -050034#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
35#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
Haiying Wang4ca06602008-10-03 12:37:41 -040036#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala129ba612008-08-12 11:13:08 -050037
38/*
39 * These can be toggled for performance analysis, otherwise use default.
40 */
41#define CONFIG_L2_CACHE /* toggle L2 cache */
42#define CONFIG_BTB /* toggle branch predition */
Kumar Gala129ba612008-08-12 11:13:08 -050043
44#define CONFIG_ENABLE_36BIT_PHYS 1
45
Kumar Gala18af1c52009-01-23 14:22:14 -060046#ifdef CONFIG_PHYS_64BIT
47#define CONFIG_ADDR_MAP 1
48#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
49#endif
50
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
52#define CONFIG_SYS_MEMTEST_END 0x7fffffff
Kumar Gala129ba612008-08-12 11:13:08 -050053
54/*
Kumar Galacb14e932010-11-12 08:22:01 -060055 * Config the L2 Cache as L2 SRAM
56 */
57#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
58#ifdef CONFIG_PHYS_64BIT
59#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
60#else
61#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
62#endif
63#define CONFIG_SYS_L2_SIZE (512 << 10)
64#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
65
Timur Tabie46fedf2011-08-04 18:03:41 -050066#define CONFIG_SYS_CCSRBAR 0xffe00000
67#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala129ba612008-08-12 11:13:08 -050068
Kumar Gala8d22ddc2011-11-09 09:10:49 -060069#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -050070#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Kumar Galacb14e932010-11-12 08:22:01 -060071#endif
72
Kumar Gala129ba612008-08-12 11:13:08 -050073/* DDR Setup */
Kumar Galaf8523cb2009-02-06 09:56:35 -060074#define CONFIG_VERY_BIG_RAM
Kumar Gala129ba612008-08-12 11:13:08 -050075#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
76#define CONFIG_DDR_SPD
Kumar Gala129ba612008-08-12 11:13:08 -050077
York Sund34897d2011-01-25 21:51:29 -080078#define CONFIG_DDR_ECC
Dave Liu9b0ad1b2008-10-28 17:53:38 +080079#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
Kumar Gala129ba612008-08-12 11:13:08 -050080#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
81
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
83#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala129ba612008-08-12 11:13:08 -050084
Kumar Gala129ba612008-08-12 11:13:08 -050085#define CONFIG_DIMM_SLOTS_PER_CTLR 1
86#define CONFIG_CHIP_SELECTS_PER_CTRL 2
87
88/* I2C addresses of SPD EEPROMs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */
Kumar Gala129ba612008-08-12 11:13:08 -050090#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
91#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
92
93/* These are used when DDR doesn't use SPD. */
Dave Liudc889e82008-11-28 20:16:58 +080094#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
95#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
96#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
97#define CONFIG_SYS_DDR_TIMING_3 0x00020000
98#define CONFIG_SYS_DDR_TIMING_0 0x00260802
99#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
100#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
101#define CONFIG_SYS_DDR_MODE_1 0x00440462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_DDR_MODE_2 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800103#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
Dave Liudc889e82008-11-28 20:16:58 +0800105#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
106#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Dave Liudc889e82008-11-28 20:16:58 +0800108#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
109#define CONFIG_SYS_DDR_CONTROL2 0x24400000
Kumar Gala129ba612008-08-12 11:13:08 -0500110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
112#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
113#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala129ba612008-08-12 11:13:08 -0500114
115/*
Kumar Gala129ba612008-08-12 11:13:08 -0500116 * Make sure required options are set
117 */
118#ifndef CONFIG_SPD_EEPROM
119#error ("CONFIG_SPD_EEPROM is required")
120#endif
121
122#undef CONFIG_CLOCKS_IN_MHZ
123
124/*
125 * Memory map
126 *
127 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
128 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
129 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
130 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
131 *
132 * Localbus cacheable (TBD)
133 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
134 *
135 * Localbus non-cacheable
136 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
137 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100138 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala129ba612008-08-12 11:13:08 -0500139 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
140 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
141 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
142 */
143
144/*
145 * Local Bus Definitions
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala18af1c52009-01-23 14:22:14 -0600148#ifdef CONFIG_PHYS_64BIT
149#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
150#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600151#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600152#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500153
Kumar Galacb14e932010-11-12 08:22:01 -0600154#define CONFIG_FLASH_BR_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000155 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Kumar Galacb14e932010-11-12 08:22:01 -0600156#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500157
Kumar Galac953ddf2008-12-02 14:19:34 -0600158#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
159#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala129ba612008-08-12 11:13:08 -0500160
Kumar Gala18af1c52009-01-23 14:22:14 -0600161#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala129ba612008-08-12 11:13:08 -0500163#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
166#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
167#undef CONFIG_SYS_FLASH_CHECKSUM
168#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
169#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala129ba612008-08-12 11:13:08 -0500170
Kumar Galacb14e932010-11-12 08:22:01 -0600171#undef CONFIG_SYS_RAMBOOT
Kumar Gala129ba612008-08-12 11:13:08 -0500172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_EMPTY_INFO
174#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala129ba612008-08-12 11:13:08 -0500175
Kumar Gala558710b2010-11-19 08:53:25 -0600176#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala129ba612008-08-12 11:13:08 -0500177#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
178#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala18af1c52009-01-23 14:22:14 -0600179#ifdef CONFIG_PHYS_64BIT
180#define PIXIS_BASE_PHYS 0xfffdf0000ull
181#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600182#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600183#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500184
Kumar Gala52b565f2008-12-02 14:19:33 -0600185#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala129ba612008-08-12 11:13:08 -0500187
188#define PIXIS_ID 0x0 /* Board ID at offset 0 */
189#define PIXIS_VER 0x1 /* Board version at offset 1 */
190#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
191#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
192#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
193#define PIXIS_PWR 0x5 /* PIXIS Power status register */
194#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
195#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
196#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
197#define PIXIS_VCTL 0x10 /* VELA Control Register */
198#define PIXIS_VSTAT 0x11 /* VELA Status Register */
199#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
200#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
201#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
202#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500203#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
204#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
205#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
206#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
207#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
Kumar Gala129ba612008-08-12 11:13:08 -0500208#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
209#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
210#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
211#define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */
212#define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */
213#define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */
214#define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */
215#define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */
216#define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */
217#define PIXIS_VWATCH 0x24 /* Watchdog Register */
218#define PIXIS_LED 0x25 /* LED Register */
219
Kumar Galacb14e932010-11-12 08:22:01 -0600220#define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */
221
Kumar Gala129ba612008-08-12 11:13:08 -0500222/* old pixis referenced names */
223#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
224#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0
Liu Yu7e183ca2008-10-10 11:40:59 +0800226#define PIXIS_VSPEED2_TSEC1SER 0x8
227#define PIXIS_VSPEED2_TSEC2SER 0x4
228#define PIXIS_VSPEED2_TSEC3SER 0x2
229#define PIXIS_VSPEED2_TSEC4SER 0x1
230#define PIXIS_VCFGEN1_TSEC1SER 0x20
231#define PIXIS_VCFGEN1_TSEC2SER 0x20
232#define PIXIS_VCFGEN1_TSEC3SER 0x20
233#define PIXIS_VCFGEN1_TSEC4SER 0x20
234#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \
235 | PIXIS_VSPEED2_TSEC2SER \
236 | PIXIS_VSPEED2_TSEC3SER \
237 | PIXIS_VSPEED2_TSEC4SER)
238#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \
239 | PIXIS_VCFGEN1_TSEC2SER \
240 | PIXIS_VCFGEN1_TSEC3SER \
241 | PIXIS_VCFGEN1_TSEC4SER)
Kumar Gala129ba612008-08-12 11:13:08 -0500242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_INIT_RAM_LOCK 1
244#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200245#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala129ba612008-08-12 11:13:08 -0500246
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200247#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
251#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala129ba612008-08-12 11:13:08 -0500252
Kumar Galacb14e932010-11-12 08:22:01 -0600253#ifndef CONFIG_NAND_SPL
Haiying Wangc013b742008-10-29 13:32:59 -0400254#define CONFIG_SYS_NAND_BASE 0xffa00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600255#ifdef CONFIG_PHYS_64BIT
256#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
257#else
Haiying Wangc013b742008-10-29 13:32:59 -0400258#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
Kumar Gala18af1c52009-01-23 14:22:14 -0600259#endif
Kumar Galacb14e932010-11-12 08:22:01 -0600260#else
261#define CONFIG_SYS_NAND_BASE 0xfff00000
262#ifdef CONFIG_PHYS_64BIT
263#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
264#else
265#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
266#endif
267#endif
268
Haiying Wangc013b742008-10-29 13:32:59 -0400269#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
270 CONFIG_SYS_NAND_BASE + 0x40000, \
271 CONFIG_SYS_NAND_BASE + 0x80000,\
272 CONFIG_SYS_NAND_BASE + 0xC0000}
273#define CONFIG_SYS_MAX_NAND_DEVICE 4
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100274#define CONFIG_NAND_FSL_ELBC 1
Haiying Wangc013b742008-10-29 13:32:59 -0400275#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Prabhakar Kushwaha68ec9c82013-10-04 13:47:58 +0530276#define CONFIG_SYS_NAND_MAX_OOBFREE 5
277#define CONFIG_SYS_NAND_MAX_ECCPOS 56
Haiying Wangc013b742008-10-29 13:32:59 -0400278
Kumar Galacb14e932010-11-12 08:22:01 -0600279/* NAND boot: 4K NAND loader config */
280#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
281#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
282#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
283#define CONFIG_SYS_NAND_U_BOOT_START \
284 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
285#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
286#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
287#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
288
Haiying Wangc013b742008-10-29 13:32:59 -0400289/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500290#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100291 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
292 | BR_PS_8 /* Port Size = 8 bit */ \
293 | BR_MS_FCM /* MSEL = FCM */ \
294 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500295#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100296 | OR_FCM_PGS /* Large Page*/ \
297 | OR_FCM_CSCT \
298 | OR_FCM_CST \
299 | OR_FCM_CHT \
300 | OR_FCM_SCY_1 \
301 | OR_FCM_TRLX \
302 | OR_FCM_EHTR)
Haiying Wangc013b742008-10-29 13:32:59 -0400303
Kumar Galacb14e932010-11-12 08:22:01 -0600304#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
305#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500306#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
307#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabi7ee41102012-07-06 07:39:26 +0000308#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100309 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
310 | BR_PS_8 /* Port Size = 8 bit */ \
311 | BR_MS_FCM /* MSEL = FCM */ \
312 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500313#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Timur Tabi7ee41102012-07-06 07:39:26 +0000314#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100315 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
316 | BR_PS_8 /* Port Size = 8 bit */ \
317 | BR_MS_FCM /* MSEL = FCM */ \
318 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500319#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400320
Timur Tabi7ee41102012-07-06 07:39:26 +0000321#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
Wolfgang Denk3cbd8232008-11-02 16:14:22 +0100322 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
323 | BR_PS_8 /* Port Size = 8 bit */ \
324 | BR_MS_FCM /* MSEL = FCM */ \
325 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500326#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Haiying Wangc013b742008-10-29 13:32:59 -0400327
Kumar Gala129ba612008-08-12 11:13:08 -0500328/* Serial Port - controlled on board with jumper J8
329 * open - index 2
330 * shorted - index 1
331 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_NS16550_SERIAL
333#define CONFIG_SYS_NS16550_REG_SIZE 1
334#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Galacb14e932010-11-12 08:22:01 -0600335#ifdef CONFIG_NAND_SPL
336#define CONFIG_NS16550_MIN_FUNCTIONS
337#endif
Kumar Gala129ba612008-08-12 11:13:08 -0500338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala129ba612008-08-12 11:13:08 -0500340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
343#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Kumar Gala129ba612008-08-12 11:13:08 -0500344
Kumar Gala129ba612008-08-12 11:13:08 -0500345/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200346#define CONFIG_SYS_I2C
347#define CONFIG_SYS_I2C_FSL
348#define CONFIG_SYS_FSL_I2C_SPEED 400000
349#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
350#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
351#define CONFIG_SYS_FSL_I2C2_SPEED 400000
352#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
353#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
354#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Kumar Gala129ba612008-08-12 11:13:08 -0500356
357/*
Haiying Wang445a7b32008-10-03 11:47:30 -0400358 * I2C2 EEPROM
359 */
360#define CONFIG_ID_EEPROM
361#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_I2C_EEPROM_NXID
Haiying Wang445a7b32008-10-03 11:47:30 -0400363#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
365#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
366#define CONFIG_SYS_EEPROM_BUS_NUM 1
Haiying Wang445a7b32008-10-03 11:47:30 -0400367
368/*
Kumar Gala129ba612008-08-12 11:13:08 -0500369 * General PCI
370 * Memory space is mapped 1-1, but I/O space must start from 0.
371 */
372
Kumar Gala129ba612008-08-12 11:13:08 -0500373/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600374#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600375#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600376#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500377#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600378#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
379#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600380#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600381#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600382#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600384#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600385#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600386#ifdef CONFIG_PHYS_64BIT
387#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
388#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
Kumar Gala18af1c52009-01-23 14:22:14 -0600390#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500392
393/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600394#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600395#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600396#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500397#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600398#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
399#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600400#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600401#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600402#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600404#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600405#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600406#ifdef CONFIG_PHYS_64BIT
407#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
408#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
Kumar Gala18af1c52009-01-23 14:22:14 -0600410#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500412
413/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala18ea5552010-12-17 06:53:52 -0600414#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600415#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600416#ifdef CONFIG_PHYS_64BIT
Kumar Gala156984a2009-06-18 08:39:42 -0500417#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600418#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
419#else
Kumar Galaad97dce2009-02-09 22:03:05 -0600420#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600421#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600422#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600424#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600425#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Kumar Gala18af1c52009-01-23 14:22:14 -0600426#ifdef CONFIG_PHYS_64BIT
427#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
428#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
Kumar Gala18af1c52009-01-23 14:22:14 -0600430#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala129ba612008-08-12 11:13:08 -0500432
433#if defined(CONFIG_PCI)
434
435/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600436#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Kumar Gala129ba612008-08-12 11:13:08 -0500437
438/* video */
Kumar Gala129ba612008-08-12 11:13:08 -0500439
440#if defined(CONFIG_VIDEO)
441#define CONFIG_BIOSEMU
Kumar Gala129ba612008-08-12 11:13:08 -0500442#define CONFIG_ATI_RADEON_FB
443#define CONFIG_VIDEO_LOGO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala129ba612008-08-12 11:13:08 -0500445#endif
446
Kumar Gala129ba612008-08-12 11:13:08 -0500447#undef CONFIG_EEPRO100
448#undef CONFIG_TULIP
Kumar Gala129ba612008-08-12 11:13:08 -0500449
Kumar Gala129ba612008-08-12 11:13:08 -0500450#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600451 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
452 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS
Kumar Gala129ba612008-08-12 11:13:08 -0500453 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
454#endif
455
456#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Gala129ba612008-08-12 11:13:08 -0500457
458#ifdef CONFIG_SCSI_AHCI
459#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
461#define CONFIG_SYS_SCSI_MAX_LUN 1
462#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
Kumar Gala129ba612008-08-12 11:13:08 -0500463#endif /* SCSI */
464
465#endif /* CONFIG_PCI */
466
Kumar Gala129ba612008-08-12 11:13:08 -0500467#if defined(CONFIG_TSEC_ENET)
468
Kumar Gala129ba612008-08-12 11:13:08 -0500469#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
470#define CONFIG_TSEC1 1
471#define CONFIG_TSEC1_NAME "eTSEC1"
472#define CONFIG_TSEC2 1
473#define CONFIG_TSEC2_NAME "eTSEC2"
474#define CONFIG_TSEC3 1
475#define CONFIG_TSEC3_NAME "eTSEC3"
476#define CONFIG_TSEC4 1
477#define CONFIG_TSEC4_NAME "eTSEC4"
478
Liu Yu7e183ca2008-10-10 11:40:59 +0800479#define CONFIG_PIXIS_SGMII_CMD
480#define CONFIG_FSL_SGMII_RISER 1
481#define SGMII_RISER_PHY_OFFSET 0x1c
482
483#ifdef CONFIG_FSL_SGMII_RISER
484#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */
485#endif
486
Kumar Gala129ba612008-08-12 11:13:08 -0500487#define TSEC1_PHY_ADDR 0
488#define TSEC2_PHY_ADDR 1
489#define TSEC3_PHY_ADDR 2
490#define TSEC4_PHY_ADDR 3
491
492#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
493#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
494#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
495#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
496
497#define TSEC1_PHYIDX 0
498#define TSEC2_PHYIDX 0
499#define TSEC3_PHYIDX 0
500#define TSEC4_PHYIDX 0
501
502#define CONFIG_ETHPRIME "eTSEC1"
Kumar Gala129ba612008-08-12 11:13:08 -0500503#endif /* CONFIG_TSEC_ENET */
504
505/*
506 * Environment
507 */
Kumar Galacb14e932010-11-12 08:22:01 -0600508
Kumar Gala129ba612008-08-12 11:13:08 -0500509#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala129ba612008-08-12 11:13:08 -0500511
512/*
Zhao Chenhui863a3ea2011-03-04 16:31:41 +0800513 * USB
514 */
Zhao Chenhui863a3ea2011-03-04 16:31:41 +0800515
Tom Rini8850c5d2017-05-12 22:33:27 -0400516#ifdef CONFIG_USB_EHCI_HCD
Zhao Chenhui863a3ea2011-03-04 16:31:41 +0800517#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Zhao Chenhui863a3ea2011-03-04 16:31:41 +0800518#define CONFIG_PCI_EHCI_DEVICE 0
Zhao Chenhui863a3ea2011-03-04 16:31:41 +0800519#endif
520
Kumar Gala129ba612008-08-12 11:13:08 -0500521#undef CONFIG_WATCHDOG /* watchdog disabled */
522
523/*
524 * Miscellaneous configurable options
525 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala129ba612008-08-12 11:13:08 -0500527
528/*
529 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500530 * have to be in the first 64 MB of memory, since this is
Kumar Gala129ba612008-08-12 11:13:08 -0500531 * the maximum mapped by the Linux kernel during initialization.
532 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500533#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
534#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala129ba612008-08-12 11:13:08 -0500535
Kumar Gala129ba612008-08-12 11:13:08 -0500536#if defined(CONFIG_CMD_KGDB)
537#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala129ba612008-08-12 11:13:08 -0500538#endif
539
540/*
541 * Environment Configuration
542 */
Kumar Gala129ba612008-08-12 11:13:08 -0500543#if defined(CONFIG_TSEC_ENET)
544#define CONFIG_HAS_ETH0
Kumar Gala129ba612008-08-12 11:13:08 -0500545#define CONFIG_HAS_ETH1
Kumar Gala129ba612008-08-12 11:13:08 -0500546#define CONFIG_HAS_ETH2
Kumar Gala129ba612008-08-12 11:13:08 -0500547#define CONFIG_HAS_ETH3
Kumar Gala129ba612008-08-12 11:13:08 -0500548#endif
549
550#define CONFIG_IPADDR 192.168.1.254
551
Mario Six5bc05432018-03-28 14:38:20 +0200552#define CONFIG_HOSTNAME "unknown"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000553#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000554#define CONFIG_BOOTFILE "uImage"
Kumar Gala129ba612008-08-12 11:13:08 -0500555#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
556
557#define CONFIG_SERVERIP 192.168.1.1
558#define CONFIG_GATEWAYIP 192.168.1.1
559#define CONFIG_NETMASK 255.255.255.0
560
561/* default location for tftp and bootm */
562#define CONFIG_LOADADDR 1000000
563
Kumar Gala129ba612008-08-12 11:13:08 -0500564#define CONFIG_EXTRA_ENV_SETTINGS \
Hongtao Jia238e1462012-12-20 19:36:12 +0000565"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200566"netdev=eth0\0" \
567"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
568"tftpflash=tftpboot $loadaddr $uboot; " \
569 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
570 " +$filesize; " \
571 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
572 " +$filesize; " \
573 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
574 " $filesize; " \
575 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
576 " +$filesize; " \
577 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
578 " $filesize\0" \
579"consoledev=ttyS0\0" \
580"ramdiskaddr=2000000\0" \
581"ramdiskfile=8572ds/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500582"fdtaddr=1e00000\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200583"fdtfile=8572ds/mpc8572ds.dtb\0" \
584"bdev=sda3\0"
Kumar Gala129ba612008-08-12 11:13:08 -0500585
586#define CONFIG_HDBOOT \
587 "setenv bootargs root=/dev/$bdev rw " \
588 "console=$consoledev,$baudrate $othbootargs;" \
589 "tftp $loadaddr $bootfile;" \
590 "tftp $fdtaddr $fdtfile;" \
591 "bootm $loadaddr - $fdtaddr"
592
593#define CONFIG_NFSBOOTCOMMAND \
594 "setenv bootargs root=/dev/nfs rw " \
595 "nfsroot=$serverip:$rootpath " \
596 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
597 "console=$consoledev,$baudrate $othbootargs;" \
598 "tftp $loadaddr $bootfile;" \
599 "tftp $fdtaddr $fdtfile;" \
600 "bootm $loadaddr - $fdtaddr"
601
602#define CONFIG_RAMBOOTCOMMAND \
603 "setenv bootargs root=/dev/ram rw " \
604 "console=$consoledev,$baudrate $othbootargs;" \
605 "tftp $ramdiskaddr $ramdiskfile;" \
606 "tftp $loadaddr $bootfile;" \
607 "tftp $fdtaddr $fdtfile;" \
608 "bootm $loadaddr $ramdiskaddr $fdtaddr"
609
610#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
611
612#endif /* __CONFIG_H */