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wdenk8966f332002-10-31 23:30:59 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Config header file for Hymod board
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_HYMOD 1 /* ...on a Hymod board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050038#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk8966f332002-10-31 23:30:59 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
41
wdenk8966f332002-10-31 23:30:59 +000042#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */
43
44/*
45 * select serial console configuration
46 *
47 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
48 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
49 * for SCC).
50 *
51 * if CONFIG_CONS_NONE is defined, then the serial console routines must
52 * defined elsewhere (for example, on the cogent platform, there are serial
53 * ports on the motherboard which are used for the serial console - see
54 * cogent/cma101/serial.[ch]).
55 */
56#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
57#define CONFIG_CONS_ON_SCC /* define if console on SCC */
58#undef CONFIG_CONS_NONE /* define if console on something else*/
59#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
60#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
61#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
62#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
63
64/*
65 * select ethernet configuration
66 *
67 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
68 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
69 * for FCC)
70 *
71 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050072 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk8966f332002-10-31 23:30:59 +000073 */
74#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
75#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
76#undef CONFIG_ETHER_NONE /* define if ether on something else */
77#define CONFIG_ETHER_INDEX 1 /* which channel for ether */
wdenk6dd652f2003-06-19 23:40:20 +000078#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */
79
80#ifdef CONFIG_ETHER_ON_FCC
wdenk8966f332002-10-31 23:30:59 +000081
82#if (CONFIG_ETHER_INDEX == 1)
83
84/*
85 * - Rx-CLK is CLK10
86 * - Tx-CLK is CLK11
87 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
88 * - Enable Full Duplex in FSMR
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
91# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
92# define CONFIG_SYS_CPMFCR_RAMTYPE 0
93# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk8966f332002-10-31 23:30:59 +000094
wdenk6dd652f2003-06-19 23:40:20 +000095# define MDIO_PORT 0 /* Port A */
96# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */
97# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */
98
wdenk8966f332002-10-31 23:30:59 +000099#elif (CONFIG_ETHER_INDEX == 2)
100
101/*
102 * - Rx-CLK is CLK13
103 * - Tx-CLK is CLK14
104 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
105 * - Enable Full Duplex in FSMR
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
108# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
109# define CONFIG_SYS_CPMFCR_RAMTYPE 0
110# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk8966f332002-10-31 23:30:59 +0000111
wdenk6dd652f2003-06-19 23:40:20 +0000112# define MDIO_PORT 0 /* Port A */
113# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */
114# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */
115
wdenk8966f332002-10-31 23:30:59 +0000116#elif (CONFIG_ETHER_INDEX == 3)
117
118/*
119 * - Rx-CLK is CLK15
120 * - Tx-CLK is CLK16
121 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
122 * - Enable Full Duplex in FSMR
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
125# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
126# define CONFIG_SYS_CPMFCR_RAMTYPE 0
127# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk8966f332002-10-31 23:30:59 +0000128
wdenk6dd652f2003-06-19 23:40:20 +0000129# define MDIO_PORT 0 /* Port A */
130# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */
131# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */
132
wdenk8966f332002-10-31 23:30:59 +0000133#endif /* CONFIG_ETHER_INDEX */
134
wdenk6dd652f2003-06-19 23:40:20 +0000135#define CONFIG_MII /* MII PHY management */
136#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
137
138#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK)
139#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK)
140#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0)
141
142#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \
143 else iop->pdat &= ~MDIO_DATA_PINMASK
144
145#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \
146 else iop->pdat &= ~MDIO_CLCK_PINMASK
147
148#define MIIDELAY udelay(1)
149
150#endif /* CONFIG_ETHER_ON_FCC */
151
wdenk8966f332002-10-31 23:30:59 +0000152
153/* other options */
154#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */
wdenk6dd652f2003-06-19 23:40:20 +0000155#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
wdenk8966f332002-10-31 23:30:59 +0000156
157/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
158#ifdef DEBUG
159#define CONFIG_8260_CLKIN 33333333 /* in Hz */
160#else
161#define CONFIG_8260_CLKIN 66666666 /* in Hz */
162#endif
163
164#if defined(CONFIG_CONS_USE_EXTC)
165#define CONFIG_BAUDRATE 115200
166#else
wdenk6dd652f2003-06-19 23:40:20 +0000167#define CONFIG_BAUDRATE 9600
wdenk8966f332002-10-31 23:30:59 +0000168#endif
169
170/* default ip addresses - these will be overridden */
171#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */
172#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */
173
wdenk6dd652f2003-06-19 23:40:20 +0000174#define CONFIG_LAST_STAGE_INIT
175
Jon Loeliger48d5d102007-07-04 22:32:25 -0500176/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500177 * BOOTP options
178 */
179#define CONFIG_BOOTP_BOOTFILESIZE
180#define CONFIG_BOOTP_BOOTPATH
181#define CONFIG_BOOTP_GATEWAY
182#define CONFIG_BOOTP_HOSTNAME
183
184
185/*
Jon Loeliger48d5d102007-07-04 22:32:25 -0500186 * Command line configuration.
187 */
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200188#include <config_cmd_default.h>
wdenk8966f332002-10-31 23:30:59 +0000189
Jean-Christophe PLAGNIOL-VILLARD4e620412007-10-24 18:16:01 +0200190#define CONFIG_CMD_ASKENV
191#define CONFIG_CMD_BSP
192#define CONFIG_CMD_CACHE
193#define CONFIG_CMD_CDP
194#define CONFIG_CMD_DATE
195#define CONFIG_CMD_DHCP
196#define CONFIG_CMD_DIAG
197#define CONFIG_CMD_DTT
198#define CONFIG_CMD_EEPROM
199#define CONFIG_CMD_ELF
200#define CONFIG_CMD_FAT
201#define CONFIG_CMD_I2C
202#define CONFIG_CMD_IMMAP
203#define CONFIG_CMD_IRQ
204#define CONFIG_CMD_KGDB
205#define CONFIG_CMD_MII
206#define CONFIG_CMD_PING
207#define CONFIG_CMD_PORTIO
208#define CONFIG_CMD_REGINFO
209#define CONFIG_CMD_SAVES
210#define CONFIG_CMD_SDRAM
211#define CONFIG_CMD_SNTP
212
Jon Loeliger48d5d102007-07-04 22:32:25 -0500213#undef CONFIG_CMD_FPGA
Jon Loeliger48d5d102007-07-04 22:32:25 -0500214#undef CONFIG_CMD_XIMG
215
wdenk8966f332002-10-31 23:30:59 +0000216#ifdef DEBUG
217#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
wdenk6dd652f2003-06-19 23:40:20 +0000218#else
219#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
220#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */
221#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */
222/* Be selective on what keys can delay or stop the autoboot process
223 * To stop use: " "
224 */
225#define CONFIG_AUTOBOOT_KEYED
226#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
Stefan Roesef2302d42008-08-06 14:05:38 +0200227 "press <SPACE> to stop\n", bootdelay
wdenk6dd652f2003-06-19 23:40:20 +0000228#define CONFIG_AUTOBOOT_STOP_STR " "
229#undef CONFIG_AUTOBOOT_DELAY_STR
230#define DEBUG_BOOTKEYS 0
wdenk8966f332002-10-31 23:30:59 +0000231#endif
232
Jon Loeliger48d5d102007-07-04 22:32:25 -0500233#if defined(CONFIG_CMD_KGDB)
wdenk8966f332002-10-31 23:30:59 +0000234#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
235#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
236#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
237#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
238#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
239#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */
240#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
241# if defined(CONFIG_KGDB_USE_EXTC)
wdenk592c5ca2003-06-21 00:17:24 +0000242#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
wdenk8966f332002-10-31 23:30:59 +0000243# else
wdenk6dd652f2003-06-19 23:40:20 +0000244#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
wdenk8966f332002-10-31 23:30:59 +0000245# endif
246#endif
247
248#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
249
250#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
251
252/*
253 * Hymod specific configurable options
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */
wdenk8966f332002-10-31 23:30:59 +0000256
257/*
258 * Miscellaneous configurable options
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_LONGHELP /* undef to save memory */
261#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500262#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk8966f332002-10-31 23:30:59 +0000264#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk8966f332002-10-31 23:30:59 +0000266#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
268#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
269#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk8966f332002-10-31 23:30:59 +0000270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
272#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */
wdenk8966f332002-10-31 23:30:59 +0000273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk8966f332002-10-31 23:30:59 +0000275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk8966f332002-10-31 23:30:59 +0000277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk8966f332002-10-31 23:30:59 +0000279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_I2C_SPEED 50000
281#define CONFIG_SYS_I2C_SLAVE 0x7e
wdenk8966f332002-10-31 23:30:59 +0000282
283/* these are for the ST M24C02 2kbit serial i2c eeprom */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
285#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenk6dd652f2003-06-19 23:40:20 +0000286/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
wdenk6dd652f2003-06-19 23:40:20 +0000288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */
290#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk6dd652f2003-06-19 23:40:20 +0000291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */
wdenk6dd652f2003-06-19 23:40:20 +0000293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */
wdenk8966f332002-10-31 23:30:59 +0000295
296/*
wdenk6dd652f2003-06-19 23:40:20 +0000297 * standard dtt sensor configuration - bottom bit will determine local or
298 * remote sensor of the ADM1021, the rest determines index into
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299 * CONFIG_SYS_DTT_ADM1021 array below.
wdenk6dd652f2003-06-19 23:40:20 +0000300 *
301 * On HYMOD board, the remote sensor should be connected to the MPC8260
302 * temperature diode thingy, but an errata said this didn't work and
303 * should be disabled - so it isn't connected.
304 */
305#if 0
306#define CONFIG_DTT_SENSORS { 0, 1 }
307#else
308#define CONFIG_DTT_SENSORS { 0 }
309#endif
310
311/*
312 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
313 * there will be one entry in this array for each two (dummy) sensors in
314 * CONFIG_DTT_SENSORS.
315 *
316 * For HYMOD board:
317 * - only one ADM1021
318 * - i2c addr 0x2a (both ADD0 and ADD1 are N/C)
319 * - conversion rate 0x02 = 0.25 conversions/second
320 * - ALERT ouput disabled
321 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
322 * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above)
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } }
wdenk6dd652f2003-06-19 23:40:20 +0000325
326/*
wdenk8966f332002-10-31 23:30:59 +0000327 * Low Level Configuration Settings
328 * (address mappings, register initial values, etc.)
329 * You should know what you are doing if you make changes here.
330 */
331
332/*-----------------------------------------------------------------------
333 * Hard Reset Configuration Words
334 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk8966f332002-10-31 23:30:59 +0000336 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk8966f332002-10-31 23:30:59 +0000338 */
339#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
wdenk8966f332002-10-31 23:30:59 +0000341 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
342 HRCW_MODCK_H0010)
343#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
wdenk8966f332002-10-31 23:30:59 +0000345 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
346 HRCW_MODCK_H0101)
347#endif
348/* no slaves so just duplicate the master hrcw */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER
350#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER
351#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER
352#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER
353#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER
354#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER
355#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER
wdenk8966f332002-10-31 23:30:59 +0000356
357/*-----------------------------------------------------------------------
358 * Internal Memory Mapped Register
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_IMMR 0xF0000000
wdenk8966f332002-10-31 23:30:59 +0000361
362/*-----------------------------------------------------------------------
363 * Definitions for initial stack pointer and data area (in DPRAM)
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
366#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
367#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
368#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
369#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk8966f332002-10-31 23:30:59 +0000370
371/*-----------------------------------------------------------------------
372 * Start addresses for the final memory configuration
373 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk8966f332002-10-31 23:30:59 +0000375 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_SDRAM_BASE 0x00000000
377#define CONFIG_SYS_FLASH_BASE TEXT_BASE
378#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
379#define CONFIG_SYS_FPGA_BASE 0x80000000
wdenk8966f332002-10-31 23:30:59 +0000380/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381 * unfortunately, CONFIG_SYS_MONITOR_LEN must include the
wdenk8966f332002-10-31 23:30:59 +0000382 * (very large i.e. 256kB) environment flash sector
383 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/
385#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk8966f332002-10-31 23:30:59 +0000386
387/*
388 * For booting Linux, the board info and command line data
389 * have to be in the first 8 MB of memory, since this is
390 * the maximum mapped by the Linux kernel during initialization.
391 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
wdenk8966f332002-10-31 23:30:59 +0000393
394/*-----------------------------------------------------------------------
395 * FLASH organization
396 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
398#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
wdenk8966f332002-10-31 23:30:59 +0000399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
401#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk8966f332002-10-31 23:30:59 +0000402
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200403#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200404#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
405#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE)
407#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk8966f332002-10-31 23:30:59 +0000408
409/*-----------------------------------------------------------------------
410 * Cache Configuration
411 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500413#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/
wdenk8966f332002-10-31 23:30:59 +0000415#endif
416
417/*-----------------------------------------------------------------------
418 * HIDx - Hardware Implementation-dependent Registers 2-11
419 *-----------------------------------------------------------------------
420 * HID0 also contains cache control - initially enable both caches and
421 * invalidate contents, then the final state leaves only the instruction
422 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
423 * but Soft reset does not.
424 *
425 * HID1 has only read-only information - nothing to set.
426 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenk8966f332002-10-31 23:30:59 +0000428 HID0_IFEM|HID0_ABE)
429#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_HID0_FINAL 0
wdenk8966f332002-10-31 23:30:59 +0000431#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
wdenk8966f332002-10-31 23:30:59 +0000433#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_HID2 0
wdenk8966f332002-10-31 23:30:59 +0000435
436/*-----------------------------------------------------------------------
437 * RMR - Reset Mode Register 5-5
438 *-----------------------------------------------------------------------
439 * turn on Checkstop Reset Enable
440 */
441#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_RMR 0
wdenk8966f332002-10-31 23:30:59 +0000443#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_RMR RMR_CSRE
wdenk8966f332002-10-31 23:30:59 +0000445#endif
446
447/*-----------------------------------------------------------------------
448 * BCR - Bus Configuration 4-25
449 *-----------------------------------------------------------------------
450 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_BCR (BCR_ETM)
wdenk8966f332002-10-31 23:30:59 +0000452
453/*-----------------------------------------------------------------------
454 * SIUMCR - SIU Module Configuration 4-31
455 *-----------------------------------------------------------------------
456 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
wdenk8966f332002-10-31 23:30:59 +0000458 SIUMCR_APPC10|SIUMCR_MMR11)
459
460/*-----------------------------------------------------------------------
461 * SYPCR - System Protection Control 4-35
462 * SYPCR can only be written once after reset!
463 *-----------------------------------------------------------------------
464 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
465 */
466#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8966f332002-10-31 23:30:59 +0000468 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
469#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8966f332002-10-31 23:30:59 +0000471 SYPCR_SWRI|SYPCR_SWP)
472#endif /* CONFIG_WATCHDOG */
473
474/*-----------------------------------------------------------------------
475 * TMCNTSC - Time Counter Status and Control 4-40
476 *-----------------------------------------------------------------------
477 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
478 * and enable Time Counter
479 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk8966f332002-10-31 23:30:59 +0000481
482/*-----------------------------------------------------------------------
483 * PISCR - Periodic Interrupt Status and Control 4-42
484 *-----------------------------------------------------------------------
485 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
486 * Periodic timer
487 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk8966f332002-10-31 23:30:59 +0000489
490/*-----------------------------------------------------------------------
491 * SCCR - System Clock Control 9-8
492 *-----------------------------------------------------------------------
493 * Ensure DFBRG is Divide by 16
494 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_SCCR (SCCR_DFBRG01)
wdenk8966f332002-10-31 23:30:59 +0000496
497/*-----------------------------------------------------------------------
498 * RCCR - RISC Controller Configuration 13-7
499 *-----------------------------------------------------------------------
500 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_RCCR 0
wdenk8966f332002-10-31 23:30:59 +0000502
503/*
504 * Init Memory Controller:
505 *
506 * Bank Bus Machine PortSz Device
507 * ---- --- ------- ------ ------
508 * 0 60x GPCM 32 bit FLASH
509 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now)
510 * 2 60x SDRAM 64 bit SDRAM
511 * 3 Local UPMC 8 bit Main Xilinx configuration
512 * 4 Local GPCM 32 bit Main Xilinx register mode
513 * 5 Local UPMB 32 bit Main Xilinx port mode
514 * 6 Local UPMC 8 bit Mezz Xilinx configuration
515 */
516
517/*
518 * Bank 0 - FLASH
519 *
520 * Quotes from the HYMOD IO Board Reference manual:
521 *
522 * "The flash memory is two Intel StrataFlash chips, each configured for
523 * 16 bit operation and connected to give a 32 bit wide port."
524 *
525 * "The chip select logic is configured to respond to both *CS0 and *CS1.
526 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
527 * It is suggested that bank 0 be read-only and bank 1 be read/write. The
528 * FLASH will then appear as ROM during boot."
529 *
530 * Initially, we are only going to use bank 0 in read/write mode.
531 */
532
533/* 32 bit, read-write, GPCM on 60x bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\
wdenk8966f332002-10-31 23:30:59 +0000535 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
536/* up to 32 Mb */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
wdenk8966f332002-10-31 23:30:59 +0000538
539/*
540 * Bank 2 - SDRAM
541 *
542 * Quotes from the HYMOD IO Board Reference manual:
543 *
544 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
545 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
546 * dynamic random access memory organised as 4 banks by 4096 rows by 512
547 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
548 *
549 * "The locations in SDRAM are accessed using multiplexed address pins to
550 * specify row and column. The pins also act to specify commands. The state
551 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
552 * pin may function as a row address or as the AUTO PRECHARGE control line,
553 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
554 * address lines to be configured to the required multiplexing scheme."
555 */
556
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_SDRAM_SIZE 64
wdenk8966f332002-10-31 23:30:59 +0000558
559/* 64 bit, read-write, SDRAM on 60x bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\
wdenk8966f332002-10-31 23:30:59 +0000561 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
562/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\
wdenk8966f332002-10-31 23:30:59 +0000564 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
565
566/*
567 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
568 *
569 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
570 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
571 * as bank select, A7 is output on SDA10 during an ACTIVATE command,
572 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
573 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
574 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
575 * command is 2 clocks, earliest timing for PRECHARGE after last data
576 * was read is 1 clock, earliest timing for PRECHARGE after last data
577 * was written is 1 clock, CAS Latency is 2.
578 */
579
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200580#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
wdenk8966f332002-10-31 23:30:59 +0000581 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
582 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
583 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
584 PSDMR_WRC_1C|PSDMR_CL_2)
585
586/*
587 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
588 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
589 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
590 * Prescaler, hence the P instead of the R). The refresh timer period is given
591 * by (note that there was a change in the 8260 UM Errata):
592 *
593 * TimerPeriod = (PSRT + 1) / Fmptc
594 *
595 * where Fmptc is the BusClock divided by PTP. i.e.
596 *
597 * TimerPeriod = (PSRT + 1) / (BusClock / PTP)
598 *
599 * or
600 *
601 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock
602 *
603 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
604 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
605 * = 15.625 usecs.
606 *
607 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
608 * appear to be reasonable.
609 */
610
611#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612#define CONFIG_SYS_PSRT 39
613#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8
wdenk8966f332002-10-31 23:30:59 +0000614#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615#define CONFIG_SYS_PSRT 31
616#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenk8966f332002-10-31 23:30:59 +0000617#endif
618
619/*
620 * Banks 3,4,5 and 6 - FPGA access
621 *
622 * Quotes from the HYMOD IO Board Reference manual:
623 *
624 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
625 * for configuring an optional FPGA on the mezzanine interface.
626 *
627 * Access to the FPGAs may be divided into several catagories:
628 *
629 * 1. Configuration
630 * 2. Register mode access
631 * 3. Port mode access
632 *
633 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
634 * configured only (mode 1). Consequently there are four access types.
635 *
636 * To improve interface performance and simplify software design, the four
637 * possible access types are separately mapped to different memory banks.
638 *
639 * All are accessed using the local bus."
640 *
641 * Device Mode Memory Bank Machine Port Size Access
642 *
643 * Main Configuration 3 UPMC 8bit R/W
644 * Main Register 4 GPCM 32bit R/W
645 * Main Port 5 UPMB 32bit R/W
646 * Mezzanine Configuration 6 UPMC 8bit W/O
647 *
648 * "Note that mezzanine mode 1 access is write-only."
649 */
650
651/* all the bank sizes must be a power of two, greater or equal to 32768 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200652#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE)
wdenk8966f332002-10-31 23:30:59 +0000653#define FPGA_MAIN_CFG_SIZE 32768
654#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
655#define FPGA_MAIN_REG_SIZE 32768
656#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
657#define FPGA_MAIN_PORT_SIZE 32768
658#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
659#define FPGA_MEZZ_CFG_SIZE 32768
660
661/* 8 bit, read-write, UPMC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200662#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
wdenk8966f332002-10-31 23:30:59 +0000663/* up to 32Kbyte, burst inhibit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200664#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
wdenk8966f332002-10-31 23:30:59 +0000665
666/* 32 bit, read-write, GPCM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200667#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
wdenk8966f332002-10-31 23:30:59 +0000668/* up to 32Kbyte */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200669#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
wdenk8966f332002-10-31 23:30:59 +0000670
671/* 32 bit, read-write, UPMB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200672#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
wdenk8966f332002-10-31 23:30:59 +0000673/* up to 32Kbyte */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200674#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
wdenk8966f332002-10-31 23:30:59 +0000675
676/* 8 bit, write-only, UPMC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200677#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
wdenk8966f332002-10-31 23:30:59 +0000678/* up to 32Kbyte, burst inhibit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200679#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
wdenk8966f332002-10-31 23:30:59 +0000680
681/*-----------------------------------------------------------------------
682 * MBMR - Machine B Mode 10-27
683 *-----------------------------------------------------------------------
684 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200685#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */
wdenk8966f332002-10-31 23:30:59 +0000686
687/*-----------------------------------------------------------------------
688 * MCMR - Machine C Mode 10-27
689 *-----------------------------------------------------------------------
690 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200691#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */
wdenk8966f332002-10-31 23:30:59 +0000692
693/*
694 * FPGA I/O Port/Bit information
695 */
696
697#define FPGA_MAIN_PROG_PORT IOPIN_PORTA
698#define FPGA_MAIN_PROG_PIN 4 /* PA4 */
699#define FPGA_MAIN_INIT_PORT IOPIN_PORTA
700#define FPGA_MAIN_INIT_PIN 5 /* PA5 */
701#define FPGA_MAIN_DONE_PORT IOPIN_PORTA
702#define FPGA_MAIN_DONE_PIN 6 /* PA6 */
703
704#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA
705#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */
706#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA
707#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */
708#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA
709#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */
710#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA
711#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */
712
713/*
wdenk6dd652f2003-06-19 23:40:20 +0000714 * FPGA Interrupt configuration
715 */
716#define FPGA_MAIN_IRQ SIU_INT_IRQ2
717
718/*
wdenk8966f332002-10-31 23:30:59 +0000719 * Internal Definitions
720 *
721 * Boot Flags
722 */
723#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
724#define BOOTFLAG_WARM 0x02 /* Software reboot */
725
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200726/*
727 * JFFS2 partitions
728 *
729 */
730/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100731#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200732#define CONFIG_JFFS2_DEV "nor0"
733#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
734#define CONFIG_JFFS2_PART_OFFSET 0x00000000
735
736/* mtdparts command line support */
737/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100738#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200739#define MTDIDS_DEFAULT ""
740#define MTDPARTS_DEFAULT ""
741*/
742
wdenk8966f332002-10-31 23:30:59 +0000743#endif /* __CONFIG_H */