blob: 6fb0096bede97a7e4f70885c7c09a86d2649b175 [file] [log] [blame]
dzu@denx.de6ca24c62006-04-21 18:30:47 +02001/*
dzu@denx.de6ca24c62006-04-21 18:30:47 +02002 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * (C) Copyright 2004-2005
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
10 *
11 * (C) Copyright 2006
12 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
13 *
dzu@denx.de6ca24c62006-04-21 18:30:47 +020014 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#include <common.h>
34#include <mpc5xxx.h>
35#include <pci.h>
Ben Warren19403632008-08-31 10:03:22 -070036#include <netdev.h>
dzu@denx.de6ca24c62006-04-21 18:30:47 +020037
38#ifdef CONFIG_VIDEO_SM501
39#include <sm501.h>
40#endif
41
42#if defined(CONFIG_MPC5200_DDR)
43#include "mt46v16m16-75.h"
44#else
45#include "mt48lc16m16a2-75.h"
46#endif
47
48#ifdef CONFIG_RTC_MPC5200
49#include <rtc.h>
Wolfgang Denk610cf362006-05-03 01:24:04 +020050#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +020051
52#ifdef CONFIG_PS2MULT
53void ps2mult_early_init(void);
54#endif
55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#ifndef CONFIG_SYS_RAMBOOT
dzu@denx.de6ca24c62006-04-21 18:30:47 +020057static void sdram_start (int hi_addr)
58{
59 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
60
61 /* unlock mode register */
62 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
63 hi_addr_bit;
64 __asm__ volatile ("sync");
65
66 /* precharge all banks */
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
68 hi_addr_bit;
69 __asm__ volatile ("sync");
70
71#if SDRAM_DDR
72 /* set mode register: extended mode */
73 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
74 __asm__ volatile ("sync");
75
76 /* set mode register: reset DLL */
77 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
78 __asm__ volatile ("sync");
79#endif
80
81 /* precharge all banks */
82 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
83 hi_addr_bit;
84 __asm__ volatile ("sync");
85
86 /* auto refresh */
87 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
88 hi_addr_bit;
89 __asm__ volatile ("sync");
90
91 /* set mode register */
92 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
93 __asm__ volatile ("sync");
94
95 /* normal operation */
96 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
97 __asm__ volatile ("sync");
98}
99#endif
100
101/*
102 * ATTENTION: Although partially referenced initdram does NOT make real use
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200104 * is something else than 0x00000000.
105 */
106
107#if defined(CONFIG_MPC5200)
Becky Bruce9973e3c2008-06-09 16:03:40 -0500108phys_size_t initdram (int board_type)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200109{
110 ulong dramsize = 0;
111 ulong dramsize2 = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#ifndef CONFIG_SYS_RAMBOOT
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200113 ulong test1, test2;
114
115 /* setup SDRAM chip selects */
116 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
117 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
118 __asm__ volatile ("sync");
119
120 /* setup config registers */
121 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
122 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
123 __asm__ volatile ("sync");
124
125#if SDRAM_DDR
126 /* set tap delay */
127 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
128 __asm__ volatile ("sync");
129#endif
130
131 /* find RAM size using SDRAM CS0 only */
132 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200134 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200136 if (test1 > test2) {
137 sdram_start(0);
138 dramsize = test1;
139 } else {
140 dramsize = test2;
141 }
142
143 /* memory smaller than 1MB is impossible */
144 if (dramsize < (1 << 20)) {
145 dramsize = 0;
146 }
147
148 /* set SDRAM CS0 size according to the amount of RAM found */
149 if (dramsize > 0) {
150 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
151 __builtin_ffs(dramsize >> 20) - 1;
152 } else {
153 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
154 }
155
156 /* let SDRAM CS1 start right after CS0 */
157 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
158
159 /* find RAM size using SDRAM CS1 only */
160 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200162 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200164 if (test1 > test2) {
165 sdram_start(0);
166 dramsize2 = test1;
167 } else {
168 dramsize2 = test2;
169 }
170
171 /* memory smaller than 1MB is impossible */
172 if (dramsize2 < (1 << 20)) {
173 dramsize2 = 0;
174 }
175
176 /* set SDRAM CS1 size according to the amount of RAM found */
177 if (dramsize2 > 0) {
178 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
179 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
180 } else {
181 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
182 }
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#else /* CONFIG_SYS_RAMBOOT */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200185
186 /* retrieve size of memory connected to SDRAM CS0 */
187 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
188 if (dramsize >= 0x13) {
189 dramsize = (1 << (dramsize - 0x13)) << 20;
190 } else {
191 dramsize = 0;
192 }
193
194 /* retrieve size of memory connected to SDRAM CS1 */
195 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
196 if (dramsize2 >= 0x13) {
197 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
198 } else {
199 dramsize2 = 0;
200 }
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#endif /* CONFIG_SYS_RAMBOOT */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200203
204 return dramsize;
205}
206
207#elif defined(CONFIG_MGT5100)
208
Becky Bruce9973e3c2008-06-09 16:03:40 -0500209phys_size_t initdram (int board_type)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200210{
211 ulong dramsize = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#ifndef CONFIG_SYS_RAMBOOT
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200213 ulong test1, test2;
214
215 /* setup and enable SDRAM chip selects */
216 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
217 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */
218 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
219 __asm__ volatile ("sync");
220
221 /* setup config registers */
222 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
223 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
224
225 /* address select register */
226 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
227 __asm__ volatile ("sync");
228
229 /* find RAM size */
230 sdram_start(0);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231 test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200232 sdram_start(1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233 test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200234 if (test1 > test2) {
235 sdram_start(0);
236 dramsize = test1;
237 } else {
238 dramsize = test2;
239 }
240
241 /* set SDRAM end address according to size */
242 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#else /* CONFIG_SYS_RAMBOOT */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200245
246 /* Retrieve amount of SDRAM available */
247 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#endif /* CONFIG_SYS_RAMBOOT */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200250
251 return dramsize;
252}
253
254#else
255#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
256#endif
257
258int checkboard (void)
259{
260#if defined (CONFIG_TQM5200)
261 puts ("Board: TQM5200 (TQ-Components GmbH)\n");
262#endif
263
264#if defined (CONFIG_BC3450)
265 puts ("Dev: GERSYS BC3450\n");
266#endif
267
268 return 0;
269}
270
271void flash_preinit(void)
272{
273 /*
274 * Now, when we are in RAM, enable flash write
275 * access for detection process.
276 * Note that CS_BOOT cannot be cleared when
277 * executing in flash.
278 */
279#if defined(CONFIG_MGT5100)
280 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
281 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
282#endif
283 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
284}
285
286
287#ifdef CONFIG_PCI
288static struct pci_controller hose;
289
290extern void pci_mpc5xxx_init(struct pci_controller *);
291
292void pci_init_board(void)
293{
294 pci_mpc5xxx_init(&hose);
295}
296#endif
297
Jon Loeliger77a31852007-07-10 10:39:10 -0500298#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200299
300void init_ide_reset (void)
301{
302 debug ("init_ide_reset\n");
303
304 /* Configure PSC1_4 as GPIO output for ATA reset */
305 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
306 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
307}
308
309void ide_set_reset (int idereset)
310{
311 debug ("ide_reset(%d)\n", idereset);
312
313 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100314 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200315 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100316 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200317 }
318}
Jon Loeliger77a31852007-07-10 10:39:10 -0500319#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200320
321#ifdef CONFIG_POST
322/*
323 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
324 * is left open, no keypress is detected.
325 */
326int post_hotkeys_pressed(void)
327{
328 struct mpc5xxx_gpio *gpio;
329
330 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
331
332 /*
333 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
334 * CODEC or UART mode. Consumer IrDA should still be possible.
335 */
336 gpio->port_config &= ~(0x07000000);
337 gpio->port_config |= 0x03000000;
338
339 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
340 gpio->simple_gpioe |= 0x20000000;
341
342 /* Configure GPIO_IRDA_1 as input */
343 gpio->simple_ddr &= ~(0x20000000);
344
345 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
346}
347#endif
348
349#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
350
351void post_word_store (ulong a)
352{
353 volatile ulong *save_addr =
354 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
355
356 *save_addr = a;
357}
358
359ulong post_word_load (void)
360{
361 volatile ulong *save_addr =
362 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
363
364 return *save_addr;
365}
366#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
367
368
369#ifdef CONFIG_BOARD_EARLY_INIT_R
370int board_early_init_r (void)
371{
372#ifdef CONFIG_RTC_MPC5200
Wolfgang Denk610cf362006-05-03 01:24:04 +0200373 struct rtc_time t;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200374
375 /* set to Wed Dec 31 19:00:00 1969 */
376 t.tm_sec = t.tm_min = 0;
377 t.tm_hour = 19;
378 t.tm_mday = 31;
379 t.tm_mon = 12;
380 t.tm_year = 1969;
381 t.tm_wday = 3;
Wolfgang Denk610cf362006-05-03 01:24:04 +0200382
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200383 rtc_set(&t);
384#endif /* CONFIG_RTC_MPC5200 */
385
386#ifdef CONFIG_PS2MULT
387 ps2mult_early_init();
388#endif /* CONFIG_PS2MULT */
389 return (0);
390}
391#endif /* CONFIG_BOARD_EARLY_INIT_R */
392
393
394int last_stage_init (void)
395{
396 /*
397 * auto scan for really existing devices and re-set chip select
398 * configuration.
399 */
400 u16 save, tmp;
401 int restore;
402
403 /*
404 * Check for SRAM and SRAM size
405 */
406
407 /* save original SRAM content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200409 restore = 1;
410
411 /* write test pattern to SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200413 __asm__ volatile ("sync");
414 /*
415 * Put a different pattern on the data lines: otherwise they may float
416 * long enough to read back what we wrote.
417 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200419 if (tmp == 0xA5A5)
420 puts ("!! possible error in SRAM detection\n");
421
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200423 /* no SRAM at all, disable cs */
424 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
425 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
426 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
427 restore = 0;
428 __asm__ volatile ("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200430 /* make sure that we access a mirrored address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200432 __asm__ volatile ("sync");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200434 /* SRAM size = 512 kByte */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200436 0x80000);
437 __asm__ volatile ("sync");
438 puts ("SRAM: 512 kB\n");
439 }
440 else
441 puts ("!! possible error in SRAM detection\n");
442 } else {
443 puts ("SRAM: 1 MB\n");
444 }
445 /* restore origianl SRAM content */
446 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200448 __asm__ volatile ("sync");
449 }
450
451 /*
452 * Check for Grafic Controller
453 */
454
455 /* save origianl FB content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200457 restore = 1;
458
459 /* write test pattern to FB memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200461 __asm__ volatile ("sync");
462 /*
463 * Put a different pattern on the data lines: otherwise they may float
464 * long enough to read back what we wrote.
465 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200467 if (tmp == 0xA5A5)
468 puts ("!! possible error in grafic controller detection\n");
469
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200471 /* no grafic controller at all, disable cs */
472 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
473 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
474 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
475 restore = 0;
476 __asm__ volatile ("sync");
477 } else {
478 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
479 }
Wolfgang Denk610cf362006-05-03 01:24:04 +0200480 /* restore origianl FB content */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200481 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200483 __asm__ volatile ("sync");
484 }
485
486 return 0;
487}
488
489#ifdef CONFIG_VIDEO_SM501
490
Wolfgang Denk610cf362006-05-03 01:24:04 +0200491#define DISPLAY_WIDTH 640
492#define DISPLAY_HEIGHT 480
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200493
494#ifdef CONFIG_VIDEO_SM501_8BPP
495#error CONFIG_VIDEO_SM501_8BPP not supported.
496#endif /* CONFIG_VIDEO_SM501_8BPP */
497
498#ifdef CONFIG_VIDEO_SM501_16BPP
499#error CONFIG_VIDEO_SM501_16BPP not supported.
500#endif /* CONFIG_VIDEO_SM501_16BPP */
501
502#ifdef CONFIG_VIDEO_SM501_32BPP
503static const SMI_REGS init_regs [] =
504{
505#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
506 /* FP only */
507 {0x00004, 0x0},
508 {0x00048, 0x00021807},
509 {0x0004C, 0x091a0a01},
510 {0x00054, 0x1},
511 {0x00040, 0x00021807},
512 {0x00044, 0x091a0a01},
513 {0x00054, 0x0},
514 {0x80000, 0x01013106},
515 {0x80004, 0xc428bb17},
516 {0x80000, 0x03013106},
517 {0x8000C, 0x00000000},
518 {0x80010, 0x0a000a00},
519 {0x80014, 0x02800000},
520 {0x80018, 0x01e00000},
521 {0x8001C, 0x00000000},
522 {0x80020, 0x01e00280},
523 {0x80024, 0x02fa027f},
524 {0x80028, 0x004a028b},
525 {0x8002C, 0x020c01df},
526 {0x80030, 0x000201e9},
527 {0x80200, 0x00010200},
528 {0x80000, 0x0f013106},
529#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
530 /* CRT only */
531 {0x00004, 0x0},
532 {0x00048, 0x00021807},
533 {0x0004C, 0x10090a01},
534 {0x00054, 0x1},
535 {0x00040, 0x00021807},
536 {0x00044, 0x10090a01},
537 {0x00054, 0x0},
538 {0x80200, 0x00010000},
539 {0x80204, 0x0},
540 {0x80208, 0x0A000A00},
541 {0x8020C, 0x02fa027f},
542 {0x80210, 0x004a028b},
543 {0x80214, 0x020c01df},
544 {0x80218, 0x000201e9},
545 {0x80200, 0x00013306},
546#else /* panel + CRT */
547 {0x00004, 0x0},
548 {0x00048, 0x00021807},
549 {0x0004C, 0x091a0a01},
550 {0x00054, 0x1},
551 {0x00040, 0x00021807},
552 {0x00044, 0x091a0a01},
553 {0x00054, 0x0},
554 {0x80000, 0x0f013106},
555 {0x80004, 0xc428bb17},
556 {0x8000C, 0x00000000},
557 {0x80010, 0x0a000a00},
558 {0x80014, 0x02800000},
559 {0x80018, 0x01e00000},
560 {0x8001C, 0x00000000},
561 {0x80020, 0x01e00280},
562 {0x80024, 0x02fa027f},
563 {0x80028, 0x004a028b},
564 {0x8002C, 0x020c01df},
565 {0x80030, 0x000201e9},
566 {0x80200, 0x00010000},
567#endif
568 {0, 0}
569};
570#endif /* CONFIG_VIDEO_SM501_32BPP */
571
572#ifdef CONFIG_CONSOLE_EXTRA_INFO
573/*
574 * Return text to be printed besides the logo.
575 */
576void video_get_info_str (int line_number, char *info)
577{
578 if (line_number == 1) {
579#if defined (CONFIG_TQM5200)
580 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
581#else
582#error No supported board selected
583#endif /* CONFIG_TQM5200 */
584
585#if defined (CONFIG_BC3450)
586 } else if (line_number == 2) {
587 strcpy (info, " Dev: GERSYS BC3450");
588#endif /* CONFIG_BC3450 */
589 }
590 else {
591 info [0] = '\0';
592 }
593}
594#endif
595
596/*
597 * Returns SM501 register base address. First thing called in the
598 * driver. Checks if SM501 is physically present.
599 */
600unsigned int board_video_init (void)
601{
602 u16 save, tmp;
603 int restore, ret;
604
605 /*
606 * Check for Grafic Controller
607 */
608
609 /* save origianl FB content */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200610 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200611 restore = 1;
612
613 /* write test pattern to FB memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200615 __asm__ volatile ("sync");
616 /*
617 * Put a different pattern on the data lines: otherwise they may float
618 * long enough to read back what we wrote.
619 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200621 if (tmp == 0xA5A5)
622 puts ("!! possible error in grafic controller detection\n");
623
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200624 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200625 /* no grafic controller found */
626 restore = 0;
627 ret = 0;
628 } else {
629 ret = SM501_MMIO_BASE;
630 }
Wolfgang Denk610cf362006-05-03 01:24:04 +0200631
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200632 if (restore) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200634 __asm__ volatile ("sync");
635 }
636 return ret;
637}
638
639/*
640 * Returns SM501 framebuffer address
641 */
642unsigned int board_video_get_fb (void)
643{
644 return SM501_FB_BASE;
645}
646
647/*
648 * Called after initializing the SM501 and before clearing the screen.
649 */
650void board_validate_screen (unsigned int base)
651{
652}
653
654/*
655 * Return a pointer to the initialization sequence.
656 */
657const SMI_REGS *board_get_regs (void)
658{
659 return init_regs;
660}
661
662int board_get_width (void)
663{
664 return DISPLAY_WIDTH;
665}
666
667int board_get_height (void)
668{
669 return DISPLAY_HEIGHT;
670}
671
672#endif /* CONFIG_VIDEO_SM501 */
Ben Warren19403632008-08-31 10:03:22 -0700673
674int board_eth_init(bd_t *bis)
675{
Ben Warrene1d74802008-08-31 10:39:12 -0700676 cpu_eth_init(bis); /* Built in FEC comes first */
Ben Warren19403632008-08-31 10:03:22 -0700677 return pci_eth_init(bis);
678}