blob: 49655831585689ec3f3d241d346dc5de1979c96e [file] [log] [blame]
Tom Warren4e5ae092011-06-17 06:27:28 +00001/*
Allen Martin00a27492012-08-31 08:30:00 +00002 * NVIDIA Tegra20 GPIO handling.
Stephen Warrenfe828572015-09-25 10:44:08 -06003 * (C) Copyright 2010-2012,2015
Tom Warren4e5ae092011-06-17 06:27:28 +00004 * NVIDIA Corporation <www.nvidia.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Tom Warren4e5ae092011-06-17 06:27:28 +00007 */
8
9/*
10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
11 * Tom Warren (twarren@nvidia.com)
12 */
13
14#include <common.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060015#include <dm.h>
16#include <malloc.h>
17#include <errno.h>
18#include <fdtdec.h>
Tom Warren4e5ae092011-06-17 06:27:28 +000019#include <asm/io.h>
20#include <asm/bitops.h>
Tom Warren150c2492012-09-19 15:50:56 -070021#include <asm/arch/tegra.h>
Tom Warren4e5ae092011-06-17 06:27:28 +000022#include <asm/gpio.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060023#include <dm/device-internal.h>
Simon Glass838aa5c2015-01-05 20:05:33 -070024#include <dt-bindings/gpio/gpio.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060025
26DECLARE_GLOBAL_DATA_PTR;
Tom Warren4e5ae092011-06-17 06:27:28 +000027
Stephen Warrenfe828572015-09-25 10:44:08 -060028static const int CONFIG_SFIO = 0;
29static const int CONFIG_GPIO = 1;
30static const int DIRECTION_INPUT = 0;
31static const int DIRECTION_OUTPUT = 1;
32
Simon Glass2fccd2d2014-09-03 17:37:03 -060033struct tegra_gpio_platdata {
34 struct gpio_ctlr_bank *bank;
35 const char *port_name; /* Name of port, e.g. "B" */
36 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
37};
Tom Warren4e5ae092011-06-17 06:27:28 +000038
Simon Glass2fccd2d2014-09-03 17:37:03 -060039/* Information about each port at run-time */
40struct tegra_port_info {
Simon Glass2fccd2d2014-09-03 17:37:03 -060041 struct gpio_ctlr_bank *bank;
42 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
43};
Tom Warren4e5ae092011-06-17 06:27:28 +000044
Stephen Warrenfe828572015-09-25 10:44:08 -060045/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
Joe Hershberger365d6072011-11-11 15:55:36 -060046static int get_config(unsigned gpio)
Tom Warren4e5ae092011-06-17 06:27:28 +000047{
Joe Hershberger365d6072011-11-11 15:55:36 -060048 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
49 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000050 u32 u;
51 int type;
52
Joe Hershberger365d6072011-11-11 15:55:36 -060053 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
Stephen Warrenfe828572015-09-25 10:44:08 -060054 type = (u >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +000055
56 debug("get_config: port = %d, bit = %d is %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060057 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
Tom Warren4e5ae092011-06-17 06:27:28 +000058
Stephen Warrenfe828572015-09-25 10:44:08 -060059 return type ? CONFIG_GPIO : CONFIG_SFIO;
Tom Warren4e5ae092011-06-17 06:27:28 +000060}
61
Stephen Warrenfe828572015-09-25 10:44:08 -060062/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
Joe Hershberger365d6072011-11-11 15:55:36 -060063static void set_config(unsigned gpio, int type)
Tom Warren4e5ae092011-06-17 06:27:28 +000064{
Joe Hershberger365d6072011-11-11 15:55:36 -060065 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
66 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000067 u32 u;
68
69 debug("set_config: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060070 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
Tom Warren4e5ae092011-06-17 06:27:28 +000071
Joe Hershberger365d6072011-11-11 15:55:36 -060072 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
Stephen Warrenfe828572015-09-25 10:44:08 -060073 if (type != CONFIG_SFIO)
Joe Hershberger365d6072011-11-11 15:55:36 -060074 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +000075 else
Joe Hershberger365d6072011-11-11 15:55:36 -060076 u &= ~(1 << GPIO_BIT(gpio));
77 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +000078}
79
Joe Hershberger365d6072011-11-11 15:55:36 -060080/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
81static int get_direction(unsigned gpio)
Tom Warren4e5ae092011-06-17 06:27:28 +000082{
Joe Hershberger365d6072011-11-11 15:55:36 -060083 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
84 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000085 u32 u;
86 int dir;
87
Joe Hershberger365d6072011-11-11 15:55:36 -060088 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
89 dir = (u >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +000090
91 debug("get_direction: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060092 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
Tom Warren4e5ae092011-06-17 06:27:28 +000093
Stephen Warrenfe828572015-09-25 10:44:08 -060094 return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
Tom Warren4e5ae092011-06-17 06:27:28 +000095}
96
Joe Hershberger365d6072011-11-11 15:55:36 -060097/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
98static void set_direction(unsigned gpio, int output)
Tom Warren4e5ae092011-06-17 06:27:28 +000099{
Joe Hershberger365d6072011-11-11 15:55:36 -0600100 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
101 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +0000102 u32 u;
103
104 debug("set_direction: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -0600105 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
Tom Warren4e5ae092011-06-17 06:27:28 +0000106
Joe Hershberger365d6072011-11-11 15:55:36 -0600107 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
Stephen Warrenfe828572015-09-25 10:44:08 -0600108 if (output != DIRECTION_INPUT)
Joe Hershberger365d6072011-11-11 15:55:36 -0600109 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +0000110 else
Joe Hershberger365d6072011-11-11 15:55:36 -0600111 u &= ~(1 << GPIO_BIT(gpio));
112 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000113}
114
Joe Hershberger365d6072011-11-11 15:55:36 -0600115/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
116static void set_level(unsigned gpio, int high)
Tom Warren4e5ae092011-06-17 06:27:28 +0000117{
Joe Hershberger365d6072011-11-11 15:55:36 -0600118 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
119 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +0000120 u32 u;
121
122 debug("set_level: port = %d, bit %d == %d\n",
Joe Hershberger365d6072011-11-11 15:55:36 -0600123 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
Tom Warren4e5ae092011-06-17 06:27:28 +0000124
Joe Hershberger365d6072011-11-11 15:55:36 -0600125 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000126 if (high)
Joe Hershberger365d6072011-11-11 15:55:36 -0600127 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +0000128 else
Joe Hershberger365d6072011-11-11 15:55:36 -0600129 u &= ~(1 << GPIO_BIT(gpio));
130 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000131}
132
133/*
134 * Generic_GPIO primitives.
135 */
136
Joe Hershberger365d6072011-11-11 15:55:36 -0600137/* set GPIO pin 'gpio' as an input */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600138static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000139{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600140 struct tegra_port_info *state = dev_get_priv(dev);
Tom Warren4e5ae092011-06-17 06:27:28 +0000141
142 /* Configure GPIO direction as input. */
Stephen Warrenfe828572015-09-25 10:44:08 -0600143 set_direction(state->base_gpio + offset, DIRECTION_INPUT);
Tom Warren4e5ae092011-06-17 06:27:28 +0000144
Stephen Warren0c35e3a2015-09-23 12:13:00 -0600145 /* Enable the pin as a GPIO */
146 set_config(state->base_gpio + offset, 1);
147
Tom Warren4e5ae092011-06-17 06:27:28 +0000148 return 0;
149}
150
Joe Hershberger365d6072011-11-11 15:55:36 -0600151/* set GPIO pin 'gpio' as an output, with polarity 'value' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600152static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
153 int value)
Tom Warren4e5ae092011-06-17 06:27:28 +0000154{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600155 struct tegra_port_info *state = dev_get_priv(dev);
156 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000157
158 /* Configure GPIO output value. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600159 set_level(gpio, value);
Tom Warren4e5ae092011-06-17 06:27:28 +0000160
161 /* Configure GPIO direction as output. */
Stephen Warrenfe828572015-09-25 10:44:08 -0600162 set_direction(gpio, DIRECTION_OUTPUT);
Tom Warren4e5ae092011-06-17 06:27:28 +0000163
Stephen Warren0c35e3a2015-09-23 12:13:00 -0600164 /* Enable the pin as a GPIO */
165 set_config(state->base_gpio + offset, 1);
166
Tom Warren4e5ae092011-06-17 06:27:28 +0000167 return 0;
168}
169
Joe Hershberger365d6072011-11-11 15:55:36 -0600170/* read GPIO IN value of pin 'gpio' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600171static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000172{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600173 struct tegra_port_info *state = dev_get_priv(dev);
174 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000175 int val;
176
Simon Glass2fccd2d2014-09-03 17:37:03 -0600177 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
178 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
179
Simon Glass651827c2016-01-30 16:37:45 -0700180 if (get_direction(gpio) == DIRECTION_INPUT)
181 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
182 else
183 val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000184
Joe Hershberger365d6072011-11-11 15:55:36 -0600185 return (val >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +0000186}
187
Joe Hershberger365d6072011-11-11 15:55:36 -0600188/* write GPIO OUT value to pin 'gpio' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600189static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
Tom Warren4e5ae092011-06-17 06:27:28 +0000190{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600191 struct tegra_port_info *state = dev_get_priv(dev);
192 int gpio = state->base_gpio + offset;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600193
Tom Warren4e5ae092011-06-17 06:27:28 +0000194 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
Simon Glass2fccd2d2014-09-03 17:37:03 -0600195 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
Tom Warren4e5ae092011-06-17 06:27:28 +0000196
197 /* Configure GPIO output value. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600198 set_level(gpio, value);
199
200 return 0;
Tom Warren4e5ae092011-06-17 06:27:28 +0000201}
202
Stephen Warreneceb3f22014-04-22 14:37:53 -0600203void gpio_config_table(const struct tegra_gpio_config *config, int len)
204{
205 int i;
206
207 for (i = 0; i < len; i++) {
208 switch (config[i].init) {
209 case TEGRA_GPIO_INIT_IN:
Stephen Warrenfe828572015-09-25 10:44:08 -0600210 set_direction(config[i].gpio, DIRECTION_INPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600211 break;
212 case TEGRA_GPIO_INIT_OUT0:
Stephen Warrenf9d3cab2015-09-23 12:12:59 -0600213 set_level(config[i].gpio, 0);
Stephen Warrenfe828572015-09-25 10:44:08 -0600214 set_direction(config[i].gpio, DIRECTION_OUTPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600215 break;
216 case TEGRA_GPIO_INIT_OUT1:
Stephen Warrenf9d3cab2015-09-23 12:12:59 -0600217 set_level(config[i].gpio, 1);
Stephen Warrenfe828572015-09-25 10:44:08 -0600218 set_direction(config[i].gpio, DIRECTION_OUTPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600219 break;
220 }
Stephen Warrenfe828572015-09-25 10:44:08 -0600221 set_config(config[i].gpio, CONFIG_GPIO);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600222 }
223}
224
Simon Glass2fccd2d2014-09-03 17:37:03 -0600225static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000226{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600227 struct tegra_port_info *state = dev_get_priv(dev);
228 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000229
Simon Glass2fccd2d2014-09-03 17:37:03 -0600230 if (!get_config(gpio))
231 return GPIOF_FUNC;
232 else if (get_direction(gpio))
233 return GPIOF_OUTPUT;
234 else
235 return GPIOF_INPUT;
Tom Warren4e5ae092011-06-17 06:27:28 +0000236}
Simon Glass2fccd2d2014-09-03 17:37:03 -0600237
Simon Glass838aa5c2015-01-05 20:05:33 -0700238static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
Simon Glass3a571232017-05-18 20:09:18 -0600239 struct ofnode_phandle_args *args)
Simon Glass838aa5c2015-01-05 20:05:33 -0700240{
241 int gpio, port, ret;
242
243 gpio = args->args[0];
244 port = gpio / TEGRA_GPIOS_PER_PORT;
245 ret = device_get_child(dev, port, &desc->dev);
246 if (ret)
247 return ret;
248 desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
249 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
250
251 return 0;
252}
253
Simon Glass2fccd2d2014-09-03 17:37:03 -0600254static const struct dm_gpio_ops gpio_tegra_ops = {
Simon Glass2fccd2d2014-09-03 17:37:03 -0600255 .direction_input = tegra_gpio_direction_input,
256 .direction_output = tegra_gpio_direction_output,
257 .get_value = tegra_gpio_get_value,
258 .set_value = tegra_gpio_set_value,
259 .get_function = tegra_gpio_get_function,
Simon Glass838aa5c2015-01-05 20:05:33 -0700260 .xlate = tegra_gpio_xlate,
Simon Glass2fccd2d2014-09-03 17:37:03 -0600261};
262
263/**
264 * Returns the name of a GPIO port
265 *
266 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
267 *
268 * @base_port: Base port number (0, 1..n-1)
269 * @return allocated string containing the name
270 */
271static char *gpio_port_name(int base_port)
272{
273 char *name, *s;
274
275 name = malloc(3);
276 if (name) {
277 s = name;
278 *s++ = 'A' + (base_port % 26);
279 if (base_port >= 26)
280 *s++ = *name;
281 *s = '\0';
282 }
283
284 return name;
285}
286
287static const struct udevice_id tegra_gpio_ids[] = {
288 { .compatible = "nvidia,tegra30-gpio" },
289 { .compatible = "nvidia,tegra20-gpio" },
290 { }
291};
292
293static int gpio_tegra_probe(struct udevice *dev)
294{
Simon Glasse564f052015-03-05 12:25:20 -0700295 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass2fccd2d2014-09-03 17:37:03 -0600296 struct tegra_port_info *priv = dev->priv;
297 struct tegra_gpio_platdata *plat = dev->platdata;
298
299 /* Only child devices have ports */
300 if (!plat)
301 return 0;
302
303 priv->bank = plat->bank;
304 priv->base_gpio = plat->base_gpio;
305
306 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
307 uc_priv->bank_name = plat->port_name;
308
309 return 0;
310}
311
312/**
313 * We have a top-level GPIO device with no actual GPIOs. It has a child
314 * device for each Tegra port.
315 */
316static int gpio_tegra_bind(struct udevice *parent)
317{
318 struct tegra_gpio_platdata *plat = parent->platdata;
319 struct gpio_ctlr *ctlr;
320 int bank_count;
321 int bank;
322 int ret;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600323
324 /* If this is a child device, there is nothing to do here */
325 if (plat)
326 return 0;
327
Simon Glassbdfb3412015-03-03 08:02:59 -0700328 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
329#ifdef CONFIG_SPL_BUILD
330 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
331 bank_count = TEGRA_GPIO_BANKS;
332#else
333 {
334 int len;
335
Simon Glass2fccd2d2014-09-03 17:37:03 -0600336 /*
337 * This driver does not make use of interrupts, other than to figure
338 * out the number of GPIO banks
339 */
Simon Glass56f5c402017-07-25 08:30:03 -0600340 len = dev_read_size(parent, "interrupts");
341 if (len < 0)
342 return len;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600343 bank_count = len / 3 / sizeof(u32);
Simon Glass56f5c402017-07-25 08:30:03 -0600344 ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
345 if ((ulong)ctlr == FDT_ADDR_T_NONE)
346 return -EINVAL;
Simon Glassbdfb3412015-03-03 08:02:59 -0700347 }
348#endif
Simon Glass2fccd2d2014-09-03 17:37:03 -0600349 for (bank = 0; bank < bank_count; bank++) {
350 int port;
351
352 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
353 struct tegra_gpio_platdata *plat;
354 struct udevice *dev;
355 int base_port;
356
357 plat = calloc(1, sizeof(*plat));
358 if (!plat)
359 return -ENOMEM;
360 plat->bank = &ctlr->gpio_bank[bank];
361 base_port = bank * TEGRA_PORTS_PER_BANK + port;
362 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
363 plat->port_name = gpio_port_name(base_port);
364
365 ret = device_bind(parent, parent->driver,
366 plat->port_name, plat, -1, &dev);
367 if (ret)
368 return ret;
Simon Glasse160f7d2017-01-17 16:52:55 -0700369 dev_set_of_offset(dev, dev_of_offset(parent));
Simon Glass2fccd2d2014-09-03 17:37:03 -0600370 }
371 }
372
373 return 0;
374}
375
376U_BOOT_DRIVER(gpio_tegra) = {
377 .name = "gpio_tegra",
378 .id = UCLASS_GPIO,
379 .of_match = tegra_gpio_ids,
380 .bind = gpio_tegra_bind,
381 .probe = gpio_tegra_probe,
382 .priv_auto_alloc_size = sizeof(struct tegra_port_info),
383 .ops = &gpio_tegra_ops,
Simon Glassbdfb3412015-03-03 08:02:59 -0700384 .flags = DM_FLAG_PRE_RELOC,
Simon Glass2fccd2d2014-09-03 17:37:03 -0600385};