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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenkc837dcb2004-01-20 23:12:12 +00002 * (C) Copyright 2000-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite..
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00007 */
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_CRAYL1
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
20
21#define CONFIG_405GP 1 /* This is a PPC405 CPU */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022
23/*
24 * Note: I make an "image" from U-Boot itself, which prefixes 0x40
25 * bytes of header info, hence start address is thus shifted.
26 */
27#define CONFIG_SYS_TEXT_BASE 0xFFFD0040
28
wdenkc6097192002-11-03 00:24:07 +000029#define CONFIG_SYS_CLK_FREQ 25000000
30#define CONFIG_BAUDRATE 9600
31#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
Ben Warren96e21f82008-10-27 23:50:15 -070032
33#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000034#define CONFIG_MII 1 /* MII PHY management */
35#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
wdenkc837dcb2004-01-20 23:12:12 +000036#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */
wdenkc6097192002-11-03 00:24:07 +000037#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
38
Stefan Roese550650d2010-09-20 16:05:31 +020039#define CONFIG_CONS_INDEX 1 /* Use UART0 */
40#define CONFIG_SYS_NS16550
41#define CONFIG_SYS_NS16550_SERIAL
42#define CONFIG_SYS_NS16550_REG_SIZE 1
43#define CONFIG_SYS_NS16550_CLK get_serial_clock()
44
wdenkc6097192002-11-03 00:24:07 +000045/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
46 * keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
wdenk8bde7f72003-06-27 21:31:46 +000047 #define CONFIG_PRAM 16
wdenkc6097192002-11-03 00:24:07 +000048 */
wdenk7f70e852003-05-20 14:25:27 +000049#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */
wdenkc6097192002-11-03 00:24:07 +000050#undef CONFIG_BOOTARGS
51
wdenk7f70e852003-05-20 14:25:27 +000052/* Bootcmd is overridden by the bootscript in board/cray/L1
wdenkc6097192002-11-03 00:24:07 +000053 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_AUTOLOAD "no"
wdenk7f70e852003-05-20 14:25:27 +000055#define CONFIG_BOOTCOMMAND "dhcp"
wdenkc6097192002-11-03 00:24:07 +000056
wdenk8bde7f72003-06-27 21:31:46 +000057/*
wdenkc6097192002-11-03 00:24:07 +000058 * ..during experiments..
59 #define CONFIG_SERVERIP 10.0.0.1
wdenk8bde7f72003-06-27 21:31:46 +000060 #define CONFIG_ETHADDR 00:40:a6:80:14:5
wdenkc6097192002-11-03 00:24:07 +000061 */
Dirk Eibach880540d2013-04-25 02:40:01 +000062#define CONFIG_SYS_I2C
63#define CONFIG_SYS_I2C_PPC4XX
64#define CONFIG_SYS_I2C_PPC4XX_CH0
wdenk7f70e852003-05-20 14:25:27 +000065#define CONFIG_SDRAM_BANK0 1
Dirk Eibach880540d2013-04-25 02:40:01 +000066#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
67#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
69#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenkc6097192002-11-03 00:24:07 +000070#define CONFIG_IDENT_STRING "Cray L1"
71#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_HUSH_PARSER 1
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020073#define CONFIG_SOURCE 1
wdenkc6097192002-11-03 00:24:07 +000074
75
Jon Loeliger49cf7e82007-07-05 19:52:35 -050076/*
77 * Command line configuration.
78 */
79
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020080#define CONFIG_CMD_ASKENV
Jon Loeliger49cf7e82007-07-05 19:52:35 -050081#define CONFIG_CMD_BDI
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020082#define CONFIG_CMD_CONSOLE
83#define CONFIG_CMD_DATE
84#define CONFIG_CMD_DHCP
85#define CONFIG_CMD_DIAG
86#define CONFIG_CMD_ECHO
87#define CONFIG_CMD_EEPROM
Jon Loeliger49cf7e82007-07-05 19:52:35 -050088#define CONFIG_CMD_FLASH
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020089#define CONFIG_CMD_I2C
90#define CONFIG_CMD_IMI
91#define CONFIG_CMD_IMMAP
Jon Loeliger49cf7e82007-07-05 19:52:35 -050092#define CONFIG_CMD_MEMORY
93#define CONFIG_CMD_NET
Jon Loeliger49cf7e82007-07-05 19:52:35 -050094#define CONFIG_CMD_REGINFO
Jon Loeliger49cf7e82007-07-05 19:52:35 -050095#define CONFIG_CMD_RUN
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020096#define CONFIG_CMD_SAVEENV
Jon Loeliger49cf7e82007-07-05 19:52:35 -050097#define CONFIG_CMD_SETGETDCR
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020098#define CONFIG_CMD_SOURCE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050099
wdenkc6097192002-11-03 00:24:07 +0000100
101/*
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500102 * BOOTP options
wdenkc6097192002-11-03 00:24:07 +0000103 */
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107#define CONFIG_BOOTP_BOOTPATH
108#define CONFIG_BOOTP_VENDOREX
109#define CONFIG_BOOTP_DNS
110#define CONFIG_BOOTP_BOOTFILESIZE
111
wdenkc6097192002-11-03 00:24:07 +0000112
wdenk8bde7f72003-06-27 21:31:46 +0000113/*
wdenk7f70e852003-05-20 14:25:27 +0000114 * how many time to fail & restart a net-TFTP before giving up & resetting
115 * the board hoping that a reset of net interface might help..
116 */
117#define CONFIG_NET_RESET 5
118
wdenk8bde7f72003-06-27 21:31:46 +0000119/*
wdenkc6097192002-11-03 00:24:07 +0000120 * bauds. Just to make it compile; in our case, I read the base_baud
121 * from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
122 * drives the system clock.
123 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_BASE_BAUD 403225
125#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc6097192002-11-03 00:24:07 +0000126 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
127
wdenkc6097192002-11-03 00:24:07 +0000128/*
129 * Miscellaneous configurable options
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
132#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
133#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
134#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
wdenkc6097192002-11-03 00:24:07 +0000135
136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
139#define CONFIG_SYS_DRAM_TEST 1
wdenkc6097192002-11-03 00:24:07 +0000140
141/*-----------------------------------------------------------------------
142 * Start addresses for the final memory configuration
143 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_SDRAM_BASE 0x00000000
147#define CONFIG_SYS_FLASH_BASE 0xFFC00000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200148#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000149
wdenkc6097192002-11-03 00:24:07 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
wdenkc6097192002-11-03 00:24:07 +0000152
153/*
154 * For booting Linux, the board info and command line data
155 * have to be in the first 8 MB of memory, since this is
156 * the maximum mapped by the Linux kernel during initialization.
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000159/*-----------------------------------------------------------------------
160 * FLASH organization
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
163#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
164#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
165#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000166
167/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200168#define CONFIG_ENV_OFFSET 0x3c8000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200169#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200170#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment area */
171#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
wdenkc6097192002-11-03 00:24:07 +0000172
wdenk7f70e852003-05-20 14:25:27 +0000173/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
wdenkc6097192002-11-03 00:24:07 +0000174 * 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_SDRAM_SIZE 32 /* megs of ram */
177#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
wdenkc6097192002-11-03 00:24:07 +0000178 /* the exception vector table */
179 /* to the end of the DRAM */
180 /* less monitor and malloc area */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
182#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* 128k for malloc space */
183#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
184 + CONFIG_SYS_MALLOC_LEN \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200185 + CONFIG_ENV_SECT_SIZE \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 + CONFIG_SYS_STACK_USAGE )
wdenkc6097192002-11-03 00:24:07 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 - CONFIG_SYS_MEM_END_USAGE)
wdenkc6097192002-11-03 00:24:07 +0000189/* END ENVIRONNEMENT FLASH */
190
wdenkc6097192002-11-03 00:24:07 +0000191/*
192 * Init Memory Controller:
193 *
194 * BR0/1 and OR0/1 (FLASH)
195 */
196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000198
199
200/*-----------------------------------------------------------------------
201 * Definitions for initial stack pointer and data area (in OnChipMem )
202 */
wdenk7f70e852003-05-20 14:25:27 +0000203#if 1
204/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_TEMP_STACK_OCM 1
206#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
207#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenk7f70e852003-05-20 14:25:27 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200210#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200211#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7f70e852003-05-20 14:25:27 +0000213#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000
215#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
216#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200217#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of On Chip SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200218#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7f70e852003-05-20 14:25:27 +0000220#endif
wdenkc6097192002-11-03 00:24:07 +0000221
222/*-----------------------------------------------------------------------
223 * Definitions for Serial Presence Detect EEPROM address
224 */
225#define EEPROM_WRITE_ADDRESS 0xA0
226#define EEPROM_READ_ADDRESS 0xA1
227
wdenkc6097192002-11-03 00:24:07 +0000228#endif /* __CONFIG_H */