blob: a21afb7ac76973d49568716fe5f3fce7812cf457 [file] [log] [blame]
Poonam Aggrwal728ece32009-08-05 13:29:24 +05301/*
Haiying Wang96196a12010-11-10 15:37:13 -05002 * Copyright 2009-2010 Freescale Semiconductor, Inc.
Poonam Aggrwal728ece32009-08-05 13:29:24 +05303 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * P1 P2 RDB board configuration file
25 * This file is intended to address a set of Low End and Ultra Low End
26 * Freescale SOCs of QorIQ series(RDB platforms).
27 * Currently only P2020RDB
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020033#ifdef CONFIG_P1011RDB
Kumar Gala62ca21c2009-09-10 16:31:53 -050034#define CONFIG_P1011
35#endif
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020036#ifdef CONFIG_P1020RDB
Kumar Gala62ca21c2009-09-10 16:31:53 -050037#define CONFIG_P1020
38#endif
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020039#ifdef CONFIG_P2010RDB
Kumar Gala62ca21c2009-09-10 16:31:53 -050040#define CONFIG_P2010
41#endif
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020042#ifdef CONFIG_P2020RDB
Kumar Gala62ca21c2009-09-10 16:31:53 -050043#define CONFIG_P2020
44#endif
45
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020046#ifdef CONFIG_NAND
Dipen Dudhatf7780ec2009-10-08 13:33:18 +053047#define CONFIG_NAND_U_BOOT 1
48#define CONFIG_RAMBOOT_NAND 1
Haiying Wang96196a12010-11-10 15:37:13 -050049#ifdef CONFIG_NAND_SPL
50#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
51#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
52#else
Wolfgang Denk2ae18242010-10-06 09:05:45 +020053#define CONFIG_SYS_TEXT_BASE 0xf8f82000
Haiying Wang96196a12010-11-10 15:37:13 -050054#endif /* CONFIG_NAND_SPL */
Dipen Dudhatf7780ec2009-10-08 13:33:18 +053055#endif
56
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020057#ifdef CONFIG_SDCARD
Dipen Dudhatfad15092009-10-08 13:33:29 +053058#define CONFIG_RAMBOOT_SDCARD 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020059#define CONFIG_SYS_TEXT_BASE 0xf8f80000
Dipen Dudhatfad15092009-10-08 13:33:29 +053060#endif
61
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020062#ifdef CONFIG_SPIFLASH
Dipen Dudhatfad15092009-10-08 13:33:29 +053063#define CONFIG_RAMBOOT_SPIFLASH 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020064#define CONFIG_SYS_TEXT_BASE 0xf8f80000
65#endif
66
67#ifndef CONFIG_SYS_TEXT_BASE
68#define CONFIG_SYS_TEXT_BASE 0xeff80000
Dipen Dudhatfad15092009-10-08 13:33:29 +053069#endif
70
Haiying Wang96196a12010-11-10 15:37:13 -050071#ifndef CONFIG_SYS_MONITOR_BASE
72#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
73#endif
74
Poonam Aggrwal728ece32009-08-05 13:29:24 +053075/* High Level Configuration Options */
76#define CONFIG_BOOKE 1 /* BOOKE */
77#define CONFIG_E500 1 /* BOOKE e500 family */
78#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
79#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
Poonam Aggrwal33f3f342009-08-21 07:29:58 +053080#define CONFIG_PCI 1 /* Enable PCI/PCIE */
81#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
82#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
83#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
84#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
85#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Poonam Aggrwal728ece32009-08-05 13:29:24 +053086#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
87#define CONFIG_TSEC_ENET /* tsec ethernet support */
88#define CONFIG_ENV_OVERWRITE
89
Poonam Aggrwalddac6f02010-07-01 14:24:36 +053090#define CONFIG_E1000 1 /* E1000 pci Ethernet card*/
Poonam Aggrwal728ece32009-08-05 13:29:24 +053091#ifndef __ASSEMBLY__
92extern unsigned long get_board_sys_clk(unsigned long dummy);
93#endif
94#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1_P2 RDB */
95#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /*sysclk for P1_P2 RDB */
96
97#if defined(CONFIG_P2020) || defined(CONFIG_P1020)
98#define CONFIG_MP
99#endif
100
Poonam Aggrwal525f6c32010-06-23 19:38:06 +0530101#define CONFIG_HWCONFIG
102
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530103/*
104 * These can be toggled for performance analysis, otherwise use default.
105 */
106#define CONFIG_L2_CACHE /* toggle L2 cache */
107#define CONFIG_BTB /* toggle branch predition */
108
109#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
110
111#define CONFIG_ENABLE_36BIT_PHYS 1
112
113#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
114#define CONFIG_SYS_MEMTEST_END 0x1fffffff
115#define CONFIG_PANIC_HANG /* do not reset board on panic */
116
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530117 /*
118 * Config the L2 Cache as L2 SRAM
119 */
120#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
121#ifdef CONFIG_PHYS_64BIT
122#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
123#else
124#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
125#endif
126#define CONFIG_SYS_L2_SIZE (512 << 10)
127#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
128
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530129/*
130 * Base addresses -- Note these are effective addresses where the
131 * actual resources get mapped (not physical addresses)
132 */
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530133#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
134#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */
135 /* CCSRBAR */
136#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
137 /* CONFIG_SYS_IMMR */
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530138
139#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
140#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
141#else
142#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
143#endif
144
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530145/* DDR Setup */
146#define CONFIG_FSL_DDR2
147#undef CONFIG_FSL_DDR_INTERACTIVE
148#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
149#undef CONFIG_DDR_DLL
150
151#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
152
153#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR size on P1_P2 RDBs */
154#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
155#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
156
157#define CONFIG_NUM_DDR_CONTROLLERS 1
158#define CONFIG_DIMM_SLOTS_PER_CTLR 1
159#define CONFIG_CHIP_SELECTS_PER_CTRL 1
160
161#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
162#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
163#define CONFIG_SYS_DDR_SBE 0x00FF0000
164
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530165/*
166 * Memory map
167 *
168 * 0x0000_0000 0x3fff_ffff DDR 1G cacheablen
169 * 0xa000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
170 * 0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
171 *
172 * Localbus cacheable (TBD)
173 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
174 *
175 * Localbus non-cacheable
176 * 0xef00_0000 0xefff_ffff FLASH 16M non-cacheable
177 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
178 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
179 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
180 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
181 */
182
183/*
184 * Local Bus Definitions
185 */
186#define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */
187
188#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
189
190#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
191 BR_PS_16 | BR_V)
192#define CONFIG_FLASH_OR_PRELIM 0xff000ff7
193
194#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
195#define CONFIG_SYS_FLASH_QUIET_TEST
196#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
197
198#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
199#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
200#undef CONFIG_SYS_FLASH_CHECKSUM
201#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
202#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
203
Kumar Galaa55bb832010-11-29 14:32:11 -0600204#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
205 defined(CONFIG_RAMBOOT_SPIFLASH)
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530206#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600207#define CONFIG_SYS_EXTRA_ENV_RELOC
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530208#else
209#undef CONFIG_SYS_RAMBOOT
210#endif
211
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530212#define CONFIG_FLASH_CFI_DRIVER
213#define CONFIG_SYS_FLASH_CFI
214#define CONFIG_SYS_FLASH_EMPTY_INFO
215#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
216
217#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
Vivek Mahajan66e821e2010-01-07 14:27:14 +0530218#define CONFIG_HWCONFIG
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530219
220#define CONFIG_SYS_INIT_RAM_LOCK 1
221#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200222#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530223
Wolfgang Denk553f0982010-10-26 13:32:32 +0200224#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200225 - GENERATED_GBL_DATA_SIZE)
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530226#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
227
228#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
229#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
230
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530231#ifndef CONFIG_NAND_SPL
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530232#define CONFIG_SYS_NAND_BASE 0xffa00000
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530233#else
234#define CONFIG_SYS_NAND_BASE 0xfff00000
235#endif
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530236#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
237#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
238#define CONFIG_SYS_MAX_NAND_DEVICE 1
239#define NAND_MAX_CHIPS 1
240#define CONFIG_MTD_NAND_VERIFY_WRITE
241#define CONFIG_CMD_NAND 1
242#define CONFIG_NAND_FSL_ELBC 1
243#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
244
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530245/* NAND boot: 4K NAND loader config */
246#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
247#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
248#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
249#define CONFIG_SYS_NAND_U_BOOT_START (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
250#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
251#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
252#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
253
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530254/* NAND flash config */
255#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
256 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
257 | BR_PS_8 /* Port Size = 8 bit */ \
258 | BR_MS_FCM /* MSEL = FCM */ \
259 | BR_V) /* valid */
260
261#define CONFIG_NAND_OR_PRELIM (0xFFF80000 /* length 32K */ \
262 | OR_FCM_CSCT \
263 | OR_FCM_CST \
264 | OR_FCM_CHT \
265 | OR_FCM_SCY_1 \
266 | OR_FCM_TRLX \
267 | OR_FCM_EHTR)
268
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530269#ifdef CONFIG_RAMBOOT_NAND
270#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
271#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
272#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
273#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
274#else
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530275#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
276#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
277#define CONFIG_SYS_BR1_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
278#define CONFIG_SYS_OR1_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530279#endif
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530280
281#define CONFIG_SYS_VSC7385_BASE 0xffb00000
282
283#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
284
285#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V)
286#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
287 OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \
288 OR_GPCM_EHTR | OR_GPCM_EAD)
289
290/* Serial Port - controlled on board with jumper J8
291 * open - index 2
292 * shorted - index 1
293 */
294#define CONFIG_CONS_INDEX 1
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530295#define CONFIG_SYS_NS16550
296#define CONFIG_SYS_NS16550_SERIAL
297#define CONFIG_SYS_NS16550_REG_SIZE 1
298#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500299#ifdef CONFIG_NAND_SPL
300#define CONFIG_NS16550_MIN_FUNCTIONS
301#endif
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530302
303#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
304#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
305
306#define CONFIG_SYS_BAUDRATE_TABLE \
307 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
308
309#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
310#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
311
312/* Use the HUSH parser */
313#define CONFIG_SYS_HUSH_PARSER
314#ifdef CONFIG_SYS_HUSH_PARSER
315#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
316#endif
317
318/*
319 * Pass open firmware flat tree
320 */
321#define CONFIG_OF_LIBFDT 1
322#define CONFIG_OF_BOARD_SETUP 1
323#define CONFIG_OF_STDOUT_VIA_ALIAS 1
324
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530325/* new uImage format support */
326#define CONFIG_FIT 1
327#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
328
329/* I2C */
330#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
331#define CONFIG_HARD_I2C /* I2C with hardware support */
332#undef CONFIG_SOFT_I2C /* I2C bit-banged */
333#define CONFIG_I2C_MULTI_BUS
334#define CONFIG_I2C_CMD_TREE
335#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
336#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
337#define CONFIG_SYS_I2C_SLAVE 0x7F
338#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
339#define CONFIG_SYS_I2C_OFFSET 0x3000
340#define CONFIG_SYS_I2C2_OFFSET 0x3100
341
342/*
343 * I2C2 EEPROM
344 */
345#define CONFIG_ID_EEPROM
346#ifdef CONFIG_ID_EEPROM
347#define CONFIG_SYS_I2C_EEPROM_NXID
348#endif
349#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
350#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
351#define CONFIG_SYS_EEPROM_BUS_NUM 1
352
353#define CONFIG_RTC_DS1337
Priyanka Jain39c2a6e2010-10-25 14:52:53 +0530354#define CONFIG_SYS_RTC_DS1337_NOOSC
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530355#define CONFIG_SYS_I2C_RTC_ADDR 0x68
356/*
357 * General PCI
358 * Memory space is mapped 1-1, but I/O space must start from 0.
359 */
360
361/* controller 2, Slot 2, tgtid 2, Base address 9000 */
362#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
363#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
364#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
365#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
366#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
367#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
368#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
369#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
370
371/* controller 1, Slot 1, tgtid 1, Base address a000 */
372#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
373#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
374#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
375#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
376#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
377#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
378#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
379#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
380
381#if defined(CONFIG_PCI)
382#define CONFIG_NET_MULTI
383#define CONFIG_PCI_PNP /* do pci plug-and-play */
384
385#undef CONFIG_EEPRO100
386#undef CONFIG_TULIP
387#undef CONFIG_RTL8139
388
389#ifdef CONFIG_RTL8139
390/* This macro is used by RTL8139 but not defined in PPC architecture */
391#define KSEG1ADDR(x) (x)
392#define _IO_BASE 0x00000000
393#endif
394
395
396#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
397#define CONFIG_DOS_PARTITION
398
399#endif /* CONFIG_PCI */
400
401#if defined(CONFIG_TSEC_ENET)
402#ifndef CONFIG_NET_MULTI
403#define CONFIG_NET_MULTI 1
404#endif
405
406#define CONFIG_MII 1 /* MII PHY management */
407#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
408#define CONFIG_TSEC1 1
409#define CONFIG_TSEC1_NAME "eTSEC1"
410#define CONFIG_TSEC2 1
411#define CONFIG_TSEC2_NAME "eTSEC2"
412#define CONFIG_TSEC3 1
413#define CONFIG_TSEC3_NAME "eTSEC3"
414
415#define TSEC1_PHY_ADDR 2
416#define TSEC2_PHY_ADDR 0
417#define TSEC3_PHY_ADDR 1
418
419#define CONFIG_VSC7385_ENET
420
421#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
424
425#define TSEC1_PHYIDX 0
426#define TSEC2_PHYIDX 0
427#define TSEC3_PHYIDX 0
428
429/* Vitesse 7385 */
430
431#ifdef CONFIG_VSC7385_ENET
432/* The size of the VSC7385 firmware image */
433#define CONFIG_VSC7385_IMAGE_SIZE 8192
434#endif
435
436#define CONFIG_ETHPRIME "eTSEC1"
437
438#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Felix Radensky90b5bf22010-06-28 01:57:39 +0300439
440/* TBI PHY configuration for SGMII mode */
441#define CONFIG_TSEC_TBICR_SETTINGS ( \
442 TBICR_PHY_RESET \
443 | TBICR_ANEG_ENABLE \
444 | TBICR_FULL_DUPLEX \
445 | TBICR_SPEED1_SET \
446 )
447
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530448#endif /* CONFIG_TSEC_ENET */
449
450/*
451 * Environment
452 */
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530453#if defined(CONFIG_SYS_RAMBOOT)
454#if defined(CONFIG_RAMBOOT_NAND)
455 #define CONFIG_ENV_IS_IN_NAND 1
456 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
457 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Dipen Dudhatfad15092009-10-08 13:33:29 +0530458#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
459 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
460 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
461 #define CONFIG_ENV_SIZE 0x2000
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530462#endif
Dipen Dudhatf7780ec2009-10-08 13:33:18 +0530463#else
464 #define CONFIG_ENV_IS_IN_FLASH 1
465 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
466 #define CONFIG_ENV_ADDR 0xfff80000
467 #else
468 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
469 #endif
470 #define CONFIG_ENV_SIZE 0x2000
471 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
472#endif
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530473
474#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
475#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
476
477/*
478 * Command line configuration.
479 */
480#include <config_cmd_default.h>
481
482#define CONFIG_CMD_DATE
483#define CONFIG_CMD_ELF
484#define CONFIG_CMD_I2C
485#define CONFIG_CMD_IRQ
486#define CONFIG_CMD_MII
487#define CONFIG_CMD_PING
488#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500489#define CONFIG_CMD_REGINFO
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530490
491#if defined(CONFIG_PCI)
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530492#define CONFIG_CMD_NET
493#define CONFIG_CMD_PCI
494#endif
495
496#undef CONFIG_WATCHDOG /* watchdog disabled */
497
498#define CONFIG_MMC 1
499
500#ifdef CONFIG_MMC
501#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
502#define CONFIG_CMD_MMC
503#define CONFIG_DOS_PARTITION
504#define CONFIG_FSL_ESDHC
505#define CONFIG_GENERIC_MMC
506#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
507#ifdef CONFIG_P2020
508#define CONFIG_SYS_FSL_ESDHC_USE_PIO /* P2020 eSDHC DMA is not functional*/
509#endif
510#endif
511
512#define CONFIG_USB_EHCI
513
514#ifdef CONFIG_USB_EHCI
515#define CONFIG_CMD_USB
516#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
517#define CONFIG_USB_EHCI_FSL
518#define CONFIG_USB_STORAGE
519#endif
520
521#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
522#define CONFIG_CMD_EXT2
523#define CONFIG_CMD_FAT
524#define CONFIG_DOS_PARTITION
525#endif
526
527/*
528 * Miscellaneous configurable options
529 */
530#define CONFIG_SYS_LONGHELP /* undef to save memory */
531#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500532#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530533#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
534#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
535#if defined(CONFIG_CMD_KGDB)
536#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
537#else
538#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
539#endif
540#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
541 /* Print Buffer Size */
542#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
543#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
544#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
545
546/*
547 * For booting Linux, the board info and command line data
548 * have to be in the first 16 MB of memory, since this is
549 * the maximum mapped by the Linux kernel during initialization.
550 */
551#define CONFIG_SYS_BOOTMAPSZ (16 << 20)/* Initial Memory map for Linux*/
552
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530553#if defined(CONFIG_CMD_KGDB)
554#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
555#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
556#endif
557
558/*
559 * Environment Configuration
560 */
561
562#if defined(CONFIG_TSEC_ENET)
563#define CONFIG_HAS_ETH0
564#define CONFIG_HAS_ETH1
565#define CONFIG_HAS_ETH2
566#endif
567
568#define CONFIG_HOSTNAME P2020RDB
569#define CONFIG_ROOTPATH /opt/nfsroot
570#define CONFIG_BOOTFILE uImage
571#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
572
573/* default location for tftp and bootm */
574#define CONFIG_LOADADDR 1000000
575
576#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
577#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
578
579#define CONFIG_BAUDRATE 115200
580
581#define CONFIG_EXTRA_ENV_SETTINGS \
582 "netdev=eth0\0" \
583 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
584 "loadaddr=1000000\0" \
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530585 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200586 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
587 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
588 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
589 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
590 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Poonam Aggrwal728ece32009-08-05 13:29:24 +0530591 "consoledev=ttyS0\0" \
592 "ramdiskaddr=2000000\0" \
593 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
594 "fdtaddr=c00000\0" \
595 "fdtfile=p2020rdb.dtb\0" \
596 "bdev=sda1\0" \
597 "jffs2nor=mtdblock3\0" \
598 "norbootaddr=ef080000\0" \
599 "norfdtaddr=ef040000\0" \
600 "jffs2nand=mtdblock9\0" \
601 "nandbootaddr=100000\0" \
602 "nandfdtaddr=80000\0" \
603 "nandimgsize=400000\0" \
604 "nandfdtsize=80000\0" \
605 "usb_phy_type=ulpi\0" \
606 "vscfw_addr=ef000000\0" \
607 "othbootargs=ramdisk_size=600000\0" \
608 "usbfatboot=setenv bootargs root=/dev/ram rw " \
609 "console=$consoledev,$baudrate $othbootargs; " \
610 "usb start;" \
611 "fatload usb 0:2 $loadaddr $bootfile;" \
612 "fatload usb 0:2 $fdtaddr $fdtfile;" \
613 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
614 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
615 "usbext2boot=setenv bootargs root=/dev/ram rw " \
616 "console=$consoledev,$baudrate $othbootargs; " \
617 "usb start;" \
618 "ext2load usb 0:4 $loadaddr $bootfile;" \
619 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
620 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
621 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
622 "norboot=setenv bootargs root=/dev/$jffs2nor rw " \
623 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
624 "bootm $norbootaddr - $norfdtaddr\0" \
625 "nandboot=setenv bootargs root=/dev/$jffs2nand rw rootfstype=jffs2 " \
626 "console=$consoledev,$baudrate $othbootargs;" \
627 "nand read 2000000 $nandbootaddr $nandimgsize;" \
628 "nand read 3000000 $nandfdtaddr $nandfdtsize;" \
629 "bootm 2000000 - 3000000;\0"
630
631#define CONFIG_NFSBOOTCOMMAND \
632 "setenv bootargs root=/dev/nfs rw " \
633 "nfsroot=$serverip:$rootpath " \
634 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
635 "console=$consoledev,$baudrate $othbootargs;" \
636 "tftp $loadaddr $bootfile;" \
637 "tftp $fdtaddr $fdtfile;" \
638 "bootm $loadaddr - $fdtaddr"
639
640#define CONFIG_HDBOOT \
641 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
642 "console=$consoledev,$baudrate $othbootargs;" \
643 "usb start;" \
644 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
645 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
646 "bootm $loadaddr - $fdtaddr"
647
648#define CONFIG_RAMBOOTCOMMAND \
649 "setenv bootargs root=/dev/ram rw " \
650 "console=$consoledev,$baudrate $othbootargs; " \
651 "tftp $ramdiskaddr $ramdiskfile;" \
652 "tftp $loadaddr $bootfile;" \
653 "tftp $fdtaddr $fdtfile;" \
654 "bootm $loadaddr $ramdiskaddr $fdtaddr"
655
656#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
657
658#endif /* __CONFIG_H */