blob: 811033b0b83757815208dc88c2ab7b9ce165ad90 [file] [log] [blame]
Jon Loeliger7237c032006-10-19 11:02:16 -05001/*
Timur Tabi92477a62009-09-04 16:28:35 -05002 * Copyright 2006,2009 Freescale Semiconductor, Inc.
Jon Loeliger7237c032006-10-19 11:02:16 -05003 *
Heiko Schocher00f792e2012-10-24 13:48:22 +02004 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Changes for multibus/multiadapter I2C support.
6 *
Jon Loeliger7237c032006-10-19 11:02:16 -05007 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * Version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
Jon Loeliger7237c032006-10-19 11:02:16 -050022#include <common.h>
Jon Loeliger4d45f692006-10-19 12:02:24 -050023#include <command.h>
Jon Loeliger20476722006-10-20 15:50:15 -050024#include <i2c.h> /* Functional interface */
Jon Loeliger7237c032006-10-19 11:02:16 -050025#include <asm/io.h>
Jon Loeliger20476722006-10-20 15:50:15 -050026#include <asm/fsl_i2c.h> /* HW definitions */
Jon Loeliger7237c032006-10-19 11:02:16 -050027
Timur Tabi92477a62009-09-04 16:28:35 -050028/* The maximum number of microseconds we will wait until another master has
29 * released the bus. If not defined in the board header file, then use a
30 * generic value.
31 */
32#ifndef CONFIG_I2C_MBB_TIMEOUT
33#define CONFIG_I2C_MBB_TIMEOUT 100000
34#endif
35
36/* The maximum number of microseconds we will wait for a read or write
37 * operation to complete. If not defined in the board header file, then use a
38 * generic value.
39 */
40#ifndef CONFIG_I2C_TIMEOUT
41#define CONFIG_I2C_TIMEOUT 10000
42#endif
Jon Loeliger7237c032006-10-19 11:02:16 -050043
Joakim Tjernlund1939d962006-11-28 16:17:27 -060044#define I2C_READ_BIT 1
45#define I2C_WRITE_BIT 0
46
Timur Tabid8c82db2008-03-14 17:45:29 -050047DECLARE_GLOBAL_DATA_PTR;
48
Shengzhou Liua17fd102014-07-07 12:17:48 +080049static const struct fsl_i2c *i2c_dev[4] = {
Heiko Schocher00f792e2012-10-24 13:48:22 +020050 (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
51#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
Shengzhou Liua17fd102014-07-07 12:17:48 +080052 (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
53#endif
54#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
55 (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
56#endif
57#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
58 (struct fsl_i2c *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
Timur Tabibe5e6182006-11-03 19:15:00 -060059#endif
60};
Jon Loeliger7237c032006-10-19 11:02:16 -050061
Timur Tabid8c82db2008-03-14 17:45:29 -050062/* I2C speed map for a DFSR value of 1 */
63
64/*
65 * Map I2C frequency dividers to FDR and DFSR values
66 *
67 * This structure is used to define the elements of a table that maps I2C
68 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
69 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
70 * Sampling Rate (DFSR) registers.
71 *
72 * The actual table should be defined in the board file, and it must be called
73 * fsl_i2c_speed_map[].
74 *
75 * The last entry of the table must have a value of {-1, X}, where X is same
76 * FDR/DFSR values as the second-to-last entry. This guarantees that any
77 * search through the array will always find a match.
78 *
79 * The values of the divider must be in increasing numerical order, i.e.
80 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
81 *
82 * For this table, the values are based on a value of 1 for the DFSR
83 * register. See the application note AN2919 "Determining the I2C Frequency
84 * Divider Ratio for SCL"
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +060085 *
86 * ColdFire I2C frequency dividers for FDR values are different from
87 * PowerPC. The protocol to use the I2C module is still the same.
88 * A different table is defined and are based on MCF5xxx user manual.
89 *
Timur Tabid8c82db2008-03-14 17:45:29 -050090 */
91static const struct {
92 unsigned short divider;
Timur Tabid8c82db2008-03-14 17:45:29 -050093 u8 fdr;
94} fsl_i2c_speed_map[] = {
Joakim Tjernlund99404202009-09-17 11:07:17 +020095#ifdef __M68K__
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +060096 {20, 32}, {22, 33}, {24, 34}, {26, 35},
97 {28, 0}, {28, 36}, {30, 1}, {32, 37},
98 {34, 2}, {36, 38}, {40, 3}, {40, 39},
99 {44, 4}, {48, 5}, {48, 40}, {56, 6},
100 {56, 41}, {64, 42}, {68, 7}, {72, 43},
101 {80, 8}, {80, 44}, {88, 9}, {96, 41},
102 {104, 10}, {112, 42}, {128, 11}, {128, 43},
103 {144, 12}, {160, 13}, {160, 48}, {192, 14},
104 {192, 49}, {224, 50}, {240, 15}, {256, 51},
105 {288, 16}, {320, 17}, {320, 52}, {384, 18},
106 {384, 53}, {448, 54}, {480, 19}, {512, 55},
107 {576, 20}, {640, 21}, {640, 56}, {768, 22},
108 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
109 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
110 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
111 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
112 {-1, 31}
113#endif
Timur Tabid8c82db2008-03-14 17:45:29 -0500114};
115
116/**
117 * Set the I2C bus speed for a given I2C device
118 *
119 * @param dev: the I2C device
120 * @i2c_clk: I2C bus clock frequency
121 * @speed: the desired speed of the bus
122 *
123 * The I2C device must be stopped before calling this function.
124 *
125 * The return value is the actual bus speed that is set.
126 */
127static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev,
128 unsigned int i2c_clk, unsigned int speed)
129{
130 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1);
Timur Tabid8c82db2008-03-14 17:45:29 -0500131
132 /*
133 * We want to choose an FDR/DFSR that generates an I2C bus speed that
134 * is equal to or lower than the requested speed. That means that we
135 * want the first divider that is equal to or greater than the
136 * calculated divider.
137 */
Joakim Tjernlund99404202009-09-17 11:07:17 +0200138#ifdef __PPC__
139 u8 dfsr, fdr = 0x31; /* Default if no FDR found */
140 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
141 unsigned short a, b, ga, gb;
142 unsigned long c_div, est_div;
143
144#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
145 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
146#else
147 /* Condition 1: dfsr <= 50/T */
148 dfsr = (5 * (i2c_clk / 1000)) / 100000;
149#endif
150#ifdef CONFIG_FSL_I2C_CUSTOM_FDR
151 fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
152 speed = i2c_clk / divider; /* Fake something */
153#else
154 debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
155 if (!dfsr)
156 dfsr = 1;
157
158 est_div = ~0;
159 for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
160 for (gb = 0; gb < 8; gb++) {
161 b = 16 << gb;
162 c_div = b * (a + ((3*dfsr)/b)*2);
163 if ((c_div > divider) && (c_div < est_div)) {
164 unsigned short bin_gb, bin_ga;
165
166 est_div = c_div;
167 bin_gb = gb << 2;
168 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
169 fdr = bin_gb | bin_ga;
170 speed = i2c_clk / est_div;
171 debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
172 "a:%d, b:%d, speed:%d\n",
173 fdr, est_div, ga, gb, a, b, speed);
174 /* Condition 2 not accounted for */
175 debug("Tr <= %d ns\n",
176 (b - 3 * dfsr) * 1000000 /
177 (i2c_clk / 1000));
178 }
179 }
180 if (a == 20)
181 a += 2;
182 if (a == 24)
183 a += 4;
184 }
185 debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr);
186 debug("FDR:0x%.2x, speed:%d\n", fdr, speed);
187#endif
188 writeb(dfsr, &dev->dfsrr); /* set default filter */
189 writeb(fdr, &dev->fdr); /* set bus speed */
190#else
191 unsigned int i;
Timur Tabid8c82db2008-03-14 17:45:29 -0500192
193 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
194 if (fsl_i2c_speed_map[i].divider >= divider) {
TsiChung Liew5d9a5ef2008-08-19 00:56:46 +0600195 u8 fdr;
Joakim Tjernlund99404202009-09-17 11:07:17 +0200196
Joakim Tjernlundd01ee4d2009-09-17 11:07:16 +0200197 fdr = fsl_i2c_speed_map[i].fdr;
198 speed = i2c_clk / fsl_i2c_speed_map[i].divider;
Joakim Tjernlundd01ee4d2009-09-17 11:07:16 +0200199 writeb(fdr, &dev->fdr); /* set bus speed */
200
Timur Tabid8c82db2008-03-14 17:45:29 -0500201 break;
202 }
Joakim Tjernlund99404202009-09-17 11:07:17 +0200203#endif
Timur Tabid8c82db2008-03-14 17:45:29 -0500204 return speed;
205}
206
Kim Phillips62f730f2012-10-16 14:28:43 +0000207static unsigned int get_i2c_clock(int bus)
Jerry Huangc9a8b252011-10-26 15:29:38 +0000208{
209 if (bus)
Simon Glass609e6ec2012-12-13 20:48:49 +0000210 return gd->arch.i2c2_clk; /* I2C2 clock */
Jerry Huangc9a8b252011-10-26 15:29:38 +0000211 else
Simon Glass609e6ec2012-12-13 20:48:49 +0000212 return gd->arch.i2c1_clk; /* I2C1 clock */
Jerry Huangc9a8b252011-10-26 15:29:38 +0000213}
214
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800215static int fsl_i2c_fixup(const struct fsl_i2c *dev)
216{
217 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
218 unsigned long long timeval = 0;
219 int ret = -1;
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800220 unsigned int flags = 0;
221
222#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
223 unsigned int svr = get_svr();
224 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
225 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
226 flags = I2C_CR_BIT6;
227#endif
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800228
229 writeb(I2C_CR_MEN | I2C_CR_MSTA, &dev->cr);
230
231 timeval = get_ticks();
232 while (!(readb(&dev->sr) & I2C_SR_MBB)) {
233 if ((get_ticks() - timeval) > timeout)
234 goto err;
235 }
236
237 if (readb(&dev->sr) & I2C_SR_MAL) {
238 /* SDA is stuck low */
239 writeb(0, &dev->cr);
240 udelay(100);
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800241 writeb(I2C_CR_MSTA | flags, &dev->cr);
242 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &dev->cr);
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800243 }
244
245 readb(&dev->dr);
246
247 timeval = get_ticks();
248 while (!(readb(&dev->sr) & I2C_SR_MIF)) {
249 if ((get_ticks() - timeval) > timeout)
250 goto err;
251 }
252 ret = 0;
253
254err:
Chunhe Lan9c3f77e2013-08-16 15:10:37 +0800255 writeb(I2C_CR_MEN | flags, &dev->cr);
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800256 writeb(0, &dev->sr);
257 udelay(100);
258
259 return ret;
260}
261
Heiko Schocher00f792e2012-10-24 13:48:22 +0200262static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
Jon Loeliger7237c032006-10-19 11:02:16 -0500263{
Kumar Galaaa551212011-11-08 03:39:43 +0000264 const struct fsl_i2c *dev;
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800265 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
266 unsigned long long timeval;
Jon Loeliger7237c032006-10-19 11:02:16 -0500267
Heiko Schocher39df00d2009-07-09 12:04:26 +0200268#ifdef CONFIG_SYS_I2C_INIT_BOARD
Richard Retanubun26a33502010-04-12 15:08:17 -0400269 /* Call board specific i2c bus reset routine before accessing the
270 * environment, which might be in a chip on that bus. For details
271 * about this problem see doc/I2C_Edge_Conditions.
272 */
Heiko Schocher39df00d2009-07-09 12:04:26 +0200273 i2c_init_board();
274#endif
Heiko Schocher00f792e2012-10-24 13:48:22 +0200275 dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Jerry Huangc9a8b252011-10-26 15:29:38 +0000276
Heiko Schocher00f792e2012-10-24 13:48:22 +0200277 writeb(0, &dev->cr); /* stop I2C controller */
278 udelay(5); /* let it shutdown in peace */
279 set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
280 writeb(slaveadd << 1, &dev->adr);/* write slave address */
281 writeb(0x0, &dev->sr); /* clear status register */
282 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
Richard Retanubun26a33502010-04-12 15:08:17 -0400283
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800284 timeval = get_ticks();
285 while (readb(&dev->sr) & I2C_SR_MBB) {
286 if ((get_ticks() - timeval) < timeout)
287 continue;
288
289 if (fsl_i2c_fixup(dev))
290 debug("i2c_init: BUS#%d failed to init\n",
291 adap->hwadapnr);
292
293 break;
294 }
295
Richard Retanubun26a33502010-04-12 15:08:17 -0400296#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
297 /* Call board specific i2c bus reset routine AFTER the bus has been
298 * initialized. Use either this callpoint or i2c_init_board;
299 * which is called before i2c_init operations.
300 * For details about this problem see doc/I2C_Edge_Conditions.
301 */
302 i2c_board_late_init();
303#endif
Jon Loeliger7237c032006-10-19 11:02:16 -0500304}
305
Joakim Tjernlund21f4cbb2009-09-17 11:07:15 +0200306static int
Heiko Schocher00f792e2012-10-24 13:48:22 +0200307i2c_wait4bus(struct i2c_adapter *adap)
Jon Loeliger7237c032006-10-19 11:02:16 -0500308{
Heiko Schocher00f792e2012-10-24 13:48:22 +0200309 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Stefan Roesef2302d42008-08-06 14:05:38 +0200310 unsigned long long timeval = get_ticks();
Timur Tabi92477a62009-09-04 16:28:35 -0500311 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
Jon Loeliger7237c032006-10-19 11:02:16 -0500312
Heiko Schocher00f792e2012-10-24 13:48:22 +0200313 while (readb(&dev->sr) & I2C_SR_MBB) {
Timur Tabi92477a62009-09-04 16:28:35 -0500314 if ((get_ticks() - timeval) > timeout)
Jon Loeliger7237c032006-10-19 11:02:16 -0500315 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500316 }
317
318 return 0;
319}
320
321static __inline__ int
Heiko Schocher00f792e2012-10-24 13:48:22 +0200322i2c_wait(struct i2c_adapter *adap, int write)
Jon Loeliger7237c032006-10-19 11:02:16 -0500323{
324 u32 csr;
Stefan Roesef2302d42008-08-06 14:05:38 +0200325 unsigned long long timeval = get_ticks();
Timur Tabi92477a62009-09-04 16:28:35 -0500326 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
Heiko Schocher00f792e2012-10-24 13:48:22 +0200327 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Jon Loeliger7237c032006-10-19 11:02:16 -0500328
329 do {
Heiko Schocher00f792e2012-10-24 13:48:22 +0200330 csr = readb(&dev->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500331 if (!(csr & I2C_SR_MIF))
332 continue;
Joakim Tjernlund21f4cbb2009-09-17 11:07:15 +0200333 /* Read again to allow register to stabilise */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200334 csr = readb(&dev->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500335
Heiko Schocher00f792e2012-10-24 13:48:22 +0200336 writeb(0x0, &dev->sr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500337
338 if (csr & I2C_SR_MAL) {
339 debug("i2c_wait: MAL\n");
340 return -1;
341 }
342
343 if (!(csr & I2C_SR_MCF)) {
344 debug("i2c_wait: unfinished\n");
345 return -1;
346 }
347
Joakim Tjernlund1939d962006-11-28 16:17:27 -0600348 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
Jon Loeliger7237c032006-10-19 11:02:16 -0500349 debug("i2c_wait: No RXACK\n");
350 return -1;
351 }
352
353 return 0;
Timur Tabi92477a62009-09-04 16:28:35 -0500354 } while ((get_ticks() - timeval) < timeout);
Jon Loeliger7237c032006-10-19 11:02:16 -0500355
356 debug("i2c_wait: timed out\n");
357 return -1;
358}
359
360static __inline__ int
Heiko Schocher00f792e2012-10-24 13:48:22 +0200361i2c_write_addr(struct i2c_adapter *adap, u8 dev, u8 dir, int rsta)
Jon Loeliger7237c032006-10-19 11:02:16 -0500362{
Heiko Schocher00f792e2012-10-24 13:48:22 +0200363 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
364
Jon Loeliger7237c032006-10-19 11:02:16 -0500365 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
366 | (rsta ? I2C_CR_RSTA : 0),
Heiko Schocher00f792e2012-10-24 13:48:22 +0200367 &device->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500368
Heiko Schocher00f792e2012-10-24 13:48:22 +0200369 writeb((dev << 1) | dir, &device->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500370
Heiko Schocher00f792e2012-10-24 13:48:22 +0200371 if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500372 return 0;
373
374 return 1;
375}
376
377static __inline__ int
Heiko Schocher00f792e2012-10-24 13:48:22 +0200378__i2c_write(struct i2c_adapter *adap, u8 *data, int length)
Jon Loeliger7237c032006-10-19 11:02:16 -0500379{
Heiko Schocher00f792e2012-10-24 13:48:22 +0200380 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Jon Loeliger7237c032006-10-19 11:02:16 -0500381 int i;
382
Jon Loeliger7237c032006-10-19 11:02:16 -0500383 for (i = 0; i < length; i++) {
Heiko Schocher00f792e2012-10-24 13:48:22 +0200384 writeb(data[i], &dev->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500385
Heiko Schocher00f792e2012-10-24 13:48:22 +0200386 if (i2c_wait(adap, I2C_WRITE_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500387 break;
388 }
389
390 return i;
391}
392
393static __inline__ int
Heiko Schocher00f792e2012-10-24 13:48:22 +0200394__i2c_read(struct i2c_adapter *adap, u8 *data, int length)
Jon Loeliger7237c032006-10-19 11:02:16 -0500395{
Heiko Schocher00f792e2012-10-24 13:48:22 +0200396 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Jon Loeliger7237c032006-10-19 11:02:16 -0500397 int i;
398
399 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
Heiko Schocher00f792e2012-10-24 13:48:22 +0200400 &dev->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500401
402 /* dummy read */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200403 readb(&dev->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500404
405 for (i = 0; i < length; i++) {
Heiko Schocher00f792e2012-10-24 13:48:22 +0200406 if (i2c_wait(adap, I2C_READ_BIT) < 0)
Jon Loeliger7237c032006-10-19 11:02:16 -0500407 break;
408
409 /* Generate ack on last next to last byte */
410 if (i == length - 2)
411 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
Heiko Schocher00f792e2012-10-24 13:48:22 +0200412 &dev->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500413
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200414 /* Do not generate stop on last byte */
Jon Loeliger7237c032006-10-19 11:02:16 -0500415 if (i == length - 1)
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200416 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
Heiko Schocher00f792e2012-10-24 13:48:22 +0200417 &dev->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500418
Heiko Schocher00f792e2012-10-24 13:48:22 +0200419 data[i] = readb(&dev->dr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500420 }
421
422 return i;
423}
424
Heiko Schocher00f792e2012-10-24 13:48:22 +0200425static int
426fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data,
427 int length)
Jon Loeliger7237c032006-10-19 11:02:16 -0500428{
Heiko Schocher00f792e2012-10-24 13:48:22 +0200429 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100430 int i = -1; /* signal error */
Jon Loeliger7237c032006-10-19 11:02:16 -0500431 u8 *a = (u8*)&addr;
Shaveta Leekhaa4057642014-04-24 14:51:23 +0530432 int len = alen * -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500433
Heiko Schocher00f792e2012-10-24 13:48:22 +0200434 if (i2c_wait4bus(adap) < 0)
Reinhard Pfaub778c1b2013-06-26 15:55:14 +0200435 return -1;
436
Shaveta Leekhaa4057642014-04-24 14:51:23 +0530437 /* To handle the need of I2C devices that require to write few bytes
438 * (more than 4 bytes of address as in the case of else part)
439 * of data before reading, Negative equivalent of length(bytes to write)
440 * is passed, but used the +ve part of len for writing data
441 */
442 if (alen < 0) {
443 /* Generate a START and send the Address and
444 * the Tx Bytes to the slave.
445 * "START: Address: Write bytes data[len]"
446 * IF part supports writing any number of bytes in contrast
447 * to the else part, which supports writing address offset
448 * of upto 4 bytes only.
449 * bytes that need to be written are passed in
450 * "data", which will eventually keep the data READ,
451 * after writing the len bytes out of it
452 */
453 if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
454 i = __i2c_write(adap, data, len);
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100455
Shaveta Leekhaa4057642014-04-24 14:51:23 +0530456 if (i != len)
457 return -1;
458
459 if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
460 i = __i2c_read(adap, data, length);
461 } else {
462 if ((!length || alen > 0) &&
463 i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
464 __i2c_write(adap, &a[4 - alen], alen) == alen)
465 i = 0; /* No error so far */
466
467 if (length &&
468 i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
469 i = __i2c_read(adap, data, length);
470 }
Jon Loeliger7237c032006-10-19 11:02:16 -0500471
Heiko Schocher00f792e2012-10-24 13:48:22 +0200472 writeb(I2C_CR_MEN, &device->cr);
Jon Loeliger7237c032006-10-19 11:02:16 -0500473
Heiko Schocher00f792e2012-10-24 13:48:22 +0200474 if (i2c_wait4bus(adap)) /* Wait until STOP */
Joakim Tjernlundd1c9e5b2009-09-22 13:40:44 +0200475 debug("i2c_read: wait4bus timed out\n");
476
Jon Loeliger4d45f692006-10-19 12:02:24 -0500477 if (i == length)
478 return 0;
479
480 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500481}
482
Heiko Schocher00f792e2012-10-24 13:48:22 +0200483static int
484fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen,
485 u8 *data, int length)
Jon Loeliger7237c032006-10-19 11:02:16 -0500486{
Heiko Schocher00f792e2012-10-24 13:48:22 +0200487 struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100488 int i = -1; /* signal error */
Jon Loeliger7237c032006-10-19 11:02:16 -0500489 u8 *a = (u8*)&addr;
490
Chunhe Lanb8ce3342013-08-16 15:10:36 +0800491 if (i2c_wait4bus(adap) < 0)
492 return -1;
493
494 if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
Heiko Schocher00f792e2012-10-24 13:48:22 +0200495 __i2c_write(adap, &a[4 - alen], alen) == alen) {
496 i = __i2c_write(adap, data, length);
Jon Loeliger4d45f692006-10-19 12:02:24 -0500497 }
Jon Loeliger7237c032006-10-19 11:02:16 -0500498
Heiko Schocher00f792e2012-10-24 13:48:22 +0200499 writeb(I2C_CR_MEN, &device->cr);
500 if (i2c_wait4bus(adap)) /* Wait until STOP */
Joakim Tjernlund21f4cbb2009-09-17 11:07:15 +0200501 debug("i2c_write: wait4bus timed out\n");
Jon Loeliger7237c032006-10-19 11:02:16 -0500502
Jon Loeliger4d45f692006-10-19 12:02:24 -0500503 if (i == length)
504 return 0;
505
506 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500507}
508
Heiko Schocher00f792e2012-10-24 13:48:22 +0200509static int
510fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
Jon Loeliger7237c032006-10-19 11:02:16 -0500511{
Heiko Schocher00f792e2012-10-24 13:48:22 +0200512 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100513 /* For unknow reason the controller will ACK when
514 * probing for a slave with the same address, so skip
515 * it.
Jon Loeliger7237c032006-10-19 11:02:16 -0500516 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200517 if (chip == (readb(&dev->adr) >> 1))
Joakim Tjernlundf6f5f702007-01-31 11:04:19 +0100518 return -1;
Jon Loeliger7237c032006-10-19 11:02:16 -0500519
Heiko Schocher00f792e2012-10-24 13:48:22 +0200520 return fsl_i2c_read(adap, chip, 0, 0, NULL, 0);
Jon Loeliger7237c032006-10-19 11:02:16 -0500521}
522
Heiko Schocher00f792e2012-10-24 13:48:22 +0200523static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap,
524 unsigned int speed)
Timur Tabibe5e6182006-11-03 19:15:00 -0600525{
Heiko Schocher00f792e2012-10-24 13:48:22 +0200526 struct fsl_i2c *dev = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
Heiko Schocherc1bce4f2009-02-24 11:30:37 +0100527
Heiko Schocher00f792e2012-10-24 13:48:22 +0200528 writeb(0, &dev->cr); /* stop controller */
529 set_i2c_bus_speed(dev, get_i2c_clock(adap->hwadapnr), speed);
530 writeb(I2C_CR_MEN, &dev->cr); /* start controller */
Timur Tabid8c82db2008-03-14 17:45:29 -0500531
532 return 0;
Timur Tabibe5e6182006-11-03 19:15:00 -0600533}
534
Heiko Schocher00f792e2012-10-24 13:48:22 +0200535/*
536 * Register fsl i2c adapters
537 */
538U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
539 fsl_i2c_write, fsl_i2c_set_bus_speed,
540 CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
541 0)
542#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
543U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
544 fsl_i2c_write, fsl_i2c_set_bus_speed,
545 CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
546 1)
Heiko Schocherc1bce4f2009-02-24 11:30:37 +0100547#endif
Shengzhou Liua17fd102014-07-07 12:17:48 +0800548#ifdef CONFIG_SYS_FSL_I2C3_OFFSET
549U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
550 fsl_i2c_write, fsl_i2c_set_bus_speed,
551 CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
552 2)
553#endif
554#ifdef CONFIG_SYS_FSL_I2C4_OFFSET
555U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
556 fsl_i2c_write, fsl_i2c_set_bus_speed,
557 CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
558 3)
559#endif