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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 06713773da4ac3d390c63d82641eb553224b27c2 / . / include / ppc405.h
blob: 97528e88a829a5a91a566fda9d340bc7f0d22e11 [file] [log] [blame]
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1/*----------------------------------------------------------------------------+
2|
3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
9|
10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
13|
14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
17|
18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20+----------------------------------------------------------------------------*/
21
22#ifndef __PPC405_H__
23#define __PPC405_H__
24
25/*--------------------------------------------------------------------- */
26/* Special Purpose Registers */
27/*--------------------------------------------------------------------- */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]28 #define srr2 0x3de /* save/restore register 2 */
29 #define srr3 0x3df /* save/restore register 3 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +0200[diff] [blame]30
31 /*
32 * 405 does not really have CSRR0/1 but SRR2/3 are used during critical
33 * exception for the exact same purposes - let's alias them and have a
34 * common handling in crit_return() and CRIT_EXCEPTION
35 */
36 #define csrr0 srr2
37 #define csrr1 srr3
38
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]39 #define dbsr 0x3f0 /* debug status register */
40 #define dbcr0 0x3f2 /* debug control register 0 */
41 #define dbcr1 0x3bd /* debug control register 1 */
42 #define iac1 0x3f4 /* instruction address comparator 1 */
43 #define iac2 0x3f5 /* instruction address comparator 2 */
44 #define iac3 0x3b4 /* instruction address comparator 3 */
45 #define iac4 0x3b5 /* instruction address comparator 4 */
46 #define dac1 0x3f6 /* data address comparator 1 */
47 #define dac2 0x3f7 /* data address comparator 2 */
48 #define dccr 0x3fa /* data cache control register */
49 #define iccr 0x3fb /* instruction cache control register */
50 #define esr 0x3d4 /* execption syndrome register */
51 #define dear 0x3d5 /* data exeption address register */
52 #define evpr 0x3d6 /* exeption vector prefix register */
53 #define tsr 0x3d8 /* timer status register */
54 #define tcr 0x3da /* timer control register */
55 #define pit 0x3db /* programmable interval timer */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]56 #define sgr 0x3b9 /* storage guarded reg */
57 #define dcwr 0x3ba /* data cache write-thru reg*/
58 #define sler 0x3bb /* storage little-endian reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]59 #define cdbcr 0x3d7 /* cache debug cntrl reg */
60 #define icdbdr 0x3d3 /* instr cache dbug data reg*/
61 #define ccr0 0x3b3 /* core configuration register */
62 #define dvc1 0x3b6 /* data value compare register 1 */
63 #define dvc2 0x3b7 /* data value compare register 2 */
64 #define pid 0x3b1 /* process ID */
65 #define su0r 0x3bc /* storage user-defined register 0 */
66 #define zpr 0x3b0 /* zone protection regsiter */
67
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]68 #define tbl 0x11c /* time base lower - privileged write */
69 #define tbu 0x11d /* time base upper - privileged write */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]70
71 #define sprg4r 0x104 /* Special purpose general 4 - read only */
72 #define sprg5r 0x105 /* Special purpose general 5 - read only */
73 #define sprg6r 0x106 /* Special purpose general 6 - read only */
74 #define sprg7r 0x107 /* Special purpose general 7 - read only */
75 #define sprg4w 0x114 /* Special purpose general 4 - write only */
76 #define sprg5w 0x115 /* Special purpose general 5 - write only */
77 #define sprg6w 0x116 /* Special purpose general 6 - write only */
78 #define sprg7w 0x117 /* Special purpose general 7 - write only */
79
80/******************************************************************************
81 * Special for PPC405GP
82 ******************************************************************************/
83
84/******************************************************************************
85 * DMA
86 ******************************************************************************/
87#define DMA_DCR_BASE 0x100
88#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
89#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
90#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
91#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
92#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
93#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
94#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
95#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
96#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
97#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
98#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
99#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
100#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
101#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
102#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
103#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
104#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
105#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
106#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
107#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
108#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
109#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
110#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
111
112/******************************************************************************
113 * Universal interrupt controller
114 ******************************************************************************/
115#define UIC_DCR_BASE 0xc0
116#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
117#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
118#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
119#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
120#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
121#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
122#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
123#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
124#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
125
Stefan Roesedbbd1252007-10-05 17:10:59 +0200[diff] [blame]126#if defined(CONFIG_405EX)
127#define uic0sr uicsr /* UIC status */
128#define uic0srs uicsrs /* UIC status set */
129#define uic0er uicer /* UIC enable */
130#define uic0cr uiccr /* UIC critical */
131#define uic0pr uicpr /* UIC polarity */
132#define uic0tr uictr /* UIC triggering */
133#define uic0msr uicmsr /* UIC masked status */
134#define uic0vr uicvr /* UIC vector */
135#define uic0vcr uicvcr /* UIC vector configuration*/
136
137#define UIC_DCR_BASE1 0xd0
138#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
139#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
140#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
141#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */
142#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */
143#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */
144#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */
145#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */
146#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
147
148#define UIC_DCR_BASE2 0xe0
149#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
150#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
151#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
152#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */
153#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */
154#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */
155#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */
156#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */
157#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/
158#endif
159
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]160/*-----------------------------------------------------------------------------+
161| Universal interrupt controller interrupts
162+-----------------------------------------------------------------------------*/
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]163#if defined(CONFIG_405EZ)
164#define UIC_DMA0 0x80000000 /* DMA chan. 0 */
165#define UIC_DMA1 0x40000000 /* DMA chan. 1 */
166#define UIC_DMA2 0x20000000 /* DMA chan. 2 */
167#define UIC_DMA3 0x10000000 /* DMA chan. 3 */
168#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
169#define UIC_UART0 0x04000000 /* UART 0 */
170#define UIC_UART1 0x02000000 /* UART 1 */
171#define UIC_CAN0 0x01000000 /* CAN 0 */
172#define UIC_CAN1 0x00800000 /* CAN 1 */
173#define UIC_SPI 0x00400000 /* SPI */
174#define UIC_IIC 0x00200000 /* IIC */
175#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
176#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
177#define UIC_USBH1 0x00040000 /* USB Host 1 */
178#define UIC_USBH2 0x00020000 /* USB Host 2 */
179#define UIC_USBDEV 0x00010000 /* USB Device */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]180#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
181#define UIC_ENET1 0x00008000 /* dummy define */
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]182#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
183
184#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]185#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]186#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
187#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
188
189#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
190#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
191#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
192#define UIC_NAND 0x00000200 /* NAND Flash controller */
193#define UIC_ADC 0x00000100 /* ADC */
194#define UIC_DAC 0x00000080 /* DAC */
195#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
196#define UIC_RESERVED0 0x00000020 /* Reserved */
197#define UIC_EXT0 0x00000010 /* External interrupt 0 */
198#define UIC_EXT1 0x00000008 /* External interrupt 1 */
199#define UIC_EXT2 0x00000004 /* External interrupt 2 */
200#define UIC_EXT3 0x00000002 /* External interrupt 3 */
201#define UIC_EXT4 0x00000001 /* External interrupt 4 */
202
Stefan Roesedbbd1252007-10-05 17:10:59 +0200[diff] [blame]203#elif defined(CONFIG_405EX)
204
205/* UIC 0 */
206#define UIC_U0 0x80000000 /* */
207#define UIC_U1 0x40000000 /* */
208#define UIC_IIC0 0x20000000 /* */
209#define UIC_PKA 0x10000000 /* */
210#define UIC_TRNG 0x08000000 /* */
211#define UIC_EBM 0x04000000 /* */
212#define UIC_BGI 0x02000000 /* */
213#define UIC_IIC1 0x01000000 /* */
214#define UIC_SPI 0x00800000 /* */
215#define UIC_EIRQ0 0x00400000 /**/
216#define UIC_MTE 0x00200000 /*MAL Tx EOB */
217#define UIC_MRE 0x00100000 /*MAL Rx EOB */
218#define UIC_DMA0 0x00080000 /* */
219#define UIC_DMA1 0x00040000 /* */
220#define UIC_DMA2 0x00020000 /* */
221#define UIC_DMA3 0x00010000 /* */
222#define UIC_PCIE0AL 0x00008000 /* */
223#define UIC_PCIE0VPD 0x00004000 /* */
224#define UIC_RPCIE0HRST 0x00002000 /* */
225#define UIC_FPCIE0HRST 0x00001000 /* */
226#define UIC_PCIE0TCR 0x00000800 /* */
227#define UIC_PCIEMSI0 0x00000400 /* */
228#define UIC_PCIEMSI1 0x00000200 /* */
229#define UIC_SECURITY 0x00000100 /* */
230#define UIC_ENET 0x00000080 /* */
231#define UIC_ENET1 0x00000040 /* */
232#define UIC_PCIEMSI2 0x00000020 /* */
233#define UIC_EIRQ4 0x00000010 /**/
234#define UIC_UIC2NC 0x00000008 /* */
235#define UIC_UIC2C 0x00000004 /* */
236#define UIC_UIC1NC 0x00000002 /* */
237#define UIC_UIC1C 0x00000001 /* */
238
239#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
240#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
241/* UIC 1 */
242#define UIC_MS 0x80000000 /* MAL SERR */
243#define UIC_MTDE 0x40000000 /* MAL TXDE */
244#define UIC_MRDE 0x20000000 /* MAL RXDE */
245#define UIC_PCIE0BMVC0 0x10000000 /* */
246#define UIC_PCIE0DCRERR 0x08000000 /* */
247#define UIC_EBC 0x04000000 /* */
248#define UIC_NDFC 0x02000000 /* */
249#define UIC_PCEI1DCRERR 0x01000000 /* */
250#define UIC_GPTCMPT8 0x00800000 /* */
251#define UIC_GPTCMPT9 0x00400000 /* */
252#define UIC_PCIE1AL 0x00200000 /* */
253#define UIC_PCIE1VPD 0x00100000 /* */
254#define UIC_RPCE1HRST 0x00080000 /* */
255#define UIC_FPCE1HRST 0x00040000 /* */
256#define UIC_PCIE1TCR 0x00020000 /* */
257#define UIC_PCIE1VC0 0x00010000 /* */
258#define UIC_GPTCMPT3 0x00008000 /* */
259#define UIC_GPTCMPT4 0x00004000 /* */
260#define UIC_EIRQ7 0x00002000 /* */
261#define UIC_EIRQ8 0x00001000 /* */
262#define UIC_EIRQ9 0x00000800 /* */
263#define UIC_GPTCMP5 0x00000400 /* */
264#define UIC_GPTCMP6 0x00000200 /* */
265#define UIC_GPTCMP7 0x00000100 /* */
266#define UIC_SROM 0x00000080 /* SERIAL ROM*/
267#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/
268#define UIC_EIRQ2 0x00000020 /* */
269#define UIC_EIRQ5 0x00000010 /* */
270#define UIC_EIRQ6 0x00000008 /* */
271#define UIC_EMAC0WAKE 0x00000004 /* */
272#define UIC_EIRQ1 0x00000002 /* */
273#define UIC_EMAC1WAKE 0x00000001 /* */
274#define UIC_MAL_SERR UIC_MS /* MAL SERR */
275#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */
276#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */
277/* UIC 2 */
278#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/
279#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/
280#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/
281#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/
282#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/
283#define UIC_DDRMCUE 0x04000000 /* */
284#define UIC_DDRMCCE 0x02000000 /* */
285#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/
286#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/
287#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/
288#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/
289#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/
290#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/
291#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/
292#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/
293#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/
294#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/
295#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/
296#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/
297#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/
298#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/
299#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/
300#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/
301#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/
302#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/
303#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/
304#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/
305#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/
306#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/
307#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/
308#define UIC_USBWAKE 0x00000002 /* USB wakup*/
309#define UIC_USBOTG 0x00000001 /* USB OTG*/
310#define UIC_ETH0 UIC_ENET
311#define UIC_ETH1 UIC_ENET1
312
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]313#else /* !defined(CONFIG_405EZ) */
314
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]315#define UIC_UART0 0x80000000 /* UART 0 */
316#define UIC_UART1 0x40000000 /* UART 1 */
317#define UIC_IIC 0x20000000 /* IIC */
318#define UIC_EXT_MAST 0x10000000 /* External Master */
319#define UIC_PCI 0x08000000 /* PCI write to command reg */
320#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
321#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
322#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
323#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
324#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
325#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
326#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
327#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
328#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
329#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
wdenkcea655a2004-06-06 23:53:59 +0000[diff] [blame]330#define UIC_ENET 0x00010000 /* Ethernet0 */
331#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */
332#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]333#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]334#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
335#define UIC_EXT0 0x00000040 /* External interrupt 0 */
336#define UIC_EXT1 0x00000020 /* External interrupt 1 */
337#define UIC_EXT2 0x00000010 /* External interrupt 2 */
338#define UIC_EXT3 0x00000008 /* External interrupt 3 */
339#define UIC_EXT4 0x00000004 /* External interrupt 4 */
340#define UIC_EXT5 0x00000002 /* External interrupt 5 */
341#define UIC_EXT6 0x00000001 /* External interrupt 6 */
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]342#endif /* defined(CONFIG_405EZ) */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]343
344/******************************************************************************
345 * SDRAM Controller
346 ******************************************************************************/
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]347 /* values for memcfga register - indirect addressing of these regs */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]348#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]349 #define mem_besra 0x00 /* bus error syndrome reg a */
350 #define mem_besrsa 0x04 /* bus error syndrome reg set a */
351 #define mem_besrb 0x08 /* bus error syndrome reg b */
352 #define mem_besrsb 0x0c /* bus error syndrome reg set b */
353 #define mem_bear 0x10 /* bus error address reg */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]354#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]355 #define mem_mcopt1 0x20 /* memory controller options 1 */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100[diff] [blame]356 #define mem_status 0x24 /* memory status */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]357 #define mem_rtr 0x30 /* refresh timer reg */
358 #define mem_pmit 0x34 /* power management idle timer */
359 #define mem_mb0cf 0x40 /* memory bank 0 configuration */
360 #define mem_mb1cf 0x44 /* memory bank 1 configuration */
stroesee075fbe2003-12-09 14:59:11 +0000[diff] [blame]361#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]362 #define mem_mb2cf 0x48 /* memory bank 2 configuration */
363 #define mem_mb3cf 0x4c /* memory bank 3 configuration */
stroesee075fbe2003-12-09 14:59:11 +0000[diff] [blame]364#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]365 #define mem_sdtr1 0x80 /* timing reg 1 */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]366#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]367 #define mem_ecccf 0x94 /* ECC configuration */
368 #define mem_eccerr 0x98 /* ECC error status */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]369#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]370
stroesee075fbe2003-12-09 14:59:11 +0000[diff] [blame]371#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]372/******************************************************************************
373 * Decompression Controller
374 ******************************************************************************/
375#define DECOMP_DCR_BASE 0x14
376#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
377#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
378 /* values for kiar register - indirect addressing of these regs */
379 #define kitor0 0x00 /* index table origin register 0 */
380 #define kitor1 0x01 /* index table origin register 1 */
381 #define kitor2 0x02 /* index table origin register 2 */
382 #define kitor3 0x03 /* index table origin register 3 */
383 #define kaddr0 0x04 /* address decode definition regsiter 0 */
384 #define kaddr1 0x05 /* address decode definition regsiter 1 */
385 #define kconf 0x40 /* decompression core config register */
386 #define kid 0x41 /* decompression core ID register */
387 #define kver 0x42 /* decompression core version # reg */
388 #define kpear 0x50 /* bus error addr reg (PLB addr) */
389 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
390 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
391 #define kesr0s 0x53 /* bus error status reg 0 (set) */
392 /* There are 0x400 of the following registers, from krom0 to krom3ff*/
393 /* Only the first one is given here. */
394 #define krom0 0x400 /* SRAM/ROM read/write */
stroesee075fbe2003-12-09 14:59:11 +0000[diff] [blame]395#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]396
397/******************************************************************************
398 * Power Management
399 ******************************************************************************/
Stefan Roesedbbd1252007-10-05 17:10:59 +0200[diff] [blame]400#ifdef CONFIG_405EX
401#define POWERMAN_DCR_BASE 0xb0
402#else
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]403#define POWERMAN_DCR_BASE 0xb8
Stefan Roesedbbd1252007-10-05 17:10:59 +0200[diff] [blame]404#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]405#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
406#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
407#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
408
409/******************************************************************************
410 * Extrnal Bus Controller
411 ******************************************************************************/
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]412 /* values for ebccfga register - indirect addressing of these regs */
413 #define pb0cr 0x00 /* periph bank 0 config reg */
414 #define pb1cr 0x01 /* periph bank 1 config reg */
415 #define pb2cr 0x02 /* periph bank 2 config reg */
416 #define pb3cr 0x03 /* periph bank 3 config reg */
417 #define pb4cr 0x04 /* periph bank 4 config reg */
stroesee075fbe2003-12-09 14:59:11 +0000[diff] [blame]418#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]419 #define pb5cr 0x05 /* periph bank 5 config reg */
420 #define pb6cr 0x06 /* periph bank 6 config reg */
421 #define pb7cr 0x07 /* periph bank 7 config reg */
stroesee075fbe2003-12-09 14:59:11 +0000[diff] [blame]422#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]423 #define pb0ap 0x10 /* periph bank 0 access parameters */
424 #define pb1ap 0x11 /* periph bank 1 access parameters */
425 #define pb2ap 0x12 /* periph bank 2 access parameters */
426 #define pb3ap 0x13 /* periph bank 3 access parameters */
427 #define pb4ap 0x14 /* periph bank 4 access parameters */
stroesee075fbe2003-12-09 14:59:11 +0000[diff] [blame]428#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]429 #define pb5ap 0x15 /* periph bank 5 access parameters */
430 #define pb6ap 0x16 /* periph bank 6 access parameters */
431 #define pb7ap 0x17 /* periph bank 7 access parameters */
stroesee075fbe2003-12-09 14:59:11 +0000[diff] [blame]432#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]433 #define pbear 0x20 /* periph bus error addr reg */
434 #define pbesr0 0x21 /* periph bus error status reg 0 */
435 #define pbesr1 0x22 /* periph bus error status reg 1 */
436 #define epcr 0x23 /* external periph control reg */
Stefan Roese4745aca2007-02-20 10:57:08 +0100[diff] [blame]437#define EBC0_CFG 0x23 /* external bus configuration reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]438
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]439#ifdef CONFIG_405EP
440/******************************************************************************
441 * Control
442 ******************************************************************************/
443#define CNTRL_DCR_BASE 0x0f0
444#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
445#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
446#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
447#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
448#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
449#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
450
451#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
452#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
453#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
454#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
455#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
456#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
457#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
458#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
459#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
460#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
461
462/* Bit definitions */
463#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
464#define PLLMR0_CPU_DIV_BYPASS 0x00000000
465#define PLLMR0_CPU_DIV_2 0x00100000
466#define PLLMR0_CPU_DIV_3 0x00200000
467#define PLLMR0_CPU_DIV_4 0x00300000
468
469#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
470#define PLLMR0_CPU_PLB_DIV_1 0x00000000
471#define PLLMR0_CPU_PLB_DIV_2 0x00010000
472#define PLLMR0_CPU_PLB_DIV_3 0x00020000
473#define PLLMR0_CPU_PLB_DIV_4 0x00030000
474
475#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
476#define PLLMR0_OPB_PLB_DIV_1 0x00000000
477#define PLLMR0_OPB_PLB_DIV_2 0x00001000
478#define PLLMR0_OPB_PLB_DIV_3 0x00002000
479#define PLLMR0_OPB_PLB_DIV_4 0x00003000
480
481#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
482#define PLLMR0_EXB_PLB_DIV_2 0x00000000
483#define PLLMR0_EXB_PLB_DIV_3 0x00000100
484#define PLLMR0_EXB_PLB_DIV_4 0x00000200
485#define PLLMR0_EXB_PLB_DIV_5 0x00000300
486
487#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
488#define PLLMR0_MAL_PLB_DIV_1 0x00000000
489#define PLLMR0_MAL_PLB_DIV_2 0x00000010
490#define PLLMR0_MAL_PLB_DIV_3 0x00000020
491#define PLLMR0_MAL_PLB_DIV_4 0x00000030
492
493#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
494#define PLLMR0_PCI_PLB_DIV_1 0x00000000
495#define PLLMR0_PCI_PLB_DIV_2 0x00000001
496#define PLLMR0_PCI_PLB_DIV_3 0x00000002
497#define PLLMR0_PCI_PLB_DIV_4 0x00000003
498
499#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
500#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
501#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
502#define PLLMR1_FBMUL_DIV_16 0x00000000
503#define PLLMR1_FBMUL_DIV_1 0x00100000
504#define PLLMR1_FBMUL_DIV_2 0x00200000
505#define PLLMR1_FBMUL_DIV_3 0x00300000
506#define PLLMR1_FBMUL_DIV_4 0x00400000
507#define PLLMR1_FBMUL_DIV_5 0x00500000
508#define PLLMR1_FBMUL_DIV_6 0x00600000
509#define PLLMR1_FBMUL_DIV_7 0x00700000
510#define PLLMR1_FBMUL_DIV_8 0x00800000
511#define PLLMR1_FBMUL_DIV_9 0x00900000
512#define PLLMR1_FBMUL_DIV_10 0x00A00000
513#define PLLMR1_FBMUL_DIV_11 0x00B00000
514#define PLLMR1_FBMUL_DIV_12 0x00C00000
515#define PLLMR1_FBMUL_DIV_13 0x00D00000
516#define PLLMR1_FBMUL_DIV_14 0x00E00000
517#define PLLMR1_FBMUL_DIV_15 0x00F00000
518
519#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
520#define PLLMR1_FWDVA_DIV_8 0x00000000
521#define PLLMR1_FWDVA_DIV_7 0x00010000
522#define PLLMR1_FWDVA_DIV_6 0x00020000
523#define PLLMR1_FWDVA_DIV_5 0x00030000
524#define PLLMR1_FWDVA_DIV_4 0x00040000
525#define PLLMR1_FWDVA_DIV_3 0x00050000
526#define PLLMR1_FWDVA_DIV_2 0x00060000
527#define PLLMR1_FWDVA_DIV_1 0x00070000
528#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
529#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
530
531/* Defines for CPC0_EPRCSR register */
532#define CPC0_EPRCSR_E0NFE 0x80000000
533#define CPC0_EPRCSR_E1NFE 0x40000000
534#define CPC0_EPRCSR_E1RPP 0x00000080
535#define CPC0_EPRCSR_E0RPP 0x00000040
536#define CPC0_EPRCSR_E1ERP 0x00000020
537#define CPC0_EPRCSR_E0ERP 0x00000010
538#define CPC0_EPRCSR_E1PCI 0x00000002
539#define CPC0_EPRCSR_E0PCI 0x00000001
540
541/* Defines for CPC0_PCI Register */
542#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
543#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
544#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
545
546/* Defines for CPC0_BOOR Register */
547#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
548
549/* Defines for CPC0_PLLMR1 Register fields */
550#define PLL_ACTIVE 0x80000000
551#define CPC0_PLLMR1_SSCS 0x80000000
552#define PLL_RESET 0x40000000
553#define CPC0_PLLMR1_PLLR 0x40000000
554 /* Feedback multiplier */
555#define PLL_FBKDIV 0x00F00000
556#define CPC0_PLLMR1_FBDV 0x00F00000
557#define PLL_FBKDIV_16 0x00000000
558#define PLL_FBKDIV_1 0x00100000
559#define PLL_FBKDIV_2 0x00200000
560#define PLL_FBKDIV_3 0x00300000
561#define PLL_FBKDIV_4 0x00400000
562#define PLL_FBKDIV_5 0x00500000
563#define PLL_FBKDIV_6 0x00600000
564#define PLL_FBKDIV_7 0x00700000
565#define PLL_FBKDIV_8 0x00800000
566#define PLL_FBKDIV_9 0x00900000
567#define PLL_FBKDIV_10 0x00A00000
568#define PLL_FBKDIV_11 0x00B00000
569#define PLL_FBKDIV_12 0x00C00000
570#define PLL_FBKDIV_13 0x00D00000
571#define PLL_FBKDIV_14 0x00E00000
572#define PLL_FBKDIV_15 0x00F00000
573 /* Forward A divisor */
574#define PLL_FWDDIVA 0x00070000
575#define CPC0_PLLMR1_FWDVA 0x00070000
576#define PLL_FWDDIVA_8 0x00000000
577#define PLL_FWDDIVA_7 0x00010000
578#define PLL_FWDDIVA_6 0x00020000
579#define PLL_FWDDIVA_5 0x00030000
580#define PLL_FWDDIVA_4 0x00040000
581#define PLL_FWDDIVA_3 0x00050000
582#define PLL_FWDDIVA_2 0x00060000
583#define PLL_FWDDIVA_1 0x00070000
584 /* Forward B divisor */
585#define PLL_FWDDIVB 0x00007000
586#define CPC0_PLLMR1_FWDVB 0x00007000
587#define PLL_FWDDIVB_8 0x00000000
588#define PLL_FWDDIVB_7 0x00001000
589#define PLL_FWDDIVB_6 0x00002000
590#define PLL_FWDDIVB_5 0x00003000
591#define PLL_FWDDIVB_4 0x00004000
592#define PLL_FWDDIVB_3 0x00005000
593#define PLL_FWDDIVB_2 0x00006000
594#define PLL_FWDDIVB_1 0x00007000
595 /* PLL tune bits */
596#define PLL_TUNE_MASK 0x000003FF
597#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
598#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
599#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
600#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
601#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
602#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
603#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
604
605/* Defines for CPC0_PLLMR0 Register fields */
606 /* CPU divisor */
607#define PLL_CPUDIV 0x00300000
608#define CPC0_PLLMR0_CCDV 0x00300000
609#define PLL_CPUDIV_1 0x00000000
610#define PLL_CPUDIV_2 0x00100000
611#define PLL_CPUDIV_3 0x00200000
612#define PLL_CPUDIV_4 0x00300000
613 /* PLB divisor */
614#define PLL_PLBDIV 0x00030000
615#define CPC0_PLLMR0_CBDV 0x00030000
616#define PLL_PLBDIV_1 0x00000000
617#define PLL_PLBDIV_2 0x00010000
618#define PLL_PLBDIV_3 0x00020000
619#define PLL_PLBDIV_4 0x00030000
620 /* OPB divisor */
621#define PLL_OPBDIV 0x00003000
622#define CPC0_PLLMR0_OPDV 0x00003000
623#define PLL_OPBDIV_1 0x00000000
624#define PLL_OPBDIV_2 0x00001000
625#define PLL_OPBDIV_3 0x00002000
626#define PLL_OPBDIV_4 0x00003000
627 /* EBC divisor */
628#define PLL_EXTBUSDIV 0x00000300
629#define CPC0_PLLMR0_EPDV 0x00000300
630#define PLL_EXTBUSDIV_2 0x00000000
631#define PLL_EXTBUSDIV_3 0x00000100
632#define PLL_EXTBUSDIV_4 0x00000200
633#define PLL_EXTBUSDIV_5 0x00000300
634 /* MAL divisor */
635#define PLL_MALDIV 0x00000030
636#define CPC0_PLLMR0_MPDV 0x00000030
637#define PLL_MALDIV_1 0x00000000
638#define PLL_MALDIV_2 0x00000010
639#define PLL_MALDIV_3 0x00000020
640#define PLL_MALDIV_4 0x00000030
641 /* PCI divisor */
642#define PLL_PCIDIV 0x00000003
643#define CPC0_PLLMR0_PPFD 0x00000003
644#define PLL_PCIDIV_1 0x00000000
645#define PLL_PCIDIV_2 0x00000001
646#define PLL_PCIDIV_3 0x00000002
647#define PLL_PCIDIV_4 0x00000003
648
649/*
650 *-------------------------------------------------------------------------------
651 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
652 * assuming a 33.3MHz input clock to the 405EP.
653 *-------------------------------------------------------------------------------
654 */
655#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]656 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
657 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]658#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]659 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
660 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]661
662#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]663 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
664 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]665#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]666 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
667 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]668#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]669 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
670 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]671#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]672 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
673 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]674#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]675 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
676 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]677#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]678 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
679 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroese44acc8d2004-12-16 18:03:44 +0000[diff] [blame]680#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
wdenkefe2a4d2004-12-16 21:44:03 +0000[diff] [blame]681 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
682 PLL_MALDIV_1 | PLL_PCIDIV_2)
stroese44acc8d2004-12-16 18:03:44 +0000[diff] [blame]683#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
wdenkefe2a4d2004-12-16 21:44:03 +0000[diff] [blame]684 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
685 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
Stefan Roese779e9752007-08-14 14:44:41 +0200[diff] [blame]686#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
687 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
688 PLL_MALDIV_1 | PLL_PCIDIV_3)
689#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
690 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
691 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
692#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
693 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
694 PLL_MALDIV_1 | PLL_PCIDIV_1)
695#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
696 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
697 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]698
699/*
700 * PLL Voltage Controlled Oscillator (VCO) definitions
701 * Maximum and minimum values (in MHz) for correct PLL operation.
702 */
703#define VCO_MIN 500
704#define VCO_MAX 1000
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]705#elif defined(CONFIG_405EZ)
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]706#define sdrnand0 0x4000
707#define sdrultra0 0x4040
708#define sdrultra1 0x4050
709#define sdricintstat 0x4510
710
711#define SDR_NAND0_NDEN 0x80000000
Stefan Roesec440bfe2007-06-06 11:42:13 +0200[diff] [blame]712#define SDR_NAND0_NDBTEN 0x40000000
713#define SDR_NAND0_NDBADR_MASK 0x30000000
714#define SDR_NAND0_NDBPG_MASK 0x0f000000
715#define SDR_NAND0_NDAREN 0x00800000
716#define SDR_NAND0_NDRBEN 0x00400000
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]717
718#define SDR_ULTRA0_NDGPIOBP 0x80000000
719#define SDR_ULTRA0_CSN_MASK 0x78000000
720#define SDR_ULTRA0_CSNSEL0 0x40000000
721#define SDR_ULTRA0_CSNSEL1 0x20000000
722#define SDR_ULTRA0_CSNSEL2 0x10000000
723#define SDR_ULTRA0_CSNSEL3 0x08000000
Stefan Roesec440bfe2007-06-06 11:42:13 +0200[diff] [blame]724#define SDR_ULTRA0_EBCRDYEN 0x04000000
725#define SDR_ULTRA0_SPISSINEN 0x02000000
726#define SDR_ULTRA0_NFSRSTEN 0x01000000
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]727
728#define SDR_ULTRA1_LEDNENABLE 0x40000000
729
730#define SDR_ICRX_STAT 0x80000000
731#define SDR_ICTX0_STAT 0x40000000
732#define SDR_ICTX1_STAT 0x20000000
733
Stefan Roese90e6f412007-04-18 12:05:59 +0200[diff] [blame]734#define SDR_PINSTP 0x40
735
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]736/******************************************************************************
737 * Control
738 ******************************************************************************/
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]739/* CPR Registers */
740#define cprclkupd 0x020 /* CPR_CLKUPD */
741#define cprpllc 0x040 /* CPR_PLLC */
742#define cprplld 0x060 /* CPR_PLLD */
743#define cprprimad 0x080 /* CPR_PRIMAD */
744#define cprperd0 0x0e0 /* CPR_PERD0 */
745#define cprperd1 0x0e1 /* CPR_PERD1 */
746#define cprperc0 0x180 /* CPR_PERC0 */
747#define cprmisc0 0x181 /* CPR_MISC0 */
748#define cprmisc1 0x182 /* CPR_MISC1 */
749
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]750#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
751#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
752#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
753
Stefan Roese273db7e2007-08-13 09:05:33 +0200[diff] [blame]754#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
755
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]756#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
757#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
758#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
759
760#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
761#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
762#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
763#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
764
765#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
766#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
767#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
768#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
769
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]770#else /* #ifdef CONFIG_405EP */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]771/******************************************************************************
772 * Control
773 ******************************************************************************/
774#define CNTRL_DCR_BASE 0x0b0
775#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
776#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
777#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
778#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]779#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]780
781#define ecr (0xaa) /* edge conditioner register (405gpr) */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]782
783/* Bit definitions */
784#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
785#define PLLMR_FWD_DIV_BYPASS 0xE0000000
786#define PLLMR_FWD_DIV_3 0xA0000000
787#define PLLMR_FWD_DIV_4 0x80000000
788#define PLLMR_FWD_DIV_6 0x40000000
789
790#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
791#define PLLMR_FB_DIV_1 0x02000000
792#define PLLMR_FB_DIV_2 0x04000000
793#define PLLMR_FB_DIV_3 0x06000000
794#define PLLMR_FB_DIV_4 0x08000000
795
796#define PLLMR_TUNING_MASK 0x01F80000
797
798#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
799#define PLLMR_CPU_PLB_DIV_1 0x00000000
800#define PLLMR_CPU_PLB_DIV_2 0x00020000
801#define PLLMR_CPU_PLB_DIV_3 0x00040000
802#define PLLMR_CPU_PLB_DIV_4 0x00060000
803
804#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
805#define PLLMR_OPB_PLB_DIV_1 0x00000000
806#define PLLMR_OPB_PLB_DIV_2 0x00008000
807#define PLLMR_OPB_PLB_DIV_3 0x00010000
808#define PLLMR_OPB_PLB_DIV_4 0x00018000
809
810#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
811#define PLLMR_PCI_PLB_DIV_1 0x00000000
812#define PLLMR_PCI_PLB_DIV_2 0x00002000
813#define PLLMR_PCI_PLB_DIV_3 0x00004000
814#define PLLMR_PCI_PLB_DIV_4 0x00006000
815
816#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
817#define PLLMR_EXB_PLB_DIV_2 0x00000000
818#define PLLMR_EXB_PLB_DIV_3 0x00000800
819#define PLLMR_EXB_PLB_DIV_4 0x00001000
820#define PLLMR_EXB_PLB_DIV_5 0x00001800
821
822/* definitions for PPC405GPr (new mode strapping) */
823#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
824
825#define PSR_PLL_FWD_MASK 0xC0000000
826#define PSR_PLL_FDBACK_MASK 0x30000000
827#define PSR_PLL_TUNING_MASK 0x0E000000
828#define PSR_PLB_CPU_MASK 0x01800000
829#define PSR_OPB_PLB_MASK 0x00600000
830#define PSR_PCI_PLB_MASK 0x00180000
831#define PSR_EB_PLB_MASK 0x00060000
832#define PSR_ROM_WIDTH_MASK 0x00018000
833#define PSR_ROM_LOC 0x00004000
834#define PSR_PCI_ASYNC_EN 0x00001000
835#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
836#define PSR_PCI_ARBIT_EN 0x00000400
837#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
838
stroese44acc8d2004-12-16 18:03:44 +0000[diff] [blame]839#ifndef CONFIG_IOP480
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]840/*
841 * PLL Voltage Controlled Oscillator (VCO) definitions
842 * Maximum and minimum values (in MHz) for correct PLL operation.
843 */
844#define VCO_MIN 400
845#define VCO_MAX 800
stroese44acc8d2004-12-16 18:03:44 +0000[diff] [blame]846#endif /* #ifndef CONFIG_IOP480 */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]847#endif /* #ifdef CONFIG_405EP */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]848
849/******************************************************************************
850 * Memory Access Layer
851 ******************************************************************************/
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]852#if defined(CONFIG_405EZ)
853#define MAL_DCR_BASE 0x380
854#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
855#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
856#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
857#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
858#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
859#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
860#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
861#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
862/* 0x08-0x0F Reserved */
863#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
864#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
865#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
866#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
867/* 0x14-0x1F Reserved */
868#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
869#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
870#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
871#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
872#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
873#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
874#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
875#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
876#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
877#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
878#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
879#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
880#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
881#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
882#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
883#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
884#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
885#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
886#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
887#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
888#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
889#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
890#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
891#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
892#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
893#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
894#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
895#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
896#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
897#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
898#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
899#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
900#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
901#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
902#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
903#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
904#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
905#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
906#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
907#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
908#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
909#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
910#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
911#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
912#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
913#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
914#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
915#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
916#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
917#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
918#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
919#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
920#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
921#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
922#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
923#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
924#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
925#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
926#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
927#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
928#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
929#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
930#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
931#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
932#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
933#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
934#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
935#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
936#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
937#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
938#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
939#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
940#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
941#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
942#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
943#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
944#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
945#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
946#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
947#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
948#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
949#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
950#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
951#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
952#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
953#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
954#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
955#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
956#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
957#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
958#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
959#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
960#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
961#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
962#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
963#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
964
965#else /* !defined(CONFIG_405EZ) */
966
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]967#define MAL_DCR_BASE 0x180
968#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
969#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
970#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
971#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
972#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
973#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
974#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
975#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
976#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
977#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
978#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
979#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
980#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
981#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
wdenkcea655a2004-06-06 23:53:59 +0000[diff] [blame]982#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]983#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
wdenkcea655a2004-06-06 23:53:59 +0000[diff] [blame]984#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]985#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
wdenkcea655a2004-06-06 23:53:59 +0000[diff] [blame]986#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]987#endif /* defined(CONFIG_405EZ) */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]988
989/*-----------------------------------------------------------------------------
990| IIC Register Offsets
991'----------------------------------------------------------------------------*/
992#define IICMDBUF 0x00
993#define IICSDBUF 0x02
994#define IICLMADR 0x04
995#define IICHMADR 0x05
996#define IICCNTL 0x06
997#define IICMDCNTL 0x07
998#define IICSTS 0x08
999#define IICEXTSTS 0x09
1000#define IICLSADR 0x0A
1001#define IICHSADR 0x0B
1002#define IICCLKDIV 0x0C
1003#define IICINTRMSK 0x0D
1004#define IICXFRCNT 0x0E
1005#define IICXTCNTLSS 0x0F
1006#define IICDIRECTCNTL 0x10
1007
1008/*-----------------------------------------------------------------------------
1009| UART Register Offsets
1010'----------------------------------------------------------------------------*/
1011#define DATA_REG 0x00
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]1012#define DL_LSB 0x00
1013#define DL_MSB 0x01
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1014#define INT_ENABLE 0x01
1015#define FIFO_CONTROL 0x02
1016#define LINE_CONTROL 0x03
1017#define MODEM_CONTROL 0x04
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200[diff] [blame]1018#define LINE_STATUS 0x05
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1019#define MODEM_STATUS 0x06
1020#define SCRATCH 0x07
1021
1022/******************************************************************************
1023 * On Chip Memory
1024 ******************************************************************************/
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]1025#if defined(CONFIG_405EZ)
1026#define OCM_DCR_BASE 0x020
1027#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
1028#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
1029#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
1030#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
1031#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
1032#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
1033#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
1034#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
1035#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
1036#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
1037#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
1038#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
1039#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
1040#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
1041#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
1042#else
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1043#define OCM_DCR_BASE 0x018
1044#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
1045#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
1046#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
1047#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]1048#endif /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1049
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]1050/******************************************************************************
1051 * GPIO macro register defines
1052 ******************************************************************************/
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]1053#if defined(CONFIG_405EZ)
1054/* Only the 405EZ has 2 GPIOs */
1055#define GPIO_BASE 0xEF600700
1056#define GPIO0_OR (GPIO_BASE+0x0)
1057#define GPIO0_TCR (GPIO_BASE+0x4)
1058#define GPIO0_OSRL (GPIO_BASE+0x8)
1059#define GPIO0_OSRH (GPIO_BASE+0xC)
1060#define GPIO0_TSRL (GPIO_BASE+0x10)
1061#define GPIO0_TSRH (GPIO_BASE+0x14)
1062#define GPIO0_ODR (GPIO_BASE+0x18)
1063#define GPIO0_IR (GPIO_BASE+0x1C)
1064#define GPIO0_RR1 (GPIO_BASE+0x20)
1065#define GPIO0_RR2 (GPIO_BASE+0x24)
1066#define GPIO0_RR3 (GPIO_BASE+0x28)
1067#define GPIO0_ISR1L (GPIO_BASE+0x30)
1068#define GPIO0_ISR1H (GPIO_BASE+0x34)
1069#define GPIO0_ISR2L (GPIO_BASE+0x38)
1070#define GPIO0_ISR2H (GPIO_BASE+0x3C)
1071#define GPIO0_ISR3L (GPIO_BASE+0x40)
1072#define GPIO0_ISR3H (GPIO_BASE+0x44)
1073
1074#define GPIO1_BASE 0xEF600800
1075#define GPIO1_OR (GPIO1_BASE+0x0)
1076#define GPIO1_TCR (GPIO1_BASE+0x4)
1077#define GPIO1_OSRL (GPIO1_BASE+0x8)
1078#define GPIO1_OSRH (GPIO1_BASE+0xC)
1079#define GPIO1_TSRL (GPIO1_BASE+0x10)
1080#define GPIO1_TSRH (GPIO1_BASE+0x14)
1081#define GPIO1_ODR (GPIO1_BASE+0x18)
1082#define GPIO1_IR (GPIO1_BASE+0x1C)
1083#define GPIO1_RR1 (GPIO1_BASE+0x20)
1084#define GPIO1_RR2 (GPIO1_BASE+0x24)
1085#define GPIO1_RR3 (GPIO1_BASE+0x28)
1086#define GPIO1_ISR1L (GPIO1_BASE+0x30)
1087#define GPIO1_ISR1H (GPIO1_BASE+0x34)
1088#define GPIO1_ISR2L (GPIO1_BASE+0x38)
1089#define GPIO1_ISR2H (GPIO1_BASE+0x3C)
1090#define GPIO1_ISR3L (GPIO1_BASE+0x40)
1091#define GPIO1_ISR3H (GPIO1_BASE+0x44)
1092
Stefan Roesedbbd1252007-10-05 17:10:59 +0200[diff] [blame]1093#elif defined(CONFIG_405EX)
1094#define GPIO_BASE 0xEF600800
1095#define GPIO0_OR (GPIO_BASE+0x0)
1096#define GPIO0_TCR (GPIO_BASE+0x4)
1097#define GPIO0_OSRL (GPIO_BASE+0x8)
1098#define GPIO0_OSRH (GPIO_BASE+0xC)
1099#define GPIO0_TSRL (GPIO_BASE+0x10)
1100#define GPIO0_TSRH (GPIO_BASE+0x14)
1101#define GPIO0_ODR (GPIO_BASE+0x18)
1102#define GPIO0_IR (GPIO_BASE+0x1C)
1103#define GPIO0_RR1 (GPIO_BASE+0x20)
1104#define GPIO0_RR2 (GPIO_BASE+0x24)
1105#define GPIO0_ISR1L (GPIO_BASE+0x30)
1106#define GPIO0_ISR1H (GPIO_BASE+0x34)
1107#define GPIO0_ISR2L (GPIO_BASE+0x38)
1108#define GPIO0_ISR2H (GPIO_BASE+0x3C)
1109#define GPIO0_ISR3L (GPIO_BASE+0x40)
1110#define GPIO0_ISR3H (GPIO_BASE+0x44)
1111
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]1112#else /* !405EZ */
1113
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]1114#define GPIO_BASE 0xEF600700
1115#define GPIO0_OR (GPIO_BASE+0x0)
1116#define GPIO0_TCR (GPIO_BASE+0x4)
1117#define GPIO0_OSRH (GPIO_BASE+0x8)
1118#define GPIO0_OSRL (GPIO_BASE+0xC)
1119#define GPIO0_TSRH (GPIO_BASE+0x10)
1120#define GPIO0_TSRL (GPIO_BASE+0x14)
1121#define GPIO0_ODR (GPIO_BASE+0x18)
1122#define GPIO0_IR (GPIO_BASE+0x1C)
1123#define GPIO0_RR1 (GPIO_BASE+0x20)
1124#define GPIO0_RR2 (GPIO_BASE+0x24)
1125#define GPIO0_ISR1H (GPIO_BASE+0x30)
1126#define GPIO0_ISR1L (GPIO_BASE+0x34)
1127#define GPIO0_ISR2H (GPIO_BASE+0x38)
1128#define GPIO0_ISR2L (GPIO_BASE+0x3C)
1129
Stefan Roesee01bd212007-03-21 13:38:59 +0100[diff] [blame]1130#endif /* CONFIG_405EZ */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1131
Stefan Roesedbbd1252007-10-05 17:10:59 +0200[diff] [blame]1132#if defined(CONFIG_405EX)
1133#define SDR0_SRST 0x0200
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1134
Stefan Roesedbbd1252007-10-05 17:10:59 +0200[diff] [blame]1135#define SDRAM_BESR0 0x00
1136#define SDRAM_BEARL 0x02
1137#define SDRAM_BEARU 0x03
1138#define SDRAM_WMIRQ 0x06 /**/
1139#define SDRAM_PLBOPT 0x08 /**/
1140#define SDRAM_PUABA 0x09 /**/
1141#define SDRAM_MCSTAT 0x1F /* memory controller status */
1142#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
1143#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
1144#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
1145#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
1146#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
1147#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
1148#define SDRAM_CODT 0x26 /* on die termination for controller */
1149#define SDRAM_VVPR 0x27 /* variable VRef programmming */
1150#define SDRAM_OPARS 0x28 /* on chip driver control setup */
1151#define SDRAM_OPART 0x29 /* on chip driver control trigger */
1152#define SDRAM_RTR 0x30 /* refresh timer */
1153#define SDRAM_PMIT 0x34 /* power management idle timer */
1154#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
1155#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
1156#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */
1157#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */
1158#define SDRAM_INITPLR0 0x50 /* manual initialization control */
1159#define SDRAM_INITPLR1 0x51 /* manual initialization control */
1160#define SDRAM_INITPLR2 0x52 /* manual initialization control */
1161#define SDRAM_INITPLR3 0x53 /* manual initialization control */
1162#define SDRAM_INITPLR4 0x54 /* manual initialization control */
1163#define SDRAM_INITPLR5 0x55 /* manual initialization control */
1164#define SDRAM_INITPLR6 0x56 /* manual initialization control */
1165#define SDRAM_INITPLR7 0x57 /* manual initialization control */
1166#define SDRAM_INITPLR8 0x58 /* manual initialization control */
1167#define SDRAM_INITPLR9 0x59 /* manual initialization control */
1168#define SDRAM_INITPLR10 0x5a /* manual initialization control */
1169#define SDRAM_INITPLR11 0x5b /* manual initialization control */
1170#define SDRAM_INITPLR12 0x5c /* manual initialization control */
1171#define SDRAM_INITPLR13 0x5d /* manual initialization control */
1172#define SDRAM_INITPLR14 0x5e /* manual initialization control */
1173#define SDRAM_INITPLR15 0x5f /* manual initialization control */
1174#define SDRAM_RQDC 0x70 /* read DQS delay control */
1175#define SDRAM_RFDC 0x74 /* read feedback delay control */
1176#define SDRAM_RDCC 0x78 /* read data capture control */
1177#define SDRAM_DLCR 0x7A /* delay line calibration */
1178#define SDRAM_CLKTR 0x80 /* DDR clock timing */
1179#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
1180#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
1181#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
1182#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
1183#define SDRAM_MMODE 0x88 /* memory mode */
1184#define SDRAM_MEMODE 0x89 /* memory extended mode */
1185#define SDRAM_ECCCR 0x98 /* ECC error status */
1186#define SDRAM_RID 0xF8 /* revision ID */
1187
1188/*-----------------------------------------------------------------------------+
1189| Memory Bank 0-7 configuration
1190+-----------------------------------------------------------------------------*/
1191#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */
1192#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */
1193#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */
1194#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */
1195#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */
1196#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */
1197#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */
1198#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */
1199#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */
1200#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */
1201#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */
1202#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */
1203
1204/*-----------------------------------------------------------------------------+
1205| Memory Controller Status
1206+-----------------------------------------------------------------------------*/
1207#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
1208#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
1209#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
1210#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */
1211#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
1212#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */
1213
1214/*-----------------------------------------------------------------------------+
1215| Memory Controller Options 1
1216+-----------------------------------------------------------------------------*/
1217#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */
1218#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
1219#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
1220#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
1221#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
1222#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
1223#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
1224#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
1225#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
1226#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
1227#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
1228#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
1229#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
1230#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
1231#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
1232#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
1233#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
1234#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
1235#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
1236#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
1237#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
1238#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
1239#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
1240#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
1241#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
1242#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
1243#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
1244#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
1245#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
1246#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
1247#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
1248#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
1249#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
1250#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
1251#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
1252
1253/*-----------------------------------------------------------------------------+
1254| Memory Controller Options 2
1255+-----------------------------------------------------------------------------*/
1256#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
1257#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
1258#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
1259#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
1260#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
1261#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
1262#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
1263#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
1264#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
1265#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
1266#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
1267#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
1268#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
1269#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
1270#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
1271#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
1272#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
1273#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
1274
1275/*-----------------------------------------------------------------------------+
1276| SDRAM Refresh Timer Register
1277+-----------------------------------------------------------------------------*/
1278#define SDRAM_RTR_RINT_MASK 0xFFF80000
1279#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
1280#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
1281
1282/*-----------------------------------------------------------------------------+
1283| SDRAM Read DQS Delay Control Register
1284+-----------------------------------------------------------------------------*/
1285#define SDRAM_RQDC_RQDE_MASK 0x80000000
1286#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
1287#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
1288#define SDRAM_RQDC_RQFD_MASK 0x000001FF
1289#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
1290
1291#define SDRAM_RQDC_RQFD_MAX 0xFF
1292
1293/*-----------------------------------------------------------------------------+
1294| SDRAM Read Data Capture Control Register
1295+-----------------------------------------------------------------------------*/
1296#define SDRAM_RDCC_RDSS_MASK 0xC0000000
1297#define SDRAM_RDCC_RDSS_T1 0x00000000
1298#define SDRAM_RDCC_RDSS_T2 0x40000000
1299#define SDRAM_RDCC_RDSS_T3 0x80000000
1300#define SDRAM_RDCC_RDSS_T4 0xC0000000
1301#define SDRAM_RDCC_RSAE_MASK 0x00000001
1302#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
1303#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
1304
1305/*-----------------------------------------------------------------------------+
1306| SDRAM Read Feedback Delay Control Register
1307+-----------------------------------------------------------------------------*/
1308#define SDRAM_RFDC_ARSE_MASK 0x80000000
1309#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
1310#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
1311#define SDRAM_RFDC_RFOS_MASK 0x007F0000
1312#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
1313#define SDRAM_RFDC_RFFD_MASK 0x000003FF
1314#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
1315
1316#define SDRAM_RFDC_RFFD_MAX 0x4FF
1317
1318/*-----------------------------------------------------------------------------+
1319| SDRAM Delay Line Calibration Register
1320+-----------------------------------------------------------------------------*/
1321#define SDRAM_DLCR_DCLM_MASK 0x80000000
1322#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
1323#define SDRAM_DLCR_DCLM_AUTO 0x00000000
1324#define SDRAM_DLCR_DLCR_MASK 0x08000000
1325#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
1326#define SDRAM_DLCR_DLCR_IDLE 0x00000000
1327#define SDRAM_DLCR_DLCS_MASK 0x07000000
1328#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
1329#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
1330#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
1331#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
1332#define SDRAM_DLCR_DLCS_ERROR 0x04000000
1333#define SDRAM_DLCR_DLCV_MASK 0x000001FF
1334#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
1335#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
1336
1337/*-----------------------------------------------------------------------------+
1338| SDRAM Controller On Die Termination Register
1339+-----------------------------------------------------------------------------*/
1340#define SDRAM_CODT_ODT_ON 0x80000000
1341#define SDRAM_CODT_ODT_OFF 0x00000000
1342#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
1343#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
1344#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
1345#define SDRAM_CODT_DQS_MASK 0x00000010
1346#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
1347#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
1348#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
1349#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
1350#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
1351#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
1352#define SDRAM_CODT_IO_HIZ 0x00000000
1353#define SDRAM_CODT_IO_NMODE 0x00000001
1354
1355/*-----------------------------------------------------------------------------+
1356| SDRAM Mode Register
1357+-----------------------------------------------------------------------------*/
1358#define SDRAM_MMODE_WR_MASK 0x00000E00
1359#define SDRAM_MMODE_WR_DDR1 0x00000000
1360#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
1361#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
1362#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
1363#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
1364#define SDRAM_MMODE_DCL_MASK 0x00000070
1365#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
1366#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
1367#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
1368#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
1369#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
1370#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
1371#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
1372#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
1373#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
1374
1375/*-----------------------------------------------------------------------------+
1376| SDRAM Extended Mode Register
1377+-----------------------------------------------------------------------------*/
1378#define SDRAM_MEMODE_DIC_MASK 0x00000002
1379#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
1380#define SDRAM_MEMODE_DIC_WEAK 0x00000002
1381#define SDRAM_MEMODE_DLL_MASK 0x00000001
1382#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
1383#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
1384#define SDRAM_MEMODE_RTT_MASK 0x00000044
1385#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
1386#define SDRAM_MEMODE_RTT_75OHM 0x00000004
1387#define SDRAM_MEMODE_RTT_150OHM 0x00000040
1388#define SDRAM_MEMODE_DQS_MASK 0x00000400
1389#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
1390#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
1391
1392/*-----------------------------------------------------------------------------+
1393| SDRAM Clock Timing Register
1394+-----------------------------------------------------------------------------*/
1395#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
1396#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
1397#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
1398
1399/*-----------------------------------------------------------------------------+
1400| SDRAM Write Timing Register
1401+-----------------------------------------------------------------------------*/
1402#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000
1403#define SDRAM_WRDTR_LLWP_MASK 0x10000000
1404#define SDRAM_WRDTR_LLWP_DIS 0x10000000
1405#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
1406#define SDRAM_WRDTR_WTR_MASK 0x0E000000
1407#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
1408#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
1409#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
1410
1411/*-----------------------------------------------------------------------------+
1412| SDRAM SDTR1 Options
1413+-----------------------------------------------------------------------------*/
1414#define SDRAM_SDTR1_LDOF_MASK 0x80000000
1415#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
1416#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
1417#define SDRAM_SDTR1_RTW_MASK 0x00F00000
1418#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
1419#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
1420#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
1421#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
1422#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
1423#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
1424#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000
1425#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
1426
1427/*-----------------------------------------------------------------------------+
1428| SDRAM SDTR2 Options
1429+-----------------------------------------------------------------------------*/
1430#define SDRAM_SDTR2_RCD_MASK 0xF0000000
1431#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
1432#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
1433#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
1434#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
1435#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
1436#define SDRAM_SDTR2_WTR_MASK 0x0F000000
1437#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
1438#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
1439#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
1440#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
1441#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
1442#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
1443#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
1444#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
1445#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
1446#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
1447#define SDRAM_SDTR2_WPC_MASK 0x0000F000
1448#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
1449#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
1450#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
1451#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
1452#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
1453#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
1454#define SDRAM_SDTR2_RPC_MASK 0x00000F00
1455#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
1456#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
1457#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
1458#define SDRAM_SDTR2_RP_MASK 0x000000F0
1459#define SDRAM_SDTR2_RP_3_CLK 0x00000030
1460#define SDRAM_SDTR2_RP_4_CLK 0x00000040
1461#define SDRAM_SDTR2_RP_5_CLK 0x00000050
1462#define SDRAM_SDTR2_RP_6_CLK 0x00000060
1463#define SDRAM_SDTR2_RP_7_CLK 0x00000070
1464#define SDRAM_SDTR2_RRD_MASK 0x0000000F
1465#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
1466#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
1467
1468/*-----------------------------------------------------------------------------+
1469| SDRAM SDTR3 Options
1470+-----------------------------------------------------------------------------*/
1471#define SDRAM_SDTR3_RAS_MASK 0x1F000000
1472#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
1473#define SDRAM_SDTR3_RC_MASK 0x001F0000
1474#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
1475#define SDRAM_SDTR3_XCS_MASK 0x00001F00
1476#define SDRAM_SDTR3_XCS 0x00000D00
1477#define SDRAM_SDTR3_RFC_MASK 0x0000003F
1478#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1479
1480/*-----------------------------------------------------------------------------+
1481| Memory Bank 0-1 configuration
1482+-----------------------------------------------------------------------------*/
1483#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
1484#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
1485#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
1486#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
1487#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
1488#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
1489#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
1490#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
1491#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
1492#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
1493#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
1494#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
1495#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
1496#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
1497
1498#define sdr_uart0 0x0120 /* UART0 Config */
1499#define sdr_uart1 0x0121 /* UART1 Config */
1500#define sdr_mfr 0x4300 /* SDR0_MFR reg */
1501
1502/* Defines for CPC0_EPRCSR register */
1503#define CPC0_EPRCSR_E0NFE 0x80000000
1504#define CPC0_EPRCSR_E1NFE 0x40000000
1505#define CPC0_EPRCSR_E1RPP 0x00000080
1506#define CPC0_EPRCSR_E0RPP 0x00000040
1507#define CPC0_EPRCSR_E1ERP 0x00000020
1508#define CPC0_EPRCSR_E0ERP 0x00000010
1509#define CPC0_EPRCSR_E1PCI 0x00000002
1510#define CPC0_EPRCSR_E0PCI 0x00000001
1511
1512#define cpr0_clkupd 0x020
1513#define cpr0_pllc 0x040
1514#define cpr0_plld 0x060
1515#define cpr0_cpud 0x080
1516#define cpr0_plbd 0x0a0
1517#define cpr0_opbd 0x0c0
1518#define cpr0_perd 0x0e0
1519#define cpr0_ahbd 0x100
1520#define cpr0_icfg 0x140
1521
1522#define SDR_PINSTP 0x0040
1523#define sdr_sdcs 0x0060
1524
1525#define SDR0_SDCS_SDD (0x80000000 >> 31)
1526
1527/* CUST0 Customer Configuration Register0 */
1528#define SDR0_CUST0 0x4000
1529#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
1530#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
1531#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
1532#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
1533
1534#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
1535#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
1536#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
1537
1538#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
1539#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
1540#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
1541
1542#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
1543#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
1544#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1545
1546#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
1547#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
1548#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1549
1550#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
1551#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
1552#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
1553
1554#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
1555#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
1556#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
1557
1558#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
1559#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
1560#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
1561
1562#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
1563#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
1564#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
1565#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
1566#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
1567#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
1568#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
1569#endif
1570
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1571#endif /* __PPC405_H__ */