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wdenk138ff602004-12-16 15:52:40 +00001/*
Detlev Zundele979e852009-03-30 00:31:35 +02002 * (C) Copyright 2009
3 * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
4 *
wdenk414eec32005-04-02 22:37:54 +00005 * (C) Copyright 2003-2005
wdenk138ff602004-12-16 15:52:40 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
wdenk151ab832005-02-24 22:44:16 +000035#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37#define CONFIG_INKA4X0 1 /* INKA4x0 board */
wdenk138ff602004-12-16 15:52:40 +000038
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenk138ff602004-12-16 15:52:40 +000040
wdenk151ab832005-02-24 22:44:16 +000041#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
42#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenk138ff602004-12-16 15:52:40 +000043
wdenk151ab832005-02-24 22:44:16 +000044#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
45
Becky Bruce31d82672008-05-08 19:02:12 -050046#define CONFIG_HIGH_BATS 1 /* High BATs supported */
47
wdenk138ff602004-12-16 15:52:40 +000048/*
49 * Serial console configuration
50 */
wdenk151ab832005-02-24 22:44:16 +000051#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenk138ff602004-12-16 15:52:40 +000054
55/*
wdenk436be292005-01-31 22:09:11 +000056 * PCI Mapping:
57 * 0x40000000 - 0x4fffffff - PCI Memory
58 * 0x50000000 - 0x50ffffff - PCI IO Space
59 */
60#define CONFIG_PCI 1
61#define CONFIG_PCI_PNP 1
62#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050063#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenk436be292005-01-31 22:09:11 +000064
65#define CONFIG_PCI_MEM_BUS 0x40000000
66#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
67#define CONFIG_PCI_MEM_SIZE 0x10000000
68
69#define CONFIG_PCI_IO_BUS 0x50000000
70#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
71#define CONFIG_PCI_IO_SIZE 0x01000000
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_XLB_PIPELINING 1
wdenk436be292005-01-31 22:09:11 +000074
75/* Partitions */
76#define CONFIG_MAC_PARTITION
77#define CONFIG_DOS_PARTITION
78#define CONFIG_ISO_PARTITION
79
wdenk138ff602004-12-16 15:52:40 +000080
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050081/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050082 * BOOTP options
83 */
84#define CONFIG_BOOTP_BOOTFILESIZE
85#define CONFIG_BOOTP_BOOTPATH
86#define CONFIG_BOOTP_GATEWAY
87#define CONFIG_BOOTP_HOSTNAME
88
89
90/*
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050091 * Command line configuration.
92 */
93#include <config_cmd_default.h>
94
Detlev Zundele979e852009-03-30 00:31:35 +020095#define CONFIG_CMD_DATE
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -050096#define CONFIG_CMD_DHCP
97#define CONFIG_CMD_EXT2
98#define CONFIG_CMD_FAT
99#define CONFIG_CMD_IDE
100#define CONFIG_CMD_NFS
101#define CONFIG_CMD_PCI
Detlev Zundele979e852009-03-30 00:31:35 +0200102#define CONFIG_CMD_PING
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -0500103#define CONFIG_CMD_SNTP
104#define CONFIG_CMD_USB
105
wdenkb05dcb52005-03-04 11:27:31 +0000106#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
107
wdenk138ff602004-12-16 15:52:40 +0000108#if (TEXT_BASE == 0xFFE00000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# define CONFIG_SYS_LOWBOOT 1
wdenk138ff602004-12-16 15:52:40 +0000110#endif
111
112/*
113 * Autobooting
114 */
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100115#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
wdenk138ff602004-12-16 15:52:40 +0000116
117#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100118 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk138ff602004-12-16 15:52:40 +0000119 "echo"
120
121#undef CONFIG_BOOTARGS
122
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100123#define CONFIG_ETHADDR 00:a0:a4:03:00:00
124#define CONFIG_OVERWRITE_ETHADDR_ONCE
125
126#define CONFIG_IPADDR 192.168.100.2
127#define CONFIG_SERVERIP 192.168.100.1
128#define CONFIG_NETMASK 255.255.255.0
129#define HOSTNAME inka4x0
130#define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage
131#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
132
wdenk138ff602004-12-16 15:52:40 +0000133#define CONFIG_EXTRA_ENV_SETTINGS \
134 "netdev=eth0\0" \
135 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100136 "nfsroot=${serverip}:${rootpath}\0" \
wdenk138ff602004-12-16 15:52:40 +0000137 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100138 "addip=setenv bootargs ${bootargs} " \
139 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
140 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100141 "addcons=setenv bootargs ${bootargs} " \
142 "console=ttyS0,${baudrate}\0" \
143 "flash_nfs=run nfsargs addip addcons;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100144 "bootm ${kernel_addr}\0" \
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100145 "net_nfs=tftp 200000 ${bootfile};" \
146 "run nfsargs addip addcons;bootm\0" \
147 "enable_disp=mw.l 100000 04000000 1;" \
148 "cp.l 100000 f0000b20 1;" \
149 "cp.l 100000 f0000b28 1\0" \
150 "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
151 "ide_boot=ext2load ide 0:1 200000 uImage;" \
Marian Balakowiczf23cb342007-11-15 13:24:43 +0100152 "run ideargs addip addcons enable_disp;bootm\0" \
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100153 "brightness=255\0" \
wdenk138ff602004-12-16 15:52:40 +0000154 ""
155
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100156#define CONFIG_BOOTCOMMAND "run ide_boot"
wdenk138ff602004-12-16 15:52:40 +0000157
158/*
159 * IPB Bus clocking configuration.
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenk138ff602004-12-16 15:52:40 +0000162
163/*
164 * Flash configuration
165 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200167#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_BASE 0xffe00000
169#define CONFIG_SYS_FLASH_SIZE 0x00200000
170#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
171#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
172#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
173#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
wdenk138ff602004-12-16 15:52:40 +0000174
175/*
176 * Environment settings
177 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200178#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200180#define CONFIG_ENV_SIZE 0x2000
181#define CONFIG_ENV_SECT_SIZE 0x2000
wdenk138ff602004-12-16 15:52:40 +0000182#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk138ff602004-12-16 15:52:40 +0000184
185/*
186 * Memory map
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MBAR 0xF0000000
189#define CONFIG_SYS_SDRAM_BASE 0x00000000
190#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenk138ff602004-12-16 15:52:40 +0000191
Marian Balakowicz5fb6d712007-11-15 13:29:55 +0100192/*
193 * SDRAM controller configuration
194 */
195#undef CONFIG_SDR_MT48LC16M16A2
196#undef CONFIG_DDR_MT46V16M16
197#undef CONFIG_DDR_MT46V32M16
198#undef CONFIG_DDR_HYB25D512160BF
199#define CONFIG_DDR_K4H511638C
wdenk138ff602004-12-16 15:52:40 +0000200
201/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
wdenk138ff602004-12-16 15:52:40 +0000203#ifdef CONFIG_POST
204/* preserve space for the post_word at end of on-chip SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
wdenk138ff602004-12-16 15:52:40 +0000206#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
wdenk138ff602004-12-16 15:52:40 +0000208#endif
209
210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
212#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
213#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk138ff602004-12-16 15:52:40 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
216#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
217# define CONFIG_SYS_RAMBOOT 1
wdenk138ff602004-12-16 15:52:40 +0000218#endif
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
221#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
222#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk138ff602004-12-16 15:52:40 +0000223
224/*
225 * Ethernet configuration
226 */
227#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800228#define CONFIG_MPC5xxx_FEC_MII100
wdenk138ff602004-12-16 15:52:40 +0000229/*
Ben Warren86321fc2009-02-05 23:58:25 -0800230 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
wdenk138ff602004-12-16 15:52:40 +0000231 */
Ben Warren86321fc2009-02-05 23:58:25 -0800232/* #define CONFIG_MPC5xxx_FEC_MII10 */
wdenk138ff602004-12-16 15:52:40 +0000233#define CONFIG_PHY_ADDR 0x00
Wolfgang Denk84e106c2006-02-07 15:18:25 +0100234#define CONFIG_MII
wdenk138ff602004-12-16 15:52:40 +0000235
236/*
237 * GPIO configuration
238 *
wdenk9f709b62005-04-22 15:09:09 +0000239 * use CS1 as gpio_wkup_6 output
240 * Bit 0 (mask: 0x80000000): 0
wdenk138ff602004-12-16 15:52:40 +0000241 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
242 * 00 -> No Alternatives, I2C1 is used for onboard EEPROM
243 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
244 * EEPROM
245 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
Detlev Zundele979e852009-03-30 00:31:35 +0200246 * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
247 * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
248 * use PSC6 as UART: Bits 9-11 (mask: 0x00700000): 0101
wdenk138ff602004-12-16 15:52:40 +0000249 */
Detlev Zundele979e852009-03-30 00:31:35 +0200250#define CONFIG_SYS_GPS_PORT_CONFIG 0x01501444
wdenk138ff602004-12-16 15:52:40 +0000251
252/*
253 * RTC configuration
254 */
Detlev Zundele979e852009-03-30 00:31:35 +0200255#define CONFIG_RTC_RTC4543 1 /* use external RTC */
256
257/*
258 * Software (bit-bang) three wire serial configuration
259 *
260 * Note that we need the ifdefs because otherwise compilation of
261 * mkimage.c fails.
262 */
263#define CONFIG_SOFT_TWS 1
264
265#ifdef TWS_IMPLEMENTATION
266#include <mpc5xxx.h>
267#include <asm/io.h>
268
269#define TWS_CE MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
270#define TWS_WR MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
271#define TWS_DATA MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
272#define TWS_CLK MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
273
274static inline void tws_ce(unsigned bit)
275{
276 struct mpc5xxx_wu_gpio *wu_gpio =
277 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
278 if (bit)
279 setbits_8(&wu_gpio->dvo, TWS_CE);
280 else
281 clrbits_8(&wu_gpio->dvo, TWS_CE);
282}
283
284static inline void tws_wr(unsigned bit)
285{
286 struct mpc5xxx_wu_gpio *wu_gpio =
287 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
288 if (bit)
289 setbits_8(&wu_gpio->dvo, TWS_WR);
290 else
291 clrbits_8(&wu_gpio->dvo, TWS_WR);
292}
293
294static inline void tws_clk(unsigned bit)
295{
296 struct mpc5xxx_gpio *gpio =
297 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
298 if (bit)
299 setbits_8(&gpio->sint_dvo, TWS_CLK);
300 else
301 clrbits_8(&gpio->sint_dvo, TWS_CLK);
302}
303
304static inline void tws_data(unsigned bit)
305{
306 struct mpc5xxx_gpio *gpio =
307 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
308 if (bit)
309 setbits_8(&gpio->sint_dvo, TWS_DATA);
310 else
311 clrbits_8(&gpio->sint_dvo, TWS_DATA);
312}
313
314static inline unsigned tws_data_read(void)
315{
316 struct mpc5xxx_gpio *gpio =
317 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
318 return !!(in_8(&gpio->sint_ival) & TWS_DATA);
319}
320
321static inline void tws_data_config_output(unsigned output)
322{
323 struct mpc5xxx_gpio *gpio =
324 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
325 if (output)
326 setbits_8(&gpio->sint_ddr, TWS_DATA);
327 else
328 clrbits_8(&gpio->sint_ddr, TWS_DATA);
329}
330#endif /* TWS_IMPLEMENTATION */
wdenk138ff602004-12-16 15:52:40 +0000331
332/*
333 * Miscellaneous configurable options
334 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_LONGHELP /* undef to save memory */
336#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -0500337#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk138ff602004-12-16 15:52:40 +0000339#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk138ff602004-12-16 15:52:40 +0000341#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
343#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
344#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk138ff602004-12-16 15:52:40 +0000345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -0500347#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger1d2c6bc2007-07-04 22:32:32 -0500349#endif
350
wdenk138ff602004-12-16 15:52:40 +0000351/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_ALT_MEMTEST
wdenk138ff602004-12-16 15:52:40 +0000353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
355#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenk138ff602004-12-16 15:52:40 +0000356
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk138ff602004-12-16 15:52:40 +0000358
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk138ff602004-12-16 15:52:40 +0000360
361/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500362 * Enable loopw command.
wdenk138ff602004-12-16 15:52:40 +0000363 */
364#define CONFIG_LOOPW
365
366/*
367 * Various low-level settings
368 */
369#if defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
371#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenk138ff602004-12-16 15:52:40 +0000372#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_HID0_INIT 0
374#define CONFIG_SYS_HID0_FINAL 0
wdenk138ff602004-12-16 15:52:40 +0000375#endif
376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
378#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
379#define CONFIG_SYS_BOOTCS_CFG 0x00087800 /* for pci_clk = 66 MHz */
380#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
381#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenk138ff602004-12-16 15:52:40 +0000382
wdenke58cf2a2005-02-27 23:46:58 +0000383/* 32Mbit SRAM @0x30000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_CS1_START 0x30000000
385#define CONFIG_SYS_CS1_SIZE 0x00400000
386#define CONFIG_SYS_CS1_CFG 0x31800 /* for pci_clk = 33 MHz */
wdenke58cf2a2005-02-27 23:46:58 +0000387
388/* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_CS2_START 0x80000000
390#define CONFIG_SYS_CS2_SIZE 0x0001000
391#define CONFIG_SYS_CS2_CFG 0x21800 /* for pci_clk = 33 MHz */
wdenke58cf2a2005-02-27 23:46:58 +0000392
wdenkf4733a02005-03-06 01:21:30 +0000393/* GPIO in @0x30400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_CS3_START 0x30400000
395#define CONFIG_SYS_CS3_SIZE 0x00100000
396#define CONFIG_SYS_CS3_CFG 0x31800 /* for pci_clk = 33 MHz */
wdenkf4733a02005-03-06 01:21:30 +0000397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_CS_BURST 0x00000000
399#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenk138ff602004-12-16 15:52:40 +0000400
wdenk436be292005-01-31 22:09:11 +0000401/*-----------------------------------------------------------------------
402 * USB stuff
403 *-----------------------------------------------------------------------
404 */
405#define CONFIG_USB_OHCI
wdenk151ab832005-02-24 22:44:16 +0000406#define CONFIG_USB_CLOCK 0x00015555
407#define CONFIG_USB_CONFIG 0x00001000
wdenk1968e612005-02-24 23:23:29 +0000408#define CONFIG_USB_STORAGE
wdenk436be292005-01-31 22:09:11 +0000409
wdenkb05dcb52005-03-04 11:27:31 +0000410/*-----------------------------------------------------------------------
411 * IDE/ATA stuff Supports IDE harddisk
412 *-----------------------------------------------------------------------
413 */
414
415#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
416
417#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
418#undef CONFIG_IDE_LED /* LED for ide not supported */
419
wdenkb05dcb52005-03-04 11:27:31 +0000420#define CONFIG_IDE_PREINIT
421
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
423#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
wdenkb05dcb52005-03-04 11:27:31 +0000424
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
426#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
427#define CONFIG_SYS_ATA_DATA_OFFSET 0x0060 /* Offset for data I/O */
428#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
429#define CONFIG_SYS_ATA_ALT_OFFSET 0x005C /* Offset for alternate registers */
430#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
wdenkb05dcb52005-03-04 11:27:31 +0000431
432#define CONFIG_ATAPI 1
Wolfgang Denk1806c752005-09-21 10:07:56 +0200433
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_BRIGHTNESS 0xFF /* LCD Default Brightness (255 = off) */
wdenkb05dcb52005-03-04 11:27:31 +0000435
wdenk138ff602004-12-16 15:52:40 +0000436#endif /* __CONFIG_H */