blob: 0c8e6dfb1ecbca94614cf7f311cb04efe7f69c05 [file] [log] [blame]
Stefan Roeseb79316f2005-08-15 12:31:23 +02001/*
2 * Copyright (c) 2005
3 * Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23#include <config.h>
24#include <common.h>
25#include <command.h>
26#include "metrobox.h"
27#include "metrobox_version.h"
Peter Tyser561858e2008-11-03 09:30:59 -060028#include <timestamp.h>
Stefan Roeseb79316f2005-08-15 12:31:23 +020029#include <asm/processor.h>
30#include <asm/io.h>
31#include <spd_sdram.h>
32#include <i2c.h>
33#include "../common/ppc440gx_i2c.h"
34#include "../common/sb_common.h"
Wolfgang Denkd2567be2009-03-28 20:16:16 +010035#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) || \
36 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
37#include <net.h>
38#endif
Stefan Roeseb79316f2005-08-15 12:31:23 +020039
Stefan Roeseb79316f2005-08-15 12:31:23 +020040void fpga_init (void);
41
42METROBOX_BOARD_ID_ST board_id_as[] =
43{ {"Undefined"}, /* Not specified */
44 {"2x10Gb"}, /* 2 ports, 10 GbE */
45 {"20x1Gb"}, /* 20 ports, 1 GbE */
46 {"Reserved"}, /* Reserved for future use */
47};
48
Stefan Roeseb79316f2005-08-15 12:31:23 +020049/*************************************************************************
50 * board_early_init_f
51 *
52 * Setup chip selects, initialize the Opto-FPGA, initialize
53 * interrupt polarity and triggers.
Stefan Roeseb79316f2005-08-15 12:31:23 +020054 ************************************************************************/
55int board_early_init_f (void)
56{
57 ppc440_gpio_regs_t *gpio_regs;
58
59 /* Enable GPIO interrupts */
Stefan Roesed1c3b272009-09-09 16:25:29 +020060 mtsdr(SDR0_PFC0, 0x00103E00);
Stefan Roeseb79316f2005-08-15 12:31:23 +020061
62 /* Setup access for LEDs, and system topology info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
Stefan Roeseb79316f2005-08-15 12:31:23 +020064 gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
65 gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
66
67 /* Turn on all the leds for now */
68 gpio_regs->out = SBCOMMON_GPIO_LEDS;
69
70 /*--------------------------------------------------------------------+
71 | Initialize EBC CONFIG
72 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +020073 mtebc(EBC0_CFG,
Stefan Roeseb79316f2005-08-15 12:31:23 +020074 EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE |
75 EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
76 EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
77 EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE |
78 EBC_CFG_PR_32);
79
80 /*--------------------------------------------------------------------+
81 | 1/2 MB FLASH. Initialize bank 0 with default values.
82 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +020083 mtebc(PB0AP,
Stefan Roeseb79316f2005-08-15 12:31:23 +020084 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
85 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
86 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
87 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
88 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
89 EBC_BXAP_PEN_DISABLED);
90
Stefan Roesed1c3b272009-09-09 16:25:29 +020091 mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
Stefan Roeseb79316f2005-08-15 12:31:23 +020092 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
93 /*--------------------------------------------------------------------+
94 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
95 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +020096 mtebc(PB1AP,
Stefan Roeseb79316f2005-08-15 12:31:23 +020097 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
98 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
99 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
100 EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
101 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
102 EBC_BXAP_PEN_DISABLED);
103
Stefan Roesed1c3b272009-09-09 16:25:29 +0200104 mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
Stefan Roeseb79316f2005-08-15 12:31:23 +0200105 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
106
107 /*--------------------------------------------------------------------+
108 | Compact Flash, uses 2 Chip Selects (2 & 6)
109 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200110 mtebc(PB2AP,
Stefan Roeseb79316f2005-08-15 12:31:23 +0200111 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
112 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
113 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
114 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
115 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
116 EBC_BXAP_PEN_DISABLED);
117
Stefan Roesed1c3b272009-09-09 16:25:29 +0200118 mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) |
Stefan Roeseb79316f2005-08-15 12:31:23 +0200119 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
120
121 /*--------------------------------------------------------------------+
122 | OPTO & OFEM FPGA. Initialize bank 3 with default values.
123 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200124 mtebc(PB3AP,
Stefan Roeseb79316f2005-08-15 12:31:23 +0200125 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
126 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
127 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
128 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
129 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
130
Stefan Roesed1c3b272009-09-09 16:25:29 +0200131 mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) |
Stefan Roeseb79316f2005-08-15 12:31:23 +0200132 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
133
134 /*--------------------------------------------------------------------+
135 | MAC A for metrobox
136 | MAC A & B for Kamino. OFEM FPGA decodes the addresses
137 | Initialize bank 4 with default values.
138 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200139 mtebc(PB4AP,
Stefan Roeseb79316f2005-08-15 12:31:23 +0200140 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
141 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
142 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
143 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
144 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
145
Stefan Roesed1c3b272009-09-09 16:25:29 +0200146 mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) |
Stefan Roeseb79316f2005-08-15 12:31:23 +0200147 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
148
149 /*--------------------------------------------------------------------+
150 | Metrobox MAC B Initialize bank 5 with default values.
151 | KA REF FPGA Initialize bank 5 with default values.
152 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200153 mtebc(PB5AP,
Stefan Roeseb79316f2005-08-15 12:31:23 +0200154 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
155 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
156 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
157 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
158 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
159
Stefan Roesed1c3b272009-09-09 16:25:29 +0200160 mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) |
Stefan Roeseb79316f2005-08-15 12:31:23 +0200161 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
162
163 /*--------------------------------------------------------------------+
164 | Compact Flash, uses 2 Chip Selects (2 & 6)
165 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200166 mtebc(PB6AP,
Stefan Roeseb79316f2005-08-15 12:31:23 +0200167 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
168 EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) |
169 EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
170 EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
171 EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY |
172 EBC_BXAP_PEN_DISABLED);
173
Stefan Roesed1c3b272009-09-09 16:25:29 +0200174 mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) |
Stefan Roeseb79316f2005-08-15 12:31:23 +0200175 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
176
177 /*--------------------------------------------------------------------+
178 | BME-32. Initialize bank 7 with default values.
179 +-------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200180 mtebc(PB7AP,
Stefan Roeseb79316f2005-08-15 12:31:23 +0200181 EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED |
182 EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) |
183 EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) |
184 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
185 EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);
186
Stefan Roesed1c3b272009-09-09 16:25:29 +0200187 mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) |
Stefan Roeseb79316f2005-08-15 12:31:23 +0200188 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
189
Stefan Roeseb79316f2005-08-15 12:31:23 +0200190 /*--------------------------------------------------------------------+
191 * Setup the interrupt controller polarities, triggers, etc.
192 +-------------------------------------------------------------------*/
Stefan Roese5de85142008-06-26 17:36:39 +0200193 /*
194 * Because of the interrupt handling rework to handle 440GX interrupts
195 * with the common code, we needed to change names of the UIC registers.
196 * Here the new relationship:
197 *
198 * U-Boot name 440GX name
199 * -----------------------
200 * UIC0 UICB0
201 * UIC1 UIC0
202 * UIC2 UIC1
203 * UIC3 UIC2
204 */
Stefan Roese952e7762009-09-24 09:55:50 +0200205 mtdcr (UIC1SR, 0xffffffff); /* clear all */
206 mtdcr (UIC1ER, 0x00000000); /* disable all */
207 mtdcr (UIC1CR, 0x00000000); /* all non- critical */
208 mtdcr (UIC1PR, 0xfffffe03); /* polarity */
209 mtdcr (UIC1TR, 0x01c00000); /* trigger edge vs level */
210 mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
211 mtdcr (UIC1SR, 0xffffffff); /* clear all */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200212
Stefan Roese952e7762009-09-24 09:55:50 +0200213 mtdcr (UIC2SR, 0xffffffff); /* clear all */
214 mtdcr (UIC2ER, 0x00000000); /* disable all */
215 mtdcr (UIC2CR, 0x00000000); /* all non-critical */
216 mtdcr (UIC2PR, 0xffffc8ff); /* polarity */
217 mtdcr (UIC2TR, 0x00ff0000); /* trigger edge vs level */
218 mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
219 mtdcr (UIC2SR, 0xffffffff); /* clear all */
Stefan Roeseb79316f2005-08-15 12:31:23 +0200220
Stefan Roese952e7762009-09-24 09:55:50 +0200221 mtdcr (UIC3SR, 0xffffffff); /* clear all */
222 mtdcr (UIC3ER, 0x00000000); /* disable all */
223 mtdcr (UIC3CR, 0x00000000); /* all non-critical */
224 mtdcr (UIC3PR, 0xffff83ff); /* polarity */
225 mtdcr (UIC3TR, 0x00ff8c0f); /* trigger edge vs level */
226 mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
227 mtdcr (UIC3SR, 0xffffffff); /* clear all */
Stefan Roese5de85142008-06-26 17:36:39 +0200228
Stefan Roese952e7762009-09-24 09:55:50 +0200229 mtdcr (UIC0SR, 0xfc000000); /* clear all */
230 mtdcr (UIC0ER, 0x00000000); /* disable all */
231 mtdcr (UIC0CR, 0x00000000); /* all non-critical */
232 mtdcr (UIC0PR, 0xfc000000);
233 mtdcr (UIC0TR, 0x00000000);
234 mtdcr (UIC0VR, 0x00000001);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200235
236 fpga_init();
237
238 return 0;
239}
240
Stefan Roeseb79316f2005-08-15 12:31:23 +0200241/*************************************************************************
242 * checkboard
243 *
244 * Dump pertinent info to the console
Stefan Roeseb79316f2005-08-15 12:31:23 +0200245 ************************************************************************/
246int checkboard (void)
247{
248 sys_info_t sysinfo;
249 unsigned char brd_rev, brd_id;
250 unsigned short sernum;
251 unsigned char opto_rev, opto_id;
252 OPTO_FPGA_REGS_ST *opto_ps;
253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
Stefan Roeseb79316f2005-08-15 12:31:23 +0200255
256 opto_rev = (unsigned char)((opto_ps->revision_ul &
257 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
258 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
259
260 opto_id = (unsigned char)((opto_ps->revision_ul &
261 SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_MASK)
262 >> SAND_HAL_XC_XCVR_CNTL_REVISION_IDENTIFICATION_SHIFT);
263
264 brd_rev = (unsigned char)((opto_ps->boardinfo_ul &
265 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_MASK)
266 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_REV_SHIFT);
267
268 brd_id = (unsigned char)((opto_ps->boardinfo_ul &
269 SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_MASK)
270 >> SAND_HAL_XC_XCVR_CNTL_BRD_INFO_BRD_ID_SHIFT);
271
272 get_sys_info (&sysinfo);
273
274 sernum = sbcommon_get_serial_number();
275 printf ("Board: Sandburst Corporation MetroBox Serial Number: %d\n", sernum);
276 printf ("%s\n", METROBOX_U_BOOT_REL_STR);
277
Peter Tyser561858e2008-11-03 09:30:59 -0600278 printf ("Built %s %s by %s\n", U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200279 if (sbcommon_get_master()) {
280 printf("Slot 0 - Master\nSlave board");
281 if (sbcommon_secondary_present())
282 printf(" present\n");
283 else
284 printf(" not detected\n");
285 } else {
286 printf("Slot 1 - Slave\n\n");
287 }
288
289 printf ("OptoFPGA ID:\t0x%02X\tRev: 0x%02X\n", opto_id, opto_rev);
Wolfgang Denkbde63582008-07-11 22:56:11 +0200290 printf ("Board Rev:\t0x%02X\tID: %s\n", brd_rev, board_id_as[brd_id].name);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200291
Stefan Roeseb79316f2005-08-15 12:31:23 +0200292 /* Fix the ack in the bme 32 */
293 udelay(5000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294 out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200295 asm("eieio");
296
297
298 return (0);
299}
300
Stefan Roeseb79316f2005-08-15 12:31:23 +0200301/*************************************************************************
302 * misc_init_f
303 *
304 * Initialize I2C bus one to gain access to the fans
Stefan Roeseb79316f2005-08-15 12:31:23 +0200305 ************************************************************************/
306int misc_init_f (void)
307{
308 /* Turn on i2c bus 1 */
309 puts ("I2C1: ");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310 i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200311 puts ("ready\n");
312
313 /* Turn on fans */
314 sbcommon_fans();
315
316 return (0);
317}
Wolfgang Denk3d078ce2005-08-15 16:03:56 +0200318
Stefan Roeseb79316f2005-08-15 12:31:23 +0200319/*************************************************************************
320 * misc_init_r
321 *
322 * Do nothing.
Stefan Roeseb79316f2005-08-15 12:31:23 +0200323 ************************************************************************/
324int misc_init_r (void)
325{
326 unsigned short sernum;
327 char envstr[255];
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500328 uchar enetaddr[6];
Stefan Roeseb79316f2005-08-15 12:31:23 +0200329 unsigned char opto_rev;
330 OPTO_FPGA_REGS_ST *opto_ps;
331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
Stefan Roeseb79316f2005-08-15 12:31:23 +0200333
334 if(NULL != getenv("secondserial")) {
335 puts("secondserial is set, switching to second serial port\n");
336 setenv("stderr", "serial1");
337 setenv("stdout", "serial1");
338 setenv("stdin", "serial1");
339 }
340
341 setenv("ubrelver", METROBOX_U_BOOT_REL_STR);
342
343 memset(envstr, 0, 255);
Peter Tyser561858e2008-11-03 09:30:59 -0600344 sprintf (envstr, "Built %s %s by %s",
345 U_BOOT_DATE, U_BOOT_TIME, BUILDUSER);
Stefan Roeseb79316f2005-08-15 12:31:23 +0200346 setenv("bldstr", envstr);
347 saveenv();
348
349 if( getenv("autorecover")) {
350 setenv("autorecover", NULL);
351 saveenv();
352 sernum = sbcommon_get_serial_number();
353
354 printf("\nSetting up environment for automatic filesystem recovery\n");
355 /*
356 * Setup default bootargs
357 */
358 memset(envstr, 0, 255);
359 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
360 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
361 sernum, sernum);
362 setenv("bootargs", envstr);
363
364 /*
365 * Setup Default boot command
366 */
367 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
368 "fatload ide 0 8100000 pramdisk;"
369 "bootm 8000000 8100000");
370
371 printf("Done. Please type allow the system to continue to boot\n");
372 }
373
374 if( getenv("fakeled")) {
375 setenv("bootdelay", "-1");
376 saveenv();
377 printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
378 opto_rev = (unsigned char)((opto_ps->revision_ul &
379 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
380 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
381
382 if(0x12 <= opto_rev) {
383 opto_ps->control_ul &= ~ SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_MASK;
384 }
385 }
386
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500387#ifdef CONFIG_HAS_ETH0
388 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
389 board_get_enetaddr(0, enetaddr);
Mike Frysinger0baeca42009-03-26 11:17:41 -0400390 eth_setenv_enetaddr("ethaddr", enetaddr);
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500391 }
392#endif
393
394#ifdef CONFIG_HAS_ETH1
395 if (!eth_getenv_enetaddr("eth1addr", enetaddr)) {
396 board_get_enetaddr(1, enetaddr);
Mike Frysinger0baeca42009-03-26 11:17:41 -0400397 eth_setenv_enetaddr("eth1addr", enetaddr);
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500398 }
399#endif
400
401#ifdef CONFIG_HAS_ETH2
402 if (!eth_getenv_enetaddr("eth2addr", enetaddr)) {
403 board_get_enetaddr(2, enetaddr);
Mike Frysinger0baeca42009-03-26 11:17:41 -0400404 eth_setenv_enetaddr("eth2addr", enetaddr);
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500405 }
406#endif
407
408#ifdef CONFIG_HAS_ETH3
409 if (!eth_getenv_enetaddr("eth3addr", enetaddr)) {
410 board_get_enetaddr(3, enetaddr);
Mike Frysinger0baeca42009-03-26 11:17:41 -0400411 eth_setenv_enetaddr("eth3addr", enetaddr);
Mike Frysingerd8d21e62009-02-16 18:03:14 -0500412 }
413#endif
414
Stefan Roeseb79316f2005-08-15 12:31:23 +0200415 return (0);
416}
417
Stefan Roeseb79316f2005-08-15 12:31:23 +0200418/*************************************************************************
419 * ide_set_reset
Stefan Roeseb79316f2005-08-15 12:31:23 +0200420 ************************************************************************/
421#ifdef CONFIG_IDE_RESET
422void ide_set_reset(int on)
423{
424 OPTO_FPGA_REGS_ST *opto_ps;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
Stefan Roeseb79316f2005-08-15 12:31:23 +0200426
427 if (on) { /* assert RESET */
428 opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
429 } else { /* release RESET */
430 opto_ps->reset_ul |= SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
431 }
432}
433#endif /* CONFIG_IDE_RESET */
434
435/*************************************************************************
436 * fpga_init
Stefan Roeseb79316f2005-08-15 12:31:23 +0200437 ************************************************************************/
438void fpga_init(void)
439{
440 OPTO_FPGA_REGS_ST *opto_ps;
441 unsigned char opto_rev;
442 unsigned long tmp;
443
444 /* Ensure we have power all around */
445 udelay(500);
446
447 /*
448 * Take appropriate hw bits out of reset
449 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450 opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
Stefan Roeseb79316f2005-08-15 12:31:23 +0200451
452 tmp =
453 SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
454 SAND_HAL_XC_XCVR_CNTL_RESET_MAC0_RESET_N_MASK |
455 SAND_HAL_XC_XCVR_CNTL_RESET_BME_RESET_N_MASK |
456 SAND_HAL_XC_XCVR_CNTL_RESET_ACE_RESET_N_MASK |
457 SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK |
458 SAND_HAL_XC_XCVR_CNTL_RESET_QE_A_RESET_N_MASK |
459 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_A_RESET_N_MASK |
460 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_A_RESET_N_MASK |
461 SAND_HAL_XC_XCVR_CNTL_RESET_QE_B_RESET_N_MASK |
462 SAND_HAL_XC_XCVR_CNTL_RESET_IFE_B_RESET_N_MASK |
463 SAND_HAL_XC_XCVR_CNTL_RESET_EFE_B_RESET_N_MASK |
464 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK1_RESET_N_MASK |
465 SAND_HAL_XC_XCVR_CNTL_RESET_LOCK0_RESET_N_MASK |
466 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX1_RESET_N_MASK |
467 SAND_HAL_XC_XCVR_CNTL_RESET_I2C_MUX0_RESET_N_MASK |
468 SAND_HAL_XC_XCVR_CNTL_RESET_PHY0_RESET_N_MASK |
469 SAND_HAL_XC_XCVR_CNTL_RESET_PHY1_RESET_N_MASK |
470 SAND_HAL_XC_XCVR_CNTL_RESET_SLAVE_RESET_N_MASK;
471 opto_ps->reset_ul = tmp;
472 /*
473 * Turn on the 'Slow Blink' for the System Error Led.
474 * Ensure FPGA rev is up to at least rev 0x12
475 */
476 opto_rev = (unsigned char)((opto_ps->revision_ul &
477 SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
478 >> SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_SHIFT);
479 if(0x12 <= opto_rev) {
480 opto_ps->control_ul |= 1 << SAND_HAL_XC_XCVR_CNTL_CNTL_ERROR_LED_SHIFT;
481 }
482
483 asm("eieio");
484
485 return;
486}
487
Stefan Roeseb79316f2005-08-15 12:31:23 +0200488int metroboxSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
489{
490 unsigned short sernum;
491 char envstr[255];
492
493 sernum = sbcommon_get_serial_number();
494
495 memset(envstr, 0, 255);
496 /*
497 * Setup our ip address
498 */
499 sprintf(envstr, "10.100.60.%d", sernum);
500
501 setenv("ipaddr", envstr);
502 /*
503 * Setup the host ip address
504 */
505 setenv("serverip", "10.100.17.10");
506
507 /*
508 * Setup default bootargs
509 */
510 memset(envstr, 0, 255);
511
512 sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
513 "rw nfsroot=10.100.17.10:/home/metrobox/mbc%d "
514 "nfsaddrs=10.100.60.%d:10.100.17.10:10.100.1.1"
515 ":255.255.0.0:metrobox%d.sandburst.com:eth0:none idebus=33",
516 sernum, sernum, sernum);
517
518 setenv("bootargs_nfs", envstr);
519 setenv("bootargs", envstr);
520
521 /*
522 * Setup CF bootargs
523 */
524 memset(envstr, 0, 255);
525 sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
526 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none idebus=33",
527 sernum, sernum);
528
529 setenv("bootargs_cf", envstr);
530
531 /*
532 * Setup Default boot command
533 */
534 setenv("bootcmd_tftp", "tftp 8000000 pImage.metrobox;bootm 8000000");
535 setenv("bootcmd", "tftp 8000000 pImage.metrobox;bootm 8000000");
536
537 /*
538 * Setup compact flash boot command
539 */
540 setenv("bootcmd_cf", "fatload ide 0 8000000 pimage.metrobox;bootm 8000000");
541
542 saveenv();
543
544
545 return(1);
546}
547
Stefan Roeseb79316f2005-08-15 12:31:23 +0200548int metroboxRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
549{
550 unsigned short sernum;
551 char envstr[255];
552
553 sernum = sbcommon_get_serial_number();
554
555 printf("\nSetting up environment for filesystem recovery\n");
556 /*
557 * Setup default bootargs
558 */
559 memset(envstr, 0, 255);
560 sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
561 "rw ip=10.100.60.%d:::255.255.0.0:metrobox%d:eth0:none",
562 sernum, sernum);
563
564 setenv("bootargs", envstr);
565
566 /*
567 * Setup Default boot command
568 */
569 setenv("bootcmd", "fatload ide 0 8000000 pimage.metrobox;"
570 "fatload ide 0 8100000 pramdisk;"
571 "bootm 8000000 8100000");
572
573 printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
574 " please type fsrecover.sh<cr>\n");
575
576 return(1);
577}
578
Stefan Roeseb79316f2005-08-15 12:31:23 +0200579U_BOOT_CMD(mbsetup, 1, 1, metroboxSetupVars,
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200580 "Set environment to factory defaults", "");
Stefan Roeseb79316f2005-08-15 12:31:23 +0200581
582U_BOOT_CMD(mbrecover, 1, 1, metroboxRecover,
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200583 "Set environment to allow for fs recovery", "");