| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Interrupt vector number definitions to ease the |
| 25 | * 405 -- 440 porting pain ;-) |
| 26 | * |
| 27 | * NOTE: They're not all here yet ... update as needed. |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | #ifndef _VECNUMS_H_ |
| 32 | #define _VECNUMS_H_ |
| 33 | |
| Stefan Roese | 854bc8d | 2006-09-13 13:51:58 +0200 | [diff] [blame] | 34 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
| Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 35 | |
| 36 | /* UIC 0 */ |
| 37 | #define VECNUM_U0 0 /* UART 0 */ |
| 38 | #define VECNUM_U1 1 /* UART 1 */ |
| 39 | #define VECNUM_IIC0 2 /* IIC */ |
| 40 | #define VECNUM_KRD 3 /* Kasumi Ready for data */ |
| 41 | #define VECNUM_KDA 4 /* Kasumi Data Available */ |
| 42 | #define VECNUM_PCRW 5 /* PCI command register write */ |
| 43 | #define VECNUM_PPM 6 /* PCI power management */ |
| 44 | #define VECNUM_IIC1 7 /* IIC */ |
| 45 | #define VECNUM_SPI 8 /* SPI */ |
| 46 | #define VECNUM_EPCISER 9 /* External PCI SERR */ |
| 47 | #define VECNUM_MTE 10 /* MAL TXEOB */ |
| 48 | #define VECNUM_MRE 11 /* MAL RXEOB */ |
| 49 | #define VECNUM_D0 12 /* DMA channel 0 */ |
| 50 | #define VECNUM_D1 13 /* DMA channel 1 */ |
| 51 | #define VECNUM_D2 14 /* DMA channel 2 */ |
| 52 | #define VECNUM_D3 15 /* DMA channel 3 */ |
| 53 | #define VECNUM_UD0 16 /* UDMA irq 0 */ |
| 54 | #define VECNUM_UD1 17 /* UDMA irq 1 */ |
| 55 | #define VECNUM_UD2 18 /* UDMA irq 2 */ |
| 56 | #define VECNUM_UD3 19 /* UDMA irq 3 */ |
| 57 | #define VECNUM_HSB2D 20 /* USB2.0 Device */ |
| 58 | #define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */ |
| 59 | #define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */ |
| 60 | #define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */ |
| 61 | #define VECNUM_EIP94 23 /* Security EIP94 */ |
| 62 | #define VECNUM_ETH0 24 /* Emac 0 */ |
| 63 | #define VECNUM_ETH1 25 /* Emac 1 */ |
| 64 | #define VECNUM_EHCI 26 /* USB2.0 Host EHCI */ |
| 65 | #define VECNUM_EIR4 27 /* External interrupt 4 */ |
| 66 | #define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */ |
| 67 | #define VECNUM_UIC2C 29 /* UIC2 critical interrupt */ |
| 68 | #define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ |
| 69 | #define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ |
| 70 | |
| 71 | /* UIC 1 */ |
| 72 | #define VECNUM_MS (32 + 0) /* MAL SERR */ |
| 73 | #define VECNUM_MTDE (32 + 1) /* MAL TXDE */ |
| 74 | #define VECNUM_MRDE (32 + 2) /* MAL RXDE */ |
| 75 | #define VECNUM_U2 (32 + 3) /* UART 2 */ |
| 76 | #define VECNUM_U3 (32 + 4) /* UART 3 */ |
| 77 | #define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */ |
| 78 | #define VECNUM_NDFC (32 + 6) /* NDFC */ |
| 79 | #define VECNUM_KSLE (32 + 7) /* KASUMI slave error */ |
| 80 | #define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */ |
| 81 | #define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */ |
| 82 | #define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */ |
| 83 | #define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */ |
| 84 | #define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */ |
| 85 | #define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */ |
| 86 | #define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */ |
| 87 | #define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */ |
| 88 | #define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */ |
| 89 | #define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */ |
| 90 | #define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */ |
| 91 | #define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */ |
| 92 | #define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */ |
| 93 | #define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */ |
| 94 | #define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */ |
| 95 | #define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */ |
| 96 | #define VECNUM_SRE (32 + 24) /* Serial ROM error */ |
| 97 | #define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */ |
| 98 | #define VECNUM_RSVD0 (32 + 26) /* Reserved */ |
| 99 | #define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */ |
| 100 | #define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */ |
| 101 | #define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ |
| 102 | #define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */ |
| 103 | #define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */ |
| 104 | |
| 105 | #define VECNUM_TXDE VECNUM_MTDE |
| 106 | #define VECNUM_RXDE VECNUM_MRDE |
| 107 | |
| 108 | /* UIC 2 */ |
| 109 | #define VECNUM_EIR5 (62 + 0) /* External interrupt 5 */ |
| 110 | #define VECNUM_EIR6 (62 + 1) /* External interrupt 6 */ |
| 111 | #define VECNUM_OPB (62 + 2) /* OPB to PLB bridge int stat */ |
| 112 | #define VECNUM_EIR2 (62 + 3) /* External interrupt 2 */ |
| 113 | #define VECNUM_EIR3 (62 + 4) /* External interrupt 3 */ |
| 114 | #define VECNUM_DDR2 (62 + 5) /* DDR2 sdram */ |
| 115 | #define VECNUM_MCTX0 (62 + 6) /* MAl intp coalescence TX0 */ |
| 116 | #define VECNUM_MCTX1 (62 + 7) /* MAl intp coalescence TX1 */ |
| 117 | #define VECNUM_MCTR0 (62 + 8) /* MAl intp coalescence TR0 */ |
| 118 | #define VECNUM_MCTR1 (62 + 9) /* MAl intp coalescence TR1 */ |
| 119 | |
| 120 | #elif defined(CONFIG_440SPE) |
| 121 | |
| Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 122 | /* UIC 0 */ |
| 123 | #define VECNUM_U0 0 /* UART0 */ |
| 124 | #define VECNUM_U1 1 /* UART1 */ |
| 125 | #define VECNUM_IIC0 2 /* IIC0 */ |
| 126 | #define VECNUM_IIC1 3 /* IIC1 */ |
| 127 | #define VECNUM_PIM 4 /* PCI inbound message */ |
| 128 | #define VECNUM_PCRW 5 /* PCI command reg write */ |
| 129 | #define VECNUM_PPM 6 /* PCI power management */ |
| 130 | #define VECNUM_MSI0 7 /* PCI MSI level 0 */ |
| 131 | #define VECNUM_MSI1 8 /* PCI MSI level 0 */ |
| 132 | #define VECNUM_MSI2 9 /* PCI MSI level 0 */ |
| 133 | #define VECNUM_D0 12 /* DMA channel 0 */ |
| 134 | #define VECNUM_D1 13 /* DMA channel 1 */ |
| 135 | #define VECNUM_D2 14 /* DMA channel 2 */ |
| 136 | #define VECNUM_D3 15 /* DMA channel 3 */ |
| 137 | #define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ |
| 138 | #define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ |
| 139 | |
| 140 | /* UIC 1 */ |
| 141 | #define VECNUM_MS (32 + 1 ) /* MAL SERR */ |
| 142 | #define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */ |
| 143 | #define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */ |
| 144 | #define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */ |
| 145 | #define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */ |
| 146 | #define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */ |
| 147 | #define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */ |
| 148 | #define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */ |
| 149 | #define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */ |
| 150 | #define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */ |
| 151 | #define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ |
| 152 | #define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ |
| 153 | |
| 154 | /* UIC 2 */ |
| 155 | #define VECNUM_EIR5 (62 + 24) /* External interrupt 5 */ |
| 156 | #define VECNUM_EIR4 (62 + 25) /* External interrupt 4 */ |
| 157 | #define VECNUM_EIR3 (62 + 26) /* External interrupt 3 */ |
| 158 | #define VECNUM_EIR2 (62 + 27) /* External interrupt 2 */ |
| 159 | #define VECNUM_EIR1 (62 + 28) /* External interrupt 1 */ |
| 160 | #define VECNUM_EIR0 (62 + 29) /* External interrupt 0 */ |
| 161 | |
| 162 | #elif defined(CONFIG_440SP) |
| Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 163 | |
| 164 | /* UIC 0 */ |
| 165 | #define VECNUM_U0 0 /* UART0 */ |
| 166 | #define VECNUM_U1 1 /* UART1 */ |
| 167 | #define VECNUM_IIC0 2 /* IIC0 */ |
| 168 | #define VECNUM_IIC1 3 /* IIC1 */ |
| 169 | #define VECNUM_PIM 4 /* PCI inbound message */ |
| 170 | #define VECNUM_PCRW 5 /* PCI command reg write */ |
| 171 | #define VECNUM_PPM 6 /* PCI power management */ |
| 172 | #define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ |
| 173 | #define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ |
| 174 | |
| 175 | /* UIC 1 */ |
| 176 | #define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */ |
| 177 | #define VECNUM_MS (32 + 1) /* MAL SERR */ |
| 178 | #define VECNUM_TXDE (32 + 2) /* MAL TXDE */ |
| 179 | #define VECNUM_RXDE (32 + 3) /* MAL RXDE */ |
| 180 | #define VECNUM_MTE (32 + 6) /* MAL Tx EOB */ |
| 181 | #define VECNUM_MRE (32 + 7) /* MAL Rx EOB */ |
| 182 | #define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */ |
| 183 | #define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */ |
| 184 | #define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */ |
| 185 | #define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */ |
| 186 | #define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */ |
| 187 | #define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */ |
| 188 | #define VECNUM_EWU0 (32 + 29) /* Emac wakeup */ |
| 189 | |
| 190 | #elif defined(CONFIG_440) |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 191 | |
| 192 | /* UIC 0 */ |
| 193 | #define VECNUM_U0 0 /* UART0 */ |
| 194 | #define VECNUM_U1 1 /* UART1 */ |
| 195 | #define VECNUM_IIC0 2 /* IIC0 */ |
| 196 | #define VECNUM_IIC1 3 /* IIC1 */ |
| 197 | #define VECNUM_PIM 4 /* PCI inbound message */ |
| 198 | #define VECNUM_PCRW 5 /* PCI command reg write */ |
| 199 | #define VECNUM_PPM 6 /* PCI power management */ |
| 200 | #define VECNUM_MSI0 7 /* PCI MSI level 0 */ |
| 201 | #define VECNUM_MSI1 8 /* PCI MSI level 0 */ |
| 202 | #define VECNUM_MSI2 9 /* PCI MSI level 0 */ |
| 203 | #define VECNUM_MTE 10 /* MAL TXEOB */ |
| 204 | #define VECNUM_MRE 11 /* MAL RXEOB */ |
| 205 | #define VECNUM_D0 12 /* DMA channel 0 */ |
| 206 | #define VECNUM_D1 13 /* DMA channel 1 */ |
| 207 | #define VECNUM_D2 14 /* DMA channel 2 */ |
| 208 | #define VECNUM_D3 15 /* DMA channel 3 */ |
| 209 | #define VECNUM_CT0 18 /* GPT compare timer 0 */ |
| 210 | #define VECNUM_CT1 19 /* GPT compare timer 1 */ |
| 211 | #define VECNUM_CT2 20 /* GPT compare timer 2 */ |
| 212 | #define VECNUM_CT3 21 /* GPT compare timer 3 */ |
| 213 | #define VECNUM_CT4 22 /* GPT compare timer 4 */ |
| 214 | #define VECNUM_EIR0 23 /* External interrupt 0 */ |
| 215 | #define VECNUM_EIR1 24 /* External interrupt 1 */ |
| 216 | #define VECNUM_EIR2 25 /* External interrupt 2 */ |
| 217 | #define VECNUM_EIR3 26 /* External interrupt 3 */ |
| 218 | #define VECNUM_EIR4 27 /* External interrupt 4 */ |
| 219 | #define VECNUM_EIR5 28 /* External interrupt 5 */ |
| 220 | #define VECNUM_EIR6 29 /* External interrupt 6 */ |
| 221 | #define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */ |
| 222 | #define VECNUM_UIC1C 31 /* UIC1 critical interrupt */ |
| 223 | |
| 224 | /* UIC 1 */ |
| 225 | #define VECNUM_MS (32 + 0 ) /* MAL SERR */ |
| 226 | #define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */ |
| 227 | #define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */ |
| Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 228 | #define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */ |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 229 | #define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */ |
| 230 | #define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */ |
| 231 | |
| 232 | #else /* !defined(CONFIG_440) */ |
| 233 | |
| Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 234 | #if defined(CONFIG_405EZ) |
| 235 | #define VECNUM_D0 0 /* DMA channel 0 */ |
| 236 | #define VECNUM_D1 1 /* DMA channel 1 */ |
| 237 | #define VECNUM_D2 2 /* DMA channel 2 */ |
| 238 | #define VECNUM_D3 3 /* DMA channel 3 */ |
| 239 | #define VECNUM_1588 4 /* IEEE 1588 network synchronization */ |
| 240 | #define VECNUM_U0 5 /* UART0 */ |
| 241 | #define VECNUM_U1 6 /* UART1 */ |
| 242 | #define VECNUM_CAN0 7 /* CAN 0 */ |
| 243 | #define VECNUM_CAN1 8 /* CAN 1 */ |
| 244 | #define VECNUM_SPI 9 /* SPI */ |
| 245 | #define VECNUM_IIC0 10 /* I2C */ |
| 246 | #define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ |
| 247 | #define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ |
| 248 | #define VECNUM_USBH1 13 /* USB Host 1 */ |
| 249 | #define VECNUM_USBH2 14 /* USB Host 2 */ |
| 250 | #define VECNUM_USBDEV 15 /* USB Device */ |
| 251 | #define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ |
| 252 | #define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ |
| 253 | |
| 254 | #define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ |
| 255 | #define VECNUM_MS 18 /* MAL_SERR_INT */ |
| 256 | #define VECNUM_TXDE 18 /* MAL_TXDE_INT */ |
| 257 | #define VECNUM_RXDE 18 /* MAL_RXDE_INT */ |
| 258 | |
| 259 | #define VECNUM_MTE 19 /* MAL TXEOB */ |
| 260 | #define VECNUM_MTE1 20 /* MAL TXEOB1 */ |
| 261 | #define VECNUM_MRE 21 /* MAL RXEOB */ |
| 262 | #define VECNUM_NAND 22 /* NAND Flash controller */ |
| 263 | #define VECNUM_ADC 23 /* ADC */ |
| 264 | #define VECNUM_DAC 24 /* DAC */ |
| 265 | #define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ |
| 266 | #define VECNUM_RESERVED0 26 /* Reserved */ |
| 267 | #define VECNUM_EIR0 27 /* External interrupt 0 */ |
| 268 | #define VECNUM_EIR1 28 /* External interrupt 1 */ |
| 269 | #define VECNUM_EIR2 29 /* External interrupt 2 */ |
| 270 | #define VECNUM_EIR3 30 /* External interrupt 3 */ |
| 271 | #define VECNUM_EIR4 31 /* External interrupt 4 */ |
| 272 | |
| Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame] | 273 | #elif defined(CONFIG_405EX) |
| 274 | |
| 275 | /* UIC 0 */ |
| 276 | #define VECNUM_U0 00 |
| 277 | #define VECNUM_U1 01 |
| 278 | #define VECNUM_IIC0 02 |
| 279 | #define VECNUM_PKA 03 |
| 280 | #define VECNUM_TRNG 04 |
| 281 | #define VECNUM_EBM 05 |
| 282 | #define VECNUM_BGI 06 |
| 283 | #define VECNUM_IIC1 07 |
| 284 | #define VECNUM_SPI 08 |
| 285 | #define VECNUM_EIR0 09 |
| 286 | #define VECNUM_MTE 10 /* MAL Tx EOB */ |
| 287 | #define VECNUM_MRE 11 /* MAL Rx EOB */ |
| 288 | #define VECNUM_DMA0 12 |
| 289 | #define VECNUM_DMA1 13 |
| 290 | #define VECNUM_DMA2 14 |
| 291 | #define VECNUM_DMA3 15 |
| 292 | #define VECNUM_PCIE0AL 16 |
| 293 | #define VECNUM_PCIE0VPD 17 |
| 294 | #define VECNUM_RPCIE0HRST 18 |
| 295 | #define VECNUM_FPCIE0HRST 19 |
| 296 | #define VECNUM_PCIE0TCR 20 |
| 297 | #define VECNUM_PCIEMSI0 21 |
| 298 | #define VECNUM_PCIEMSI1 22 |
| 299 | #define VECNUM_SECURITY 23 |
| 300 | #define VECNUM_ETH0 24 |
| 301 | #define VECNUM_ETH1 25 |
| 302 | #define VECNUM_PCIEMSI2 26 |
| 303 | #define VECNUM_EIR4 27 |
| 304 | #define VECNUM_UIC2NC 28 |
| 305 | #define VECNUM_UIC2C 29 |
| 306 | #define VECNUM_UIC1NC 30 |
| 307 | #define VECNUM_UIC1C 31 |
| 308 | |
| 309 | /* UIC 1 */ |
| 310 | #define VECNUM_MS (32 + 00) /* MAL SERR */ |
| 311 | #define VECNUM_TXDE (32 + 01) /* MAL TXDE */ |
| 312 | #define VECNUM_RXDE (32 + 02) /* MAL RXDE */ |
| 313 | #define VECNUM_PCIE0BMVC0 (32 + 03) |
| 314 | #define VECNUM_PCIE0DCRERR (32 + 04) |
| 315 | #define VECNUM_EBC (32 + 05) |
| 316 | #define VECNUM_NDFC (32 + 06) |
| 317 | #define VECNUM_PCEI1DCRERR (32 + 07) |
| 318 | #define VECNUM_CT8 (32 + 08) |
| 319 | #define VECNUM_CT9 (32 + 09) |
| 320 | #define VECNUM_PCIE1AL (32 + 10) |
| 321 | #define VECNUM_PCIE1VPD (32 + 11) |
| 322 | #define VECNUM_RPCE1HRST (32 + 12) |
| 323 | #define VECNUM_FPCE1HRST (32 + 13) |
| 324 | #define VECNUM_PCIE1TCR (32 + 14) |
| 325 | #define VECNUM_PCIE1VC0 (32 + 15) |
| 326 | #define VECNUM_CT3 (32 + 16) |
| 327 | #define VECNUM_CT4 (32 + 17) |
| 328 | #define VECNUM_EIR7 (32 + 18) |
| 329 | #define VECNUM_EIR8 (32 + 19) |
| 330 | #define VECNUM_EIR9 (32 + 20) |
| 331 | #define VECNUM_CT5 (32 + 21) |
| 332 | #define VECNUM_CT6 (32 + 22) |
| 333 | #define VECNUM_CT7 (32 + 23) |
| 334 | #define VECNUM_SROM (32 + 24) /* SERIAL ROM */ |
| 335 | #define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ |
| 336 | #define VECNUM_EIR2 (32 + 26) |
| 337 | #define VECNUM_EIR5 (32 + 27) |
| 338 | #define VECNUM_EIR6 (32 + 28) |
| 339 | #define VECNUM_EMAC0WAKE (32 + 29) |
| 340 | #define VECNUM_EIR1 (32 + 30) |
| 341 | #define VECNUM_EMAC1WAKE (32 + 31) |
| 342 | |
| 343 | /* UIC 2 */ |
| 344 | #define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ |
| 345 | #define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ |
| 346 | #define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */ |
| 347 | #define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */ |
| 348 | #define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */ |
| 349 | #define VECNUM_DDRMCUE (64 + 05) |
| 350 | #define VECNUM_DDRMCCE (64 + 06) |
| 351 | #define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */ |
| 352 | #define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */ |
| 353 | #define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */ |
| 354 | #define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */ |
| 355 | #define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */ |
| 356 | #define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */ |
| 357 | #define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */ |
| 358 | #define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */ |
| 359 | #define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */ |
| 360 | #define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */ |
| 361 | #define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */ |
| 362 | #define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */ |
| 363 | #define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */ |
| 364 | #define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */ |
| 365 | #define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */ |
| 366 | #define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */ |
| 367 | #define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */ |
| 368 | #define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */ |
| 369 | #define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */ |
| 370 | #define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */ |
| 371 | #define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */ |
| 372 | #define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */ |
| 373 | #define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */ |
| 374 | #define VECNUM_USBWAKE (64 + 30) /* USB wakup */ |
| 375 | #define VECNUM_USBOTG (64 + 31) /* USB OTG */ |
| 376 | |
| Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 377 | #else /* !CONFIG_405EZ */ |
| 378 | |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 379 | #define VECNUM_U0 0 /* UART0 */ |
| 380 | #define VECNUM_U1 1 /* UART1 */ |
| 381 | #define VECNUM_D0 5 /* DMA channel 0 */ |
| 382 | #define VECNUM_D1 6 /* DMA channel 1 */ |
| 383 | #define VECNUM_D2 7 /* DMA channel 2 */ |
| 384 | #define VECNUM_D3 8 /* DMA channel 3 */ |
| 385 | #define VECNUM_EWU0 9 /* Ethernet wakeup */ |
| 386 | #define VECNUM_MS 10 /* MAL SERR */ |
| 387 | #define VECNUM_MTE 11 /* MAL TXEOB */ |
| 388 | #define VECNUM_MRE 12 /* MAL RXEOB */ |
| 389 | #define VECNUM_TXDE 13 /* MAL TXDE */ |
| 390 | #define VECNUM_RXDE 14 /* MAL RXDE */ |
| 391 | #define VECNUM_ETH0 15 /* Ethernet interrupt status */ |
| 392 | #define VECNUM_EIR0 25 /* External interrupt 0 */ |
| 393 | #define VECNUM_EIR1 26 /* External interrupt 1 */ |
| 394 | #define VECNUM_EIR2 27 /* External interrupt 2 */ |
| 395 | #define VECNUM_EIR3 28 /* External interrupt 3 */ |
| 396 | #define VECNUM_EIR4 29 /* External interrupt 4 */ |
| 397 | #define VECNUM_EIR5 30 /* External interrupt 5 */ |
| 398 | #define VECNUM_EIR6 31 /* External interrupt 6 */ |
| Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 399 | #endif /* defined(CONFIG_405EZ) */ |
| wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 400 | |
| 401 | #endif /* defined(CONFIG_440) */ |
| 402 | |
| 403 | #endif /* _VECNUMS_H_ */ |