Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 1 | /* |
Zhao Chenhui | d5c784e | 2011-08-24 13:20:06 +0800 | [diff] [blame] | 2 | * Copyright 2007,2009-2011 Freescale Semiconductor, Inc. |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 3 | * |
Wolfgang Denk | 3765b3e | 2013-10-07 13:07:26 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 5 | */ |
Jon Loeliger | c9974ab | 2008-01-04 11:58:23 -0600 | [diff] [blame] | 6 | |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 7 | #include <common.h> |
| 8 | #include <command.h> |
| 9 | #include <pci.h> |
| 10 | #include <asm/processor.h> |
| 11 | #include <asm/immap_86xx.h> |
Kumar Gala | c851462 | 2009-04-02 13:22:48 -0500 | [diff] [blame] | 12 | #include <asm/fsl_pci.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 13 | #include <fsl_ddr_sdram.h> |
Kumar Gala | 5d27e02 | 2010-12-15 04:55:20 -0600 | [diff] [blame] | 14 | #include <asm/fsl_serdes.h> |
Jon Loeliger | c9974ab | 2008-01-04 11:58:23 -0600 | [diff] [blame] | 15 | #include <i2c.h> |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 16 | #include <asm/io.h> |
Jon Loeliger | 1df170f | 2008-01-04 12:07:27 -0600 | [diff] [blame] | 17 | #include <libfdt.h> |
| 18 | #include <fdt_support.h> |
Jon Loeliger | a30a549 | 2008-03-04 10:03:03 -0600 | [diff] [blame] | 19 | #include <spd_sdram.h> |
Ben Warren | 89973f8 | 2008-08-31 22:22:04 -0700 | [diff] [blame] | 20 | #include <netdev.h> |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 21 | |
Simon Glass | 088454c | 2017-03-31 08:40:25 -0600 | [diff] [blame^] | 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 24 | void sdram_init(void); |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 25 | phys_size_t fixed_sdram(void); |
Timur Tabi | e69e520 | 2010-08-31 19:56:43 -0500 | [diff] [blame] | 26 | int mpc8610hpcd_diu_init(void); |
Jon Loeliger | c9974ab | 2008-01-04 11:58:23 -0600 | [diff] [blame] | 27 | |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 28 | |
| 29 | /* called before any console output */ |
| 30 | int board_early_init_f(void) |
| 31 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 33 | volatile ccsr_gur_t *gur = &immap->im_gur; |
| 34 | |
York Sun | a877880 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 35 | gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */ |
| 36 | |
| 37 | return 0; |
| 38 | } |
| 39 | |
| 40 | int misc_init_r(void) |
| 41 | { |
| 42 | u8 tmp_val, version; |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 43 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
York Sun | a877880 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 44 | |
| 45 | /*Do not use 8259PIC*/ |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 46 | tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); |
| 47 | out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); |
York Sun | a877880 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 48 | |
| 49 | /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 50 | version = in_8(pixis_base + PIXIS_PVER); |
York Sun | a877880 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 51 | if(version >= 0x07) { |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 52 | tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); |
| 53 | out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); |
York Sun | a877880 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | /* Using this for DIU init before the driver in linux takes over |
| 57 | * Enable the TFP410 Encoder (I2C address 0x38) |
| 58 | */ |
| 59 | |
| 60 | tmp_val = 0xBF; |
| 61 | i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); |
| 62 | /* Verify if enabled */ |
| 63 | tmp_val = 0; |
| 64 | i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); |
Marek Vasut | 7315ab2 | 2011-10-21 14:17:09 +0000 | [diff] [blame] | 65 | debug("DVI Encoder Read: 0x%02x\n", tmp_val); |
York Sun | a877880 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 66 | |
| 67 | tmp_val = 0x10; |
| 68 | i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); |
| 69 | /* Verify if enabled */ |
| 70 | tmp_val = 0; |
| 71 | i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); |
Marek Vasut | 7315ab2 | 2011-10-21 14:17:09 +0000 | [diff] [blame] | 72 | debug("DVI Encoder Read: 0x%02x\n", tmp_val); |
York Sun | a877880 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 73 | |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | int checkboard(void) |
| 78 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 79 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 80 | volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 81 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 82 | |
Timur Tabi | 26fd33b | 2011-04-28 13:41:20 -0500 | [diff] [blame] | 83 | printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, " |
| 84 | "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 85 | in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), |
| 86 | in_8(pixis_base + PIXIS_PVER)); |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 87 | |
Timur Tabi | 26fd33b | 2011-04-28 13:41:20 -0500 | [diff] [blame] | 88 | /* |
| 89 | * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot |
| 90 | * bank and LBMAP=00 is the alternate bank. However, the pixis |
| 91 | * altbank code can only set bits, not clear them, so we treat 00 as |
| 92 | * the normal bank and 11 as the alternate. |
| 93 | */ |
| 94 | switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) { |
| 95 | case 0: |
| 96 | puts("vBank: Standard\n"); |
| 97 | break; |
| 98 | case 0x40: |
| 99 | puts("Promjet\n"); |
| 100 | break; |
| 101 | case 0x80: |
| 102 | puts("NAND\n"); |
| 103 | break; |
| 104 | case 0xC0: |
| 105 | puts("vBank: Alternate\n"); |
| 106 | break; |
| 107 | } |
| 108 | |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 109 | mcm->abcr |= 0x00010000; /* 0 */ |
| 110 | mcm->hpmr3 = 0x80000008; /* 4c */ |
| 111 | mcm->hpmr0 = 0; |
| 112 | mcm->hpmr1 = 0; |
| 113 | mcm->hpmr2 = 0; |
| 114 | mcm->hpmr4 = 0; |
| 115 | mcm->hpmr5 = 0; |
| 116 | |
| 117 | return 0; |
| 118 | } |
| 119 | |
| 120 | |
Simon Glass | 088454c | 2017-03-31 08:40:25 -0600 | [diff] [blame^] | 121 | int initdram(void) |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 122 | { |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 123 | phys_size_t dram_size = 0; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 124 | |
| 125 | #if defined(CONFIG_SPD_EEPROM) |
Jon Loeliger | 39aa1a7 | 2008-08-26 15:01:36 -0500 | [diff] [blame] | 126 | dram_size = fsl_ddr_sdram(); |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 127 | #else |
| 128 | dram_size = fixed_sdram(); |
| 129 | #endif |
| 130 | |
Timur Tabi | 9ff32d8 | 2010-03-29 12:51:07 -0500 | [diff] [blame] | 131 | setup_ddr_bat(dram_size); |
| 132 | |
Wolfgang Denk | 21cd581 | 2011-07-25 10:13:53 +0200 | [diff] [blame] | 133 | debug(" DDR: "); |
Simon Glass | 088454c | 2017-03-31 08:40:25 -0600 | [diff] [blame^] | 134 | gd->ram_size = dram_size; |
| 135 | |
| 136 | return 0; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 140 | #if !defined(CONFIG_SPD_EEPROM) |
| 141 | /* |
| 142 | * Fixed sdram init -- doesn't use serial presence detect. |
| 143 | */ |
| 144 | |
Becky Bruce | 4c77de3 | 2008-10-31 17:13:32 -0500 | [diff] [blame] | 145 | phys_size_t fixed_sdram(void) |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 146 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 147 | #if !defined(CONFIG_SYS_RAMBOOT) |
| 148 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
York Sun | 9a17eb5 | 2013-11-18 10:29:32 -0800 | [diff] [blame] | 149 | struct ccsr_ddr __iomem *ddr = &immap->im_ddr1; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 150 | uint d_init; |
| 151 | |
| 152 | ddr->cs0_bnds = 0x0000001f; |
| 153 | ddr->cs0_config = 0x80010202; |
| 154 | |
Kumar Gala | 45239cf | 2008-04-29 10:27:08 -0500 | [diff] [blame] | 155 | ddr->timing_cfg_3 = 0x00000000; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 156 | ddr->timing_cfg_0 = 0x00260802; |
| 157 | ddr->timing_cfg_1 = 0x3935d322; |
| 158 | ddr->timing_cfg_2 = 0x14904cc8; |
Peter Tyser | e7ee23e | 2009-07-17 10:14:45 -0500 | [diff] [blame] | 159 | ddr->sdram_mode = 0x00480432; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 160 | ddr->sdram_mode_2 = 0x00000000; |
| 161 | ddr->sdram_interval = 0x06180fff; /* 0x06180100; */ |
| 162 | ddr->sdram_data_init = 0xDEADBEEF; |
| 163 | ddr->sdram_clk_cntl = 0x03800000; |
| 164 | ddr->sdram_cfg_2 = 0x04400010; |
| 165 | |
| 166 | #if defined(CONFIG_DDR_ECC) |
| 167 | ddr->err_int_en = 0x0000000d; |
| 168 | ddr->err_disable = 0x00000000; |
| 169 | ddr->err_sbe = 0x00010000; |
| 170 | #endif |
| 171 | asm("sync;isync"); |
| 172 | |
| 173 | udelay(500); |
| 174 | |
Peter Tyser | e7ee23e | 2009-07-17 10:14:45 -0500 | [diff] [blame] | 175 | ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/ |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 176 | |
| 177 | |
| 178 | #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 179 | d_init = 1; |
| 180 | debug("DDR - 1st controller: memory initializing\n"); |
| 181 | /* |
| 182 | * Poll until memory is initialized. |
| 183 | * 512 Meg at 400 might hit this 200 times or so. |
| 184 | */ |
| 185 | while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) |
| 186 | udelay(1000); |
| 187 | |
| 188 | debug("DDR: memory initialized\n\n"); |
| 189 | asm("sync; isync"); |
| 190 | udelay(500); |
| 191 | #endif |
| 192 | |
| 193 | return 512 * 1024 * 1024; |
| 194 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 195 | return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 196 | } |
| 197 | |
| 198 | #endif |
| 199 | |
| 200 | #if defined(CONFIG_PCI) |
| 201 | /* |
| 202 | * Initialize PCI Devices, report devices found. |
| 203 | */ |
| 204 | |
| 205 | #ifndef CONFIG_PCI_PNP |
| 206 | static struct pci_config_table pci_fsl86xxads_config_table[] = { |
| 207 | {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 208 | PCI_IDSEL_NUMBER, PCI_ANY_ID, |
| 209 | pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, |
| 210 | PCI_ENET0_MEMADDR, |
| 211 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} }, |
| 212 | {} |
| 213 | }; |
| 214 | #endif |
| 215 | |
| 216 | |
Zhao Chenhui | d5c784e | 2011-08-24 13:20:06 +0800 | [diff] [blame] | 217 | static struct pci_controller pci1_hose; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 218 | #endif /* CONFIG_PCI */ |
| 219 | |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 220 | void pci_init_board(void) |
| 221 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 222 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 223 | volatile ccsr_gur_t *gur = &immap->im_gur; |
Kumar Gala | b852621 | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 224 | struct fsl_pci_info pci_info; |
Wolfgang Denk | e38cc2c | 2011-11-29 22:17:54 +0000 | [diff] [blame] | 225 | u32 devdisr; |
Kumar Gala | b852621 | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 226 | int first_free_busno; |
| 227 | int pci_agent; |
Kumar Gala | 5e3d705 | 2009-11-04 12:51:10 -0600 | [diff] [blame] | 228 | |
| 229 | devdisr = in_be32(&gur->devdisr); |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 230 | |
Kumar Gala | b852621 | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 231 | first_free_busno = fsl_pcie_init_board(0); |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 232 | |
| 233 | #ifdef CONFIG_PCI1 |
Kumar Gala | 5e3d705 | 2009-11-04 12:51:10 -0600 | [diff] [blame] | 234 | if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { |
Kumar Gala | b852621 | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 235 | SET_STD_PCI_INFO(pci_info, 1); |
| 236 | set_next_law(pci_info.mem_phys, |
| 237 | law_size_bits(pci_info.mem_size), pci_info.law); |
| 238 | set_next_law(pci_info.io_phys, |
| 239 | law_size_bits(pci_info.io_size), pci_info.law); |
| 240 | |
| 241 | pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); |
Peter Tyser | 8ca78f2 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 242 | printf("PCI: connected to PCI slots as %s" \ |
Kumar Gala | 5e3d705 | 2009-11-04 12:51:10 -0600 | [diff] [blame] | 243 | " (base address %lx)\n", |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 244 | pci_agent ? "Agent" : "Host", |
Kumar Gala | b852621 | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 245 | pci_info.regs); |
Zhao Chenhui | d5c784e | 2011-08-24 13:20:06 +0800 | [diff] [blame] | 246 | #ifndef CONFIG_PCI_PNP |
| 247 | pci1_hose.config_table = pci_mpc86xxcts_config_table; |
| 248 | #endif |
Kumar Gala | b852621 | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 249 | first_free_busno = fsl_pci_init_port(&pci_info, |
Kumar Gala | 5e3d705 | 2009-11-04 12:51:10 -0600 | [diff] [blame] | 250 | &pci1_hose, first_free_busno); |
| 251 | } else { |
Peter Tyser | 8ca78f2 | 2010-10-29 17:59:24 -0500 | [diff] [blame] | 252 | printf("PCI: disabled\n"); |
Kumar Gala | 5e3d705 | 2009-11-04 12:51:10 -0600 | [diff] [blame] | 253 | } |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 254 | |
Kumar Gala | 5e3d705 | 2009-11-04 12:51:10 -0600 | [diff] [blame] | 255 | puts("\n"); |
| 256 | #else |
| 257 | setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */ |
| 258 | #endif |
Kumar Gala | b852621 | 2010-12-17 10:42:33 -0600 | [diff] [blame] | 259 | |
| 260 | fsl_pcie_init_board(first_free_busno); |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 261 | } |
| 262 | |
Jon Loeliger | 1df170f | 2008-01-04 12:07:27 -0600 | [diff] [blame] | 263 | #if defined(CONFIG_OF_BOARD_SETUP) |
Simon Glass | e895a4b | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 264 | int ft_board_setup(void *blob, bd_t *bd) |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 265 | { |
Peter Tyser | 8439f05 | 2009-09-21 23:09:28 -0500 | [diff] [blame] | 266 | ft_cpu_setup(blob, bd); |
Jon Loeliger | 1df170f | 2008-01-04 12:07:27 -0600 | [diff] [blame] | 267 | |
Kumar Gala | 6525d51 | 2010-07-08 22:37:44 -0500 | [diff] [blame] | 268 | FT_FSL_PCI_SETUP; |
Simon Glass | e895a4b | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 269 | |
| 270 | return 0; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 271 | } |
| 272 | #endif |
| 273 | |
| 274 | /* |
| 275 | * get_board_sys_clk |
| 276 | * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ |
| 277 | */ |
| 278 | |
| 279 | unsigned long |
| 280 | get_board_sys_clk(ulong dummy) |
| 281 | { |
York Sun | a877880 | 2007-10-29 13:58:39 -0500 | [diff] [blame] | 282 | u8 i; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 283 | ulong val = 0; |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 284 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 285 | |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 286 | i = in_8(pixis_base + PIXIS_SPD); |
Jon Loeliger | 3dd2db5 | 2007-10-16 13:54:01 -0500 | [diff] [blame] | 287 | i &= 0x07; |
| 288 | |
| 289 | switch (i) { |
| 290 | case 0: |
| 291 | val = 33333000; |
| 292 | break; |
| 293 | case 1: |
| 294 | val = 39999600; |
| 295 | break; |
| 296 | case 2: |
| 297 | val = 49999500; |
| 298 | break; |
| 299 | case 3: |
| 300 | val = 66666000; |
| 301 | break; |
| 302 | case 4: |
| 303 | val = 83332500; |
| 304 | break; |
| 305 | case 5: |
| 306 | val = 99999000; |
| 307 | break; |
| 308 | case 6: |
| 309 | val = 133332000; |
| 310 | break; |
| 311 | case 7: |
| 312 | val = 166665000; |
| 313 | break; |
| 314 | } |
| 315 | |
| 316 | return val; |
| 317 | } |
Ben Warren | 65d3d99 | 2008-07-11 23:42:19 -0700 | [diff] [blame] | 318 | |
Ben Warren | 65d3d99 | 2008-07-11 23:42:19 -0700 | [diff] [blame] | 319 | int board_eth_init(bd_t *bis) |
| 320 | { |
Ben Warren | 89973f8 | 2008-08-31 22:22:04 -0700 | [diff] [blame] | 321 | return pci_eth_init(bis); |
Ben Warren | 65d3d99 | 2008-07-11 23:42:19 -0700 | [diff] [blame] | 322 | } |
Peter Tyser | 4ef630d | 2009-02-05 11:25:25 -0600 | [diff] [blame] | 323 | |
| 324 | void board_reset(void) |
| 325 | { |
Kumar Gala | 048e7ef | 2009-07-22 10:12:39 -0500 | [diff] [blame] | 326 | u8 *pixis_base = (u8 *)PIXIS_BASE; |
| 327 | |
| 328 | out_8(pixis_base + PIXIS_RST, 0); |
Peter Tyser | 4ef630d | 2009-02-05 11:25:25 -0600 | [diff] [blame] | 329 | |
| 330 | while (1) |
| 331 | ; |
| 332 | } |