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wdenkacea76a2002-09-20 09:17:33 +00001/*
2 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/************************************************************************
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020024 * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
wdenkacea76a2002-09-20 09:17:33 +000025 ***********************************************************************/
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*-----------------------------------------------------------------------
31 * High Level Configuration Options
32 *----------------------------------------------------------------------*/
33#define CONFIG_EBONY 1 /* Board is ebony */
Stefan Roese4a3cd9e2005-09-07 16:21:12 +020034#define CONFIG_440GP 1 /* Specifc GP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020035#define CONFIG_440 1 /* ... PPC440 family */
wdenkacea76a2002-09-20 09:17:33 +000036#define CONFIG_4xx 1 /* ... PPC4xx family */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
wdenkacea76a2002-09-20 09:17:33 +000038#undef CFG_DRAM_TEST /* Disable-takes long time! */
39#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
40
Stefan Roese8a316c92005-08-01 16:49:12 +020041/*
42 * Define here the location of the environment variables (FLASH or NVRAM).
43 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
44 * supported for backward compatibility.
45 */
46#if 1
47#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
48#else
49#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
50#endif
51
wdenkacea76a2002-09-20 09:17:33 +000052/*-----------------------------------------------------------------------
53 * Base addresses -- Note these are effective addresses where the
54 * actual resources get mapped (not physical addresses)
55 *----------------------------------------------------------------------*/
56#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
57#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
Stefan Roese8a316c92005-08-01 16:49:12 +020058#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
wdenkacea76a2002-09-20 09:17:33 +000059#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
60#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
61#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
62#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
63
wdenkacea76a2002-09-20 09:17:33 +000064#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
Stefan Roese8a316c92005-08-01 16:49:12 +020065#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
wdenkacea76a2002-09-20 09:17:33 +000066
67/*-----------------------------------------------------------------------
68 * Initial RAM & stack pointer (placed in internal SRAM)
69 *----------------------------------------------------------------------*/
70#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
71#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
72#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
73
74#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
75#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
76
77#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
78#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
79
80/*-----------------------------------------------------------------------
81 * Serial Port
82 *----------------------------------------------------------------------*/
83#undef CONFIG_SERIAL_SOFTWARE_FIFO
84#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
Stefan Roese8a316c92005-08-01 16:49:12 +020085#define CONFIG_BAUDRATE 115200
wdenkacea76a2002-09-20 09:17:33 +000086
87#define CFG_BAUDRATE_TABLE \
88 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
89
90/*-----------------------------------------------------------------------
91 * NVRAM/RTC
92 *
93 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
94 * The DS1743 code assumes this condition (i.e. -- it assumes the base
95 * address for the RTC registers is:
96 *
97 * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
98 *
99 *----------------------------------------------------------------------*/
100#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
101#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
102
Stefan Roese8a316c92005-08-01 16:49:12 +0200103#ifdef CFG_ENV_IS_IN_NVRAM
104#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
105#define CFG_ENV_ADDR \
106 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
107#endif /* CFG_ENV_IS_IN_NVRAM */
108
wdenkacea76a2002-09-20 09:17:33 +0000109/*-----------------------------------------------------------------------
110 * FLASH related
111 *----------------------------------------------------------------------*/
112#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
113#define CFG_MAX_FLASH_SECT 32 /* sectors per device */
114
wdenkacea76a2002-09-20 09:17:33 +0000115#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
116#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
117
Stefan Roese8a316c92005-08-01 16:49:12 +0200118#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
119
120#define CFG_FLASH_ADDR0 0x5555
121#define CFG_FLASH_ADDR1 0x2aaa
122#define CFG_FLASH_WORD_SIZE unsigned char
123
124#ifdef CFG_ENV_IS_IN_FLASH
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200125#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200126#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
127#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
128
129/* Address and size of Redundant Environment Sector */
130#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
131#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
132#endif /* CFG_ENV_IS_IN_FLASH */
133
wdenkacea76a2002-09-20 09:17:33 +0000134/*-----------------------------------------------------------------------
135 * DDR SDRAM
136 *----------------------------------------------------------------------*/
Stefan Roese8423e5e2007-03-16 21:11:42 +0100137#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
138#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
139#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
wdenkacea76a2002-09-20 09:17:33 +0000140
141/*-----------------------------------------------------------------------
142 * I2C
143 *----------------------------------------------------------------------*/
144#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
145#undef CONFIG_SOFT_I2C /* I2C bit-banged */
146#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
147#define CFG_I2C_SLAVE 0x7F
Stefan Roese4f92ed52006-08-07 14:33:32 +0200148
149#define CFG_I2C_MULTI_EEPROMS
150#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
151#define CFG_I2C_EEPROM_ADDR_LEN 1
152#define CFG_EEPROM_PAGE_WRITE_ENABLE
153#define CFG_EEPROM_PAGE_WRITE_BITS 3
154#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenkacea76a2002-09-20 09:17:33 +0000155
Stefan Roese8a316c92005-08-01 16:49:12 +0200156#define CONFIG_PREBOOT "echo;" \
157 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
158 "echo"
wdenkacea76a2002-09-20 09:17:33 +0000159
Stefan Roese8a316c92005-08-01 16:49:12 +0200160#undef CONFIG_BOOTARGS
wdenkacea76a2002-09-20 09:17:33 +0000161
Stefan Roese8a316c92005-08-01 16:49:12 +0200162#define CONFIG_EXTRA_ENV_SETTINGS \
163 "netdev=eth0\0" \
164 "hostname=ebony\0" \
165 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100166 "nfsroot=${serverip}:${rootpath}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200167 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100168 "addip=setenv bootargs ${bootargs} " \
169 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
170 ":${hostname}:${netdev}:off panic=1\0" \
171 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Stefan Roese8a316c92005-08-01 16:49:12 +0200172 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100173 "bootm ${kernel_addr}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200174 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100175 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
176 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200177 "bootm\0" \
178 "rootpath=/opt/eldk/ppc_4xx\0" \
179 "bootfile=/tftpboot/ebony/uImage\0" \
180 "kernel_addr=ff800000\0" \
181 "ramdisk_addr=ff810000\0" \
Stefan Roese5a753f92007-02-07 16:51:08 +0100182 "initrd_high=30000000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200183 "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \
184 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
185 "cp.b 100000 fffc0000 40000;" \
186 "setenv filesize;saveenv\0" \
187 "upd=run load;run update\0" \
188 ""
189#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkacea76a2002-09-20 09:17:33 +0000190
Stefan Roese8a316c92005-08-01 16:49:12 +0200191#if 0
192#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
193#else
194#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
195#endif
196
197#define CONFIG_BAUDRATE 115200
wdenkacea76a2002-09-20 09:17:33 +0000198
199#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
200#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
201
202#define CONFIG_MII 1 /* MII PHY management */
203#define CONFIG_PHY_ADDR 8 /* PHY address */
Stefan Roese4a3cd9e2005-09-07 16:21:12 +0200204#define CONFIG_HAS_ETH1
205#define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */
206#define CONFIG_NET_MULTI 1
207#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
wdenkacea76a2002-09-20 09:17:33 +0000208
Stefan Roese1e25f952005-10-20 16:34:28 +0200209#define CONFIG_NETCONSOLE /* include NetConsole support */
210
wdenkacea76a2002-09-20 09:17:33 +0000211
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500212/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500213 * BOOTP options
214 */
215#define CONFIG_BOOTP_BOOTFILESIZE
216#define CONFIG_BOOTP_BOOTPATH
217#define CONFIG_BOOTP_GATEWAY
218#define CONFIG_BOOTP_HOSTNAME
219
220
221/*
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500222 * Command line configuration.
223 */
224#include <config_cmd_default.h>
225
226#define CONFIG_CMD_ASKENV
227#define CONFIG_CMD_DATE
228#define CONFIG_CMD_DHCP
229#define CONFIG_CMD_DIAG
230#define CONFIG_CMD_ELF
231#define CONFIG_CMD_EEPROM
232#define CONFIG_CMD_I2C
233#define CONFIG_CMD_IRQ
234#define CONFIG_CMD_MII
235#define CONFIG_CMD_NET
236#define CONFIG_CMD_NFS
237#define CONFIG_CMD_PCI
238#define CONFIG_CMD_PING
239#define CONFIG_CMD_REGINFO
240#define CONFIG_CMD_SDRAM
241#define CONFIG_CMD_SNTP
242
wdenkacea76a2002-09-20 09:17:33 +0000243
244#undef CONFIG_WATCHDOG /* watchdog disabled */
245
246/*
247 * Miscellaneous configurable options
248 */
249#define CFG_LONGHELP /* undef to save memory */
250#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500251#if defined(CONFIG_CMD_KGDB)
wdenkacea76a2002-09-20 09:17:33 +0000252#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
253#else
254#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
255#endif
256#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
257#define CFG_MAXARGS 16 /* max number of command args */
258#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
259
260#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
261#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
262
263#define CFG_LOAD_ADDR 0x100000 /* default load address */
264#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
265
266#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
267
Stefan Roese4f92ed52006-08-07 14:33:32 +0200268#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Stefan Roese8a316c92005-08-01 16:49:12 +0200269#define CONFIG_LOOPW 1 /* enable loopw command */
Stefan Roese4f92ed52006-08-07 14:33:32 +0200270#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese8a316c92005-08-01 16:49:12 +0200271#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
272#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
273
wdenkacea76a2002-09-20 09:17:33 +0000274/*-----------------------------------------------------------------------
275 * PCI stuff
276 *-----------------------------------------------------------------------
277 */
278/* General PCI */
279#define CONFIG_PCI /* include pci support */
280#define CONFIG_PCI_PNP /* do pci plug-and-play */
281#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
282#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
283
284/* Board-specific PCI */
wdenkacea76a2002-09-20 09:17:33 +0000285#define CFG_PCI_TARGET_INIT /* let board init pci target */
286
Stefan Roese8a316c92005-08-01 16:49:12 +0200287#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
wdenkacea76a2002-09-20 09:17:33 +0000288#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
289
290/*
291 * For booting Linux, the board info and command line data
292 * have to be in the first 8 MB of memory, since this is
293 * the maximum mapped by the Linux kernel during initialization.
294 */
295#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkacea76a2002-09-20 09:17:33 +0000296
297/*
298 * Internal Definitions
299 *
300 * Boot Flags
301 */
302#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
303#define BOOTFLAG_WARM 0x02 /* Software reboot */
304
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500305#if defined(CONFIG_CMD_KGDB)
wdenkacea76a2002-09-20 09:17:33 +0000306#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
307#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
308#endif
309#endif /* __CONFIG_H */