Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010-2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 23 | |
| 24 | /* Tegra AP (Application Processor) code */ |
| 25 | |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 26 | #include <common.h> |
Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 27 | #include <asm/io.h> |
| 28 | #include <asm/arch/gp_padctrl.h> |
| 29 | #include <asm/arch-tegra/ap.h> |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 30 | #include <asm/arch-tegra/clock.h> |
Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 31 | #include <asm/arch-tegra/fuse.h> |
| 32 | #include <asm/arch-tegra/pmc.h> |
| 33 | #include <asm/arch-tegra/scu.h> |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 34 | #include <asm/arch-tegra/tegra.h> |
Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 35 | #include <asm/arch-tegra/warmboot.h> |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 36 | |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 37 | int tegra_get_chip(void) |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 38 | { |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 39 | int rev; |
| 40 | struct apb_misc_gp_ctlr *gp = |
| 41 | (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 42 | |
| 43 | /* |
| 44 | * This is undocumented, Chip ID is bits 15:8 of the register |
| 45 | * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 46 | * Tegra30, and 0x35 for T114. |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 47 | */ |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 48 | rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 49 | debug("%s: CHIPID is 0x%02X\n", __func__, rev); |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 50 | |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 51 | return rev; |
| 52 | } |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 53 | |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 54 | int tegra_get_sku_info(void) |
| 55 | { |
| 56 | int sku_id; |
| 57 | struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; |
| 58 | |
| 59 | sku_id = readl(&fuse->sku_info) & 0xff; |
| 60 | debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); |
| 61 | |
| 62 | return sku_id; |
| 63 | } |
| 64 | |
| 65 | int tegra_get_chip_sku(void) |
| 66 | { |
| 67 | uint sku_id, chip_id; |
| 68 | |
| 69 | chip_id = tegra_get_chip(); |
| 70 | sku_id = tegra_get_sku_info(); |
| 71 | |
| 72 | switch (chip_id) { |
Allen Martin | 00a2749 | 2012-08-31 08:30:00 +0000 | [diff] [blame] | 73 | case CHIPID_TEGRA20: |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 74 | switch (sku_id) { |
Stephen Warren | 20583d0 | 2013-05-17 14:10:15 +0000 | [diff] [blame] | 75 | case SKU_ID_T20_7: |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 76 | case SKU_ID_T20: |
| 77 | return TEGRA_SOC_T20; |
| 78 | case SKU_ID_T25SE: |
| 79 | case SKU_ID_AP25: |
| 80 | case SKU_ID_T25: |
| 81 | case SKU_ID_AP25E: |
| 82 | case SKU_ID_T25E: |
| 83 | return TEGRA_SOC_T25; |
| 84 | } |
| 85 | break; |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 86 | case CHIPID_TEGRA30: |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 87 | switch (sku_id) { |
Stephen Warren | eb222d1 | 2013-03-27 09:37:02 +0000 | [diff] [blame] | 88 | case SKU_ID_T33: |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 89 | case SKU_ID_T30: |
| 90 | return TEGRA_SOC_T30; |
| 91 | } |
| 92 | break; |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 93 | case CHIPID_TEGRA114: |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 94 | switch (sku_id) { |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 95 | case SKU_ID_T114_ENG: |
Stephen Warren | 840167c | 2013-05-17 14:10:14 +0000 | [diff] [blame] | 96 | case SKU_ID_T114_1: |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 97 | return TEGRA_SOC_T114; |
| 98 | } |
| 99 | break; |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 100 | } |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 101 | /* unknown chip/sku id */ |
| 102 | printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", |
| 103 | __func__, chip_id, sku_id); |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 104 | return TEGRA_SOC_UNKNOWN; |
| 105 | } |
| 106 | |
Allen Martin | 12b7b70 | 2012-08-31 08:30:12 +0000 | [diff] [blame] | 107 | static void enable_scu(void) |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 108 | { |
| 109 | struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; |
| 110 | u32 reg; |
| 111 | |
Tom Warren | dbc000b | 2013-05-23 12:26:18 +0000 | [diff] [blame] | 112 | /* Only enable the SCU on T20/T25 */ |
| 113 | if (tegra_get_chip() != CHIPID_TEGRA20) |
| 114 | return; |
| 115 | |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 116 | /* If SCU already setup/enabled, return */ |
| 117 | if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) |
| 118 | return; |
| 119 | |
| 120 | /* Invalidate all ways for all processors */ |
| 121 | writel(0xFFFF, &scu->scu_inv_all); |
| 122 | |
| 123 | /* Enable SCU - bit 0 */ |
| 124 | reg = readl(&scu->scu_ctrl); |
| 125 | reg |= SCU_CTRL_ENABLE; |
| 126 | writel(reg, &scu->scu_ctrl); |
| 127 | } |
| 128 | |
Tom Warren | 76e350b | 2012-05-30 14:06:09 -0700 | [diff] [blame] | 129 | static u32 get_odmdata(void) |
| 130 | { |
| 131 | /* |
| 132 | * ODMDATA is stored in the BCT in IRAM by the BootROM. |
| 133 | * The BCT start and size are stored in the BIT in IRAM. |
| 134 | * Read the data @ bct_start + (bct_size - 12). This works |
| 135 | * on T20 and T30 BCTs, which are locked down. If this changes |
| 136 | * in new chips (T114, etc.), we can revisit this algorithm. |
| 137 | */ |
| 138 | |
| 139 | u32 bct_start, odmdata; |
| 140 | |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 141 | bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR); |
Tom Warren | 76e350b | 2012-05-30 14:06:09 -0700 | [diff] [blame] | 142 | odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); |
| 143 | |
| 144 | return odmdata; |
| 145 | } |
| 146 | |
Allen Martin | 12b7b70 | 2012-08-31 08:30:12 +0000 | [diff] [blame] | 147 | static void init_pmc_scratch(void) |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 148 | { |
Tom Warren | 29f3e3f | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 149 | struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
Tom Warren | 76e350b | 2012-05-30 14:06:09 -0700 | [diff] [blame] | 150 | u32 odmdata; |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 151 | int i; |
| 152 | |
| 153 | /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ |
| 154 | for (i = 0; i < 23; i++) |
| 155 | writel(0, &pmc->pmc_scratch1+i); |
| 156 | |
| 157 | /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ |
Tom Warren | 76e350b | 2012-05-30 14:06:09 -0700 | [diff] [blame] | 158 | odmdata = get_odmdata(); |
| 159 | writel(odmdata, &pmc->pmc_scratch20); |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 160 | } |
| 161 | |
Allen Martin | 12b7b70 | 2012-08-31 08:30:12 +0000 | [diff] [blame] | 162 | void s_init(void) |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 163 | { |
Simon Glass | 210576f | 2011-11-05 03:56:50 +0000 | [diff] [blame] | 164 | /* Init PMC scratch memory */ |
| 165 | init_pmc_scratch(); |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 166 | |
Simon Glass | 210576f | 2011-11-05 03:56:50 +0000 | [diff] [blame] | 167 | enable_scu(); |
| 168 | |
Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 169 | /* init the cache */ |
| 170 | config_cache(); |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 171 | } |