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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChung Liew8e585f02007-06-18 13:50:13 -05002/*
TsiChungLiew2bd806f2007-07-05 23:17:36 -05003 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
TsiChung Liew8e585f02007-06-18 13:50:13 -05004 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
5 *
angelo@sysam.ite27802a2016-04-27 21:51:13 +02006 * Modified to add device model (DM) support
7 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
Angelo Dureghello461ea072019-03-13 21:46:49 +01008 *
9 * Modified to add DM and fdt support, removed non DM code
10 * (C) Copyright 2018 Angelo Dureghello <angelo@sysam.it>
TsiChung Liew8e585f02007-06-18 13:50:13 -050011 */
12
13/*
14 * Minimal serial functions needed to use one of the uart ports
15 * as serial console interface.
16 */
17
18#include <common.h>
angelo@sysam.ite27802a2016-04-27 21:51:13 +020019#include <dm.h>
20#include <dm/platform_data/serial_coldfire.h>
Alison Wang39c7a262012-10-18 16:54:38 +000021#include <serial.h>
22#include <linux/compiler.h>
TsiChungLiew2bd806f2007-07-05 23:17:36 -050023#include <asm/immap.h>
24#include <asm/uart.h>
TsiChung Liew8e585f02007-06-18 13:50:13 -050025
26DECLARE_GLOBAL_DATA_PTR;
27
TsiChung Liewfa9da592010-03-09 19:24:43 -060028extern void uart_port_conf(int port);
TsiChungLiew8d1d66a2007-08-05 03:55:21 -050029
angelo@sysam.ite27802a2016-04-27 21:51:13 +020030static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
TsiChung Liew8e585f02007-06-18 13:50:13 -050031{
TsiChung Liew8e585f02007-06-18 13:50:13 -050032 u32 counter;
33
angelo@sysam.ite27802a2016-04-27 21:51:13 +020034 uart_port_conf(port_idx);
TsiChungLiew8d1d66a2007-08-05 03:55:21 -050035
TsiChung Liew8e585f02007-06-18 13:50:13 -050036 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020037 writeb(UART_UCR_RESET_RX, &uart->ucr);
38 writeb(UART_UCR_RESET_TX, &uart->ucr);
39 writeb(UART_UCR_RESET_ERROR, &uart->ucr);
40 writeb(UART_UCR_RESET_MR, &uart->ucr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050041 __asm__("nop");
42
angelo@sysam.ite27802a2016-04-27 21:51:13 +020043 writeb(0, &uart->uimr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050044
45 /* write to CSR: RX/TX baud rate from timers */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020046 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050047
angelo@sysam.ite27802a2016-04-27 21:51:13 +020048 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
49 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050050
51 /* Setting up BaudRate */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020052 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
53 counter = counter / baudrate;
TsiChung Liew8e585f02007-06-18 13:50:13 -050054
55 /* write to CTUR: divide counter upper byte */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020056 writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
TsiChung Liew8e585f02007-06-18 13:50:13 -050057 /* write to CTLR: divide counter lower byte */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020058 writeb((u8)(counter & 0x00ff), &uart->ubg2);
TsiChung Liew8e585f02007-06-18 13:50:13 -050059
angelo@sysam.ite27802a2016-04-27 21:51:13 +020060 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050061
62 return (0);
63}
64
angelo@sysam.ite27802a2016-04-27 21:51:13 +020065static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
66{
67 u32 counter;
68
69 /* Setting up BaudRate */
70 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
71 counter = counter / baudrate;
72
73 /* write to CTUR: divide counter upper byte */
74 writeb(((counter & 0xff00) >> 8), &uart->ubg1);
75 /* write to CTLR: divide counter lower byte */
76 writeb((counter & 0x00ff), &uart->ubg2);
77
78 writeb(UART_UCR_RESET_RX, &uart->ucr);
79 writeb(UART_UCR_RESET_TX, &uart->ucr);
80
81 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
82}
83
angelo@sysam.ite27802a2016-04-27 21:51:13 +020084static int coldfire_serial_probe(struct udevice *dev)
85{
86 struct coldfire_serial_platdata *plat = dev->platdata;
87
Angelo Durgehelloce5e3ea2020-02-29 01:01:32 +010088 plat->port = dev->seq;
89
angelo@sysam.ite27802a2016-04-27 21:51:13 +020090 return mcf_serial_init_common((uart_t *)plat->base,
91 plat->port, plat->baudrate);
92}
93
94static int coldfire_serial_putc(struct udevice *dev, const char ch)
95{
96 struct coldfire_serial_platdata *plat = dev->platdata;
97 uart_t *uart = (uart_t *)plat->base;
98
99 /* Wait for last character to go. */
100 if (!(readb(&uart->usr) & UART_USR_TXRDY))
101 return -EAGAIN;
102
103 writeb(ch, &uart->utb);
104
105 return 0;
106}
107
108static int coldfire_serial_getc(struct udevice *dev)
109{
110 struct coldfire_serial_platdata *plat = dev->platdata;
111 uart_t *uart = (uart_t *)(plat->base);
112
113 /* Wait for a character to arrive. */
114 if (!(readb(&uart->usr) & UART_USR_RXRDY))
115 return -EAGAIN;
116
117 return readb(&uart->urb);
118}
119
120int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
121{
122 struct coldfire_serial_platdata *plat = dev->platdata;
123 uart_t *uart = (uart_t *)(plat->base);
124
125 mcf_serial_setbrg_common(uart, baudrate);
126
127 return 0;
128}
129
130static int coldfire_serial_pending(struct udevice *dev, bool input)
131{
132 struct coldfire_serial_platdata *plat = dev->platdata;
133 uart_t *uart = (uart_t *)(plat->base);
134
135 if (input)
136 return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
137 else
138 return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
139
140 return 0;
141}
142
Angelo Dureghello461ea072019-03-13 21:46:49 +0100143static int coldfire_ofdata_to_platdata(struct udevice *dev)
144{
145 struct coldfire_serial_platdata *plat = dev_get_platdata(dev);
146 fdt_addr_t addr_base;
147
148 addr_base = devfdt_get_addr(dev);
149 if (addr_base == FDT_ADDR_T_NONE)
150 return -ENODEV;
151
152 plat->base = (uint32_t)addr_base;
Angelo Dureghello461ea072019-03-13 21:46:49 +0100153 plat->baudrate = gd->baudrate;
154
155 return 0;
156}
157
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200158static const struct dm_serial_ops coldfire_serial_ops = {
159 .putc = coldfire_serial_putc,
160 .pending = coldfire_serial_pending,
161 .getc = coldfire_serial_getc,
162 .setbrg = coldfire_serial_setbrg,
163};
164
Angelo Dureghello461ea072019-03-13 21:46:49 +0100165static const struct udevice_id coldfire_serial_ids[] = {
166 { .compatible = "fsl,mcf-uart" },
167 { }
168};
169
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200170U_BOOT_DRIVER(serial_coldfire) = {
171 .name = "serial_coldfire",
172 .id = UCLASS_SERIAL,
Angelo Dureghello461ea072019-03-13 21:46:49 +0100173 .of_match = coldfire_serial_ids,
174 .ofdata_to_platdata = coldfire_ofdata_to_platdata,
175 .platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata),
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200176 .probe = coldfire_serial_probe,
177 .ops = &coldfire_serial_ops,
178 .flags = DM_FLAG_PRE_RELOC,
179};