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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * Configuation settings for the esd TASREG board.
3 *
4 * (C) Copyright 2004
5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
stroesea20b27a2004-12-16 18:05:42 +00008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _TASREG_H
15#define _TASREG_H
16
17#ifndef __ASSEMBLY__
18#include <asm/m5249.h>
19#endif
20
21/*
22 * High Level Configuration Options
23 * (easy to change)
24 */
25#define CONFIG_MCF52x2 /* define processor family */
26#define CONFIG_M5249 /* define processor type */
27
28#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
29
TsiChungLiewaa93d852007-08-15 19:46:38 -050030#define CONFIG_MCFTMR
31
32#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_UART_PORT (0)
stroesea20b27a2004-12-16 18:05:42 +000034#define CONFIG_BAUDRATE 19200
stroesea20b27a2004-12-16 18:05:42 +000035
36#undef CONFIG_WATCHDOG
37
38#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
39
stroesea20b27a2004-12-16 18:05:42 +000040
Jon Loeligera5562902007-07-08 15:31:57 -050041/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050042 * BOOTP options
43 */
44#define CONFIG_BOOTP_BOOTFILESIZE
45#define CONFIG_BOOTP_BOOTPATH
46#define CONFIG_BOOTP_GATEWAY
47#define CONFIG_BOOTP_HOSTNAME
48
49
50/*
Jon Loeligera5562902007-07-08 15:31:57 -050051 * Command line configuration.
52 */
53#include <config_cmd_default.h>
54
55#define CONFIG_CMD_BSP
56#define CONFIG_CMD_EEPROM
57#define CONFIG_CMD_I2C
58
59#undef CONFIG_CMD_NET
60
61
stroesea20b27a2004-12-16 18:05:42 +000062#define CONFIG_BOOTDELAY 3
63
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_LONGHELP /* undef to save memory */
stroesea20b27a2004-12-16 18:05:42 +000065
Jon Loeligera5562902007-07-08 15:31:57 -050066#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +000068#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +000070#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
72#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
73#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +000074
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
76#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea20b27a2004-12-16 18:05:42 +000077#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
78#define CONFIG_LOOPW 1 /* enable loopw command */
79#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
80
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
stroesea20b27a2004-12-16 18:05:42 +000082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_MEMTEST_START 0x400
84#define CONFIG_SYS_MEMTEST_END 0x380000
stroesea20b27a2004-12-16 18:05:42 +000085
stroesea20b27a2004-12-16 18:05:42 +000086/*
87 * Clock configuration: enable only one of the following options
88 */
89
90#if 0 /* this setting will run the cpu at 11MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_PLL_BYPASS 1 /* bypass PLL for test purpose */
92#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
93#define CONFIG_SYS_CLK 11289600 /* PLL bypass */
stroesea20b27a2004-12-16 18:05:42 +000094#endif
95
96#if 0 /* this setting will run the cpu at 70MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
98#undef CONFIG_SYS_FAST_CLK /* MCF5249 can run at 140MHz */
99#define CONFIG_SYS_CLK 72185018 /* The next lower speed */
stroesea20b27a2004-12-16 18:05:42 +0000100#endif
101
102#if 1 /* this setting will run the cpu at 140MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
104#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
105#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
stroesea20b27a2004-12-16 18:05:42 +0000106#endif
107
108/*
109 * Low Level Configuration Settings
110 * (address mappings, register initial values, etc.)
111 * You should know what you are doing if you make changes here.
112 */
113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
115#define CONFIG_SYS_MBAR2 0x80000000
stroesea20b27a2004-12-16 18:05:42 +0000116
117/*-----------------------------------------------------------------------
118 * I2C
119 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100120#define CONFIG_SYS_I2C
121#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
122#define CONFIG_SYS_I2C_SOFT_SPEED 100000
123#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000124
stroesea20b27a2004-12-16 18:05:42 +0000125#if 0 /* push-pull */
126#define SDA 0x00800000
127#define SCL 0x00000008
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
129#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
130#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
131#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
132#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
133#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
stroesea20b27a2004-12-16 18:05:42 +0000134#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;}
135#define I2C_READ ((IN1&SDA)?1:0)
136#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;}
137#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;}
138#define I2C_DELAY {udelay(5);}
139#define I2C_ACTIVE {DIR1|=SDA;}
140#define I2C_TRISTATE {DIR1&=~SDA;}
141#else /* open-collector */
142#define SDA 0x00800000
143#define SCL 0x00000008
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define DIR0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
145#define DIR1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
146#define OUT0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
147#define OUT1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
148#define IN0 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
149#define IN1 *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
stroesea20b27a2004-12-16 18:05:42 +0000150#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
151#define I2C_READ ((IN1&SDA)?1:0)
152#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;}
153#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;}
154#define I2C_DELAY {udelay(5);}
155#define I2C_ACTIVE {DIR1|=SDA;}
156#define I2C_TRISTATE {DIR1&=~SDA;}
157#endif
Heiko Schocherea818db2013-01-29 08:53:15 +0100158
159#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
160#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
161/* mask of address bits that overflow into the "EEPROM chip address" */
162#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
163/*
164 * The Catalyst CAT24WC32 has 32 byte page write mode using
165 * last 5 bits of the address
166 */
167#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
168#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000169
170/*-----------------------------------------------------------------------
171 * Definitions for initial stack pointer and data area (in DPRAM)
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200174#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200175#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000177
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200178#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200179#define CONFIG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/
180#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
181#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
stroesea20b27a2004-12-16 18:05:42 +0000182
183/*-----------------------------------------------------------------------
184 * Start addresses for the final memory configuration
185 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_SDRAM_BASE 0x00000000
189#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew012522f2008-10-21 10:03:07 +0000190#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
stroesea20b27a2004-12-16 18:05:42 +0000191
192#if 0 /* test-only */
193#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
194#endif
195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
stroesea20b27a2004-12-16 18:05:42 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MONITOR_LEN 0x20000
199#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
200#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
stroesea20b27a2004-12-16 18:05:42 +0000201
202/*
203 * For booting Linux, the board info and command line data
204 * have to be in the first 8 MB of memory, since this is
205 * the maximum mapped by the Linux kernel during initialization ??
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000208
209/*-----------------------------------------------------------------------
210 * FLASH organization
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
213#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea20b27a2004-12-16 18:05:42 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
216#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
219#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
220#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea20b27a2004-12-16 18:05:42 +0000221/*
222 * The following defines are added for buggy IOP480 byte interface.
223 * All other boards should use the standard values (CPCI405 etc.)
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
226#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
227#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea20b27a2004-12-16 18:05:42 +0000228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000230
231/*-----------------------------------------------------------------------
232 * Cache Configuration
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_CACHELINE_SIZE 16
stroesea20b27a2004-12-16 18:05:42 +0000235
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600236#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200237 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600238#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200239 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600240#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
241#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
242 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
243 CF_ACR_EN | CF_ACR_SM_ALL)
244#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
245 CF_CACR_DBWE)
246
stroesea20b27a2004-12-16 18:05:42 +0000247/*-----------------------------------------------------------------------
248 * Memory bank definitions
249 */
250
251/* CS0 - AMD Flash, address 0xffc00000 */
TsiChung Liew012522f2008-10-21 10:03:07 +0000252#define CONFIG_SYS_CS0_BASE 0xffc00000
253#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
stroesea20b27a2004-12-16 18:05:42 +0000254/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
TsiChung Liew012522f2008-10-21 10:03:07 +0000255#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
stroesea20b27a2004-12-16 18:05:42 +0000256
257/* CS1 - FPGA, address 0xe0000000 */
TsiChung Liew012522f2008-10-21 10:03:07 +0000258#define CONFIG_SYS_CS1_BASE 0xe0000000
259#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
260#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
stroesea20b27a2004-12-16 18:05:42 +0000261
262/*-----------------------------------------------------------------------
263 * Port configuration
264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
266#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
267#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
268#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
269#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
270#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
stroesea20b27a2004-12-16 18:05:42 +0000271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
stroesea20b27a2004-12-16 18:05:42 +0000273
274/*-----------------------------------------------------------------------
275 * FPGA stuff
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
278#define CONFIG_SYS_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/
stroesea20b27a2004-12-16 18:05:42 +0000279
280/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */
282#define CONFIG_SYS_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */
283#define CONFIG_SYS_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */
284#define CONFIG_SYS_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */
285#define CONFIG_SYS_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000286
287#endif /* _TASREG_H */