| Wu, Josh | bdfd59a | 2012-08-23 00:05:36 +0000 | [diff] [blame] | 1 | How to enable PMECC(Programmable Multibit ECC) for nand on Atmel SoCs |
| 2 | ----------------------------------------------------------- |
| 3 | 2012-08-22 Josh Wu <josh.wu@atmel.com> |
| 4 | |
| 5 | The Programmable Multibit ECC (PMECC) controller is a programmable binary |
| 6 | BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller |
| 7 | can be used to support both SLC and MLC NAND Flash devices. It supports to |
| 8 | generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector (512 or |
| 9 | 1024 bytes) of data. |
| 10 | |
| 11 | Following Atmel AT91 products support PMECC. |
| 12 | - AT91SAM9X25, X35, G25, G15, G35 (tested) |
| 13 | - AT91SAM9N12 (not tested, Should work) |
| 14 | |
| 15 | As soon as your nand flash software ECC works, you can enable PMECC. |
| 16 | |
| 17 | To use PMECC in this driver, the user needs to set: |
| 18 | 1. the PMECC correction error bits capability: CONFIG_PMECC_CAP. |
| 19 | It can be 2, 4, 8, 12 or 24. |
| 20 | 2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE. |
| 21 | It only can be 512 or 1024. |
| Wu, Josh | bdfd59a | 2012-08-23 00:05:36 +0000 | [diff] [blame] | 22 | |
| 23 | Take AT91SAM9X5EK as an example, the board definition file likes: |
| 24 | |
| 25 | /* PMECC & PMERRLOC */ |
| 26 | #define CONFIG_ATMEL_NAND_HWECC 1 |
| 27 | #define CONFIG_ATMEL_NAND_HW_PMECC 1 |
| 28 | #define CONFIG_PMECC_CAP 2 |
| 29 | #define CONFIG_PMECC_SECTOR_SIZE 512 |