Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0b35b2d11774fadd48b9492bacd89a9757965ecc / . / arch / arm / dts / vf.dtsi
blob: 5198eee024190bd0995fea08ab5b2130ff8664db [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]4 */
5/include/ "skeleton.dtsi"
Sanchayan Maity5aaad062016-08-09 23:45:00 +0530[diff] [blame]6#include <dt-bindings/gpio/gpio.h>
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]7
8/ {
9 aliases {
10 gpio0 = &gpio0;
11 gpio1 = &gpio1;
12 gpio2 = &gpio2;
13 gpio3 = &gpio3;
14 gpio4 = &gpio4;
Bhuvanchandra DVd5e4f0a2016-01-27 10:31:45 +0530[diff] [blame]15 serial0 = &uart0;
16 serial1 = &uart1;
17 serial2 = &uart2;
18 serial3 = &uart3;
19 serial4 = &uart4;
20 serial5 = &uart5;
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]21 spi0 = &dspi0;
22 spi1 = &dspi1;
Sanchayan Maity5aaad062016-08-09 23:45:00 +0530[diff] [blame]23 ehci0 = &ehci0;
24 ehci1 = &ehci1;
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]25 };
26
27 soc {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 compatible = "simple-bus";
31 ranges;
32
33 aips0: aips-bus@40000000 {
34 compatible = "fsl,aips-bus", "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
Stefan Agner19271132016-11-30 13:41:57 -0800[diff] [blame]37 reg = <0x40000000 0x00070000>;
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]38 ranges;
39
Bhuvanchandra DVd5e4f0a2016-01-27 10:31:45 +0530[diff] [blame]40 uart0: serial@40027000 {
41 compatible = "fsl,vf610-lpuart";
42 reg = <0x40027000 0x1000>;
43 status = "disabled";
44 };
45
46 uart1: serial@40028000 {
47 compatible = "fsl,vf610-lpuart";
48 reg = <0x40028000 0x1000>;
49 status = "disabled";
50 };
51
52 uart2: serial@40029000 {
53 compatible = "fsl,vf610-lpuart";
54 reg = <0x40029000 0x1000>;
55 status = "disabled";
56 };
57
58 uart3: serial@4002a000 {
59 compatible = "fsl,vf610-lpuart";
60 reg = <0x4002a000 0x1000>;
61 status = "disabled";
62 };
63
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]64 dspi0: dspi0@4002c000 {
65 #address-cells = <1>;
66 #size-cells = <0>;
67 compatible = "fsl,vf610-dspi";
68 reg = <0x4002c000 0x1000>;
69 num-cs = <5>;
70 status = "disabled";
71 };
72
73 dspi1: dspi1@4002d000 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "fsl,vf610-dspi";
77 reg = <0x4002d000 0x1000>;
78 num-cs = <5>;
79 status = "disabled";
80 };
81
82 qspi0: quadspi@40044000 {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 compatible = "fsl,vf610-qspi";
Albert ARIBAUD \(3ADEV\)27192d12016-09-26 09:08:08 +0200[diff] [blame]86 reg = <0x40044000 0x1000>,
87 <0x20000000 0x10000000>;
88 reg-names = "QuadSPI", "QuadSPI-memory";
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]89 status = "disabled";
90 };
91
92 gpio0: gpio@40049000 {
93 compatible = "fsl,vf610-gpio";
94 reg = <0x400ff000 0x40>;
95 #gpio-cells = <2>;
96 };
97
98 gpio1: gpio@4004a000 {
99 compatible = "fsl,vf610-gpio";
100 reg = <0x400ff040 0x40>;
101 #gpio-cells = <2>;
102 };
103
104 gpio2: gpio@4004b000 {
105 compatible = "fsl,vf610-gpio";
106 reg = <0x400ff080 0x40>;
107 #gpio-cells = <2>;
108 };
109
110 gpio3: gpio@4004c000 {
111 compatible = "fsl,vf610-gpio";
112 reg = <0x400ff0c0 0x40>;
113 #gpio-cells = <2>;
114 };
115
116 gpio4: gpio@4004d000 {
117 compatible = "fsl,vf610-gpio";
118 reg = <0x400ff100 0x40>;
119 #gpio-cells = <2>;
120 };
Sanchayan Maity5aaad062016-08-09 23:45:00 +0530[diff] [blame]121
122 ehci0: ehci@40034000 {
123 compatible = "fsl,vf610-usb";
124 reg = <0x40034000 0x800>;
125 status = "disabled";
126 };
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]127 };
128
129 aips1: aips-bus@40080000 {
130 compatible = "fsl,aips-bus", "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
Stefan Agner19271132016-11-30 13:41:57 -0800[diff] [blame]133 reg = <0x40080000 0x0007f000>;
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]134 ranges;
Bhuvanchandra DVd5e4f0a2016-01-27 10:31:45 +0530[diff] [blame]135
136 uart4: serial@400a9000 {
137 compatible = "fsl,vf610-lpuart";
138 reg = <0x400a9000 0x1000>;
139 status = "disabled";
140 };
141
142 uart5: serial@400aa000 {
143 compatible = "fsl,vf610-lpuart";
144 reg = <0x400aa000 0x1000>;
145 status = "disabled";
146 };
147
Sanchayan Maity5aaad062016-08-09 23:45:00 +0530[diff] [blame]148 ehci1: ehci@400b4000 {
149 compatible = "fsl,vf610-usb";
150 reg = <0x400b4000 0x800>;
151 status = "disabled";
152 };
Bhuvanchandra DVd4700302015-06-01 18:37:21 +0530[diff] [blame]153 };
154 };
155};