Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 2 | /* |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 3 | * Copyright 2008-2014 Freescale Semiconductor, Inc. |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * Generic driver for Freescale DDR/DDR2/DDR3 memory controller. |
| 8 | * Based on code from spd_sdram.c |
| 9 | * Author: James Yang [at freescale.com] |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 13 | #include <dm.h> |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 14 | #include <i2c.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 15 | #include <fsl_ddr_sdram.h> |
York Sun | 5614e71 | 2013-09-30 09:22:09 -0700 | [diff] [blame] | 16 | #include <fsl_ddr.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 17 | #include <init.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 18 | #include <log.h> |
Simon Glass | cd93d62 | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 19 | #include <asm/bitops.h> |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 20 | |
York Sun | 6b9e309 | 2014-02-10 13:59:43 -0800 | [diff] [blame] | 21 | /* |
| 22 | * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view |
| 23 | * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for |
| 24 | * all Power SoCs. But it could be different for ARM SoCs. For example, |
| 25 | * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of |
| 26 | * 0x00_8000_0000 ~ 0x00_ffff_ffff |
| 27 | * 0x80_8000_0000 ~ 0xff_ffff_ffff |
| 28 | */ |
| 29 | #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY |
Mario Six | 133ec60 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 30 | #ifdef CONFIG_MPC83xx |
| 31 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE |
| 32 | #else |
York Sun | 6b9e309 | 2014-02-10 13:59:43 -0800 | [diff] [blame] | 33 | #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE |
| 34 | #endif |
Mario Six | 133ec60 | 2019-01-21 09:18:16 +0100 | [diff] [blame] | 35 | #endif |
York Sun | 6b9e309 | 2014-02-10 13:59:43 -0800 | [diff] [blame] | 36 | |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 37 | #ifdef CONFIG_PPC |
| 38 | #include <asm/fsl_law.h> |
| 39 | |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 40 | void fsl_ddr_set_lawbar( |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 41 | const common_timing_params_t *memctl_common_params, |
| 42 | unsigned int memctl_interleaved, |
| 43 | unsigned int ctrl_num); |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 44 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 45 | |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 46 | void fsl_ddr_set_intl3r(const unsigned int granule_size); |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 47 | #if defined(SPD_EEPROM_ADDRESS) || \ |
| 48 | defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ |
| 49 | defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 50 | #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) |
| 51 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 52 | [0][0] = SPD_EEPROM_ADDRESS, |
| 53 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 54 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) |
| 55 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
York Sun | 639f330 | 2011-08-26 11:32:41 -0700 | [diff] [blame] | 56 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 57 | [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ |
| 58 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 59 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) |
| 60 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 61 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 62 | [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ |
| 63 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 64 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) |
| 65 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 66 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 67 | [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ |
| 68 | [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ |
| 69 | [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ |
| 70 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 71 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) |
| 72 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 73 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 74 | [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ |
| 75 | [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */ |
| 76 | }; |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 77 | #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) |
| 78 | u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 79 | [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ |
| 80 | [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ |
| 81 | [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ |
| 82 | [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ |
| 83 | [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */ |
| 84 | [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */ |
| 85 | }; |
| 86 | |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 87 | #endif |
| 88 | |
Igor Opaniuk | 2147a16 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 89 | #if CONFIG_IS_ENABLED(DM_I2C) |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 90 | #define DEV_TYPE struct udevice |
| 91 | #else |
| 92 | /* Local udevice */ |
| 93 | struct ludevice { |
| 94 | u8 chip; |
| 95 | }; |
| 96 | |
| 97 | #define DEV_TYPE struct ludevice |
| 98 | |
| 99 | #endif |
| 100 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 101 | #define SPD_SPA0_ADDRESS 0x36 |
| 102 | #define SPD_SPA1_ADDRESS 0x37 |
| 103 | |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 104 | static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr, |
| 105 | int alen, uint8_t *buf, int len) |
| 106 | { |
| 107 | int ret; |
| 108 | |
Igor Opaniuk | 2147a16 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 109 | #if CONFIG_IS_ENABLED(DM_I2C) |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 110 | ret = dm_i2c_read(dev, 0, buf, len); |
| 111 | #else |
| 112 | ret = i2c_read(dev->chip, addr, alen, buf, len); |
| 113 | #endif |
| 114 | |
| 115 | return ret; |
| 116 | } |
| 117 | |
| 118 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 119 | static int ddr_i2c_dummy_write(unsigned int chip_addr) |
| 120 | { |
| 121 | uint8_t buf = 0; |
| 122 | |
Igor Opaniuk | 2147a16 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 123 | #if CONFIG_IS_ENABLED(DM_I2C) |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 124 | struct udevice *dev; |
| 125 | int ret; |
| 126 | |
| 127 | ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr, |
| 128 | 1, &dev); |
| 129 | if (ret) { |
| 130 | printf("%s: Cannot find udev for a bus %d\n", __func__, |
| 131 | CONFIG_SYS_SPD_BUS_NUM); |
| 132 | return ret; |
| 133 | } |
| 134 | |
| 135 | return dm_i2c_write(dev, 0, &buf, 1); |
| 136 | #else |
| 137 | return i2c_write(chip_addr, 0, 1, &buf, 1); |
| 138 | #endif |
| 139 | |
| 140 | return 0; |
| 141 | } |
| 142 | #endif |
| 143 | |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 144 | static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) |
| 145 | { |
Valentin Longchamp | 0778bbe | 2013-10-18 11:47:19 +0200 | [diff] [blame] | 146 | int ret; |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 147 | DEV_TYPE *dev; |
Valentin Longchamp | 0778bbe | 2013-10-18 11:47:19 +0200 | [diff] [blame] | 148 | |
Igor Opaniuk | 2147a16 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 149 | #if CONFIG_IS_ENABLED(DM_I2C) |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 150 | ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address, |
| 151 | 1, &dev); |
| 152 | if (ret) { |
| 153 | printf("%s: Cannot find udev for a bus %d\n", __func__, |
| 154 | CONFIG_SYS_SPD_BUS_NUM); |
| 155 | return; |
| 156 | } |
| 157 | #else /* Non DM I2C support - will be removed */ |
| 158 | struct ludevice ldev = { |
| 159 | .chip = i2c_address, |
| 160 | }; |
| 161 | dev = &ldev; |
| 162 | |
Valentin Longchamp | 0778bbe | 2013-10-18 11:47:19 +0200 | [diff] [blame] | 163 | i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM); |
Chuanhua Han | 0eba65d | 2019-07-10 21:00:20 +0800 | [diff] [blame] | 164 | #endif |
| 165 | |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 166 | #ifdef CONFIG_SYS_FSL_DDR4 |
| 167 | /* |
| 168 | * DDR4 SPD has 384 to 512 bytes |
| 169 | * To access the lower 256 bytes, we need to set EE page address to 0 |
| 170 | * To access the upper 256 bytes, we need to set EE page address to 1 |
| 171 | * See Jedec standar No. 21-C for detail |
| 172 | */ |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 173 | ddr_i2c_dummy_write(SPD_SPA0_ADDRESS); |
| 174 | ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 175 | if (!ret) { |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 176 | ddr_i2c_dummy_write(SPD_SPA1_ADDRESS); |
| 177 | ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256), |
| 178 | min(256, |
| 179 | (int)sizeof(generic_spd_eeprom_t) |
| 180 | - 256)); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 181 | } |
Chuanhua Han | 0eba65d | 2019-07-10 21:00:20 +0800 | [diff] [blame] | 182 | |
| 183 | #else |
Heiko Schocher | 09aa70f | 2019-08-26 17:28:34 +0200 | [diff] [blame] | 184 | ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, |
| 185 | sizeof(generic_spd_eeprom_t)); |
York Sun | 34e026f | 2014-03-27 17:54:47 -0700 | [diff] [blame] | 186 | #endif |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 187 | |
| 188 | if (ret) { |
York Sun | 82968a7 | 2012-10-08 07:44:28 +0000 | [diff] [blame] | 189 | if (i2c_address == |
| 190 | #ifdef SPD_EEPROM_ADDRESS |
| 191 | SPD_EEPROM_ADDRESS |
| 192 | #elif defined(SPD_EEPROM_ADDRESS1) |
| 193 | SPD_EEPROM_ADDRESS1 |
| 194 | #endif |
| 195 | ) { |
| 196 | printf("DDR: failed to read SPD from address %u\n", |
| 197 | i2c_address); |
| 198 | } else { |
| 199 | debug("DDR: failed to read SPD from address %u\n", |
| 200 | i2c_address); |
| 201 | } |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 202 | memset(spd, 0, sizeof(generic_spd_eeprom_t)); |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | __attribute__((weak, alias("__get_spd"))) |
| 207 | void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); |
| 208 | |
York Sun | b92557c | 2015-05-28 14:54:08 +0530 | [diff] [blame] | 209 | /* This function allows boards to update SPD address */ |
| 210 | __weak void update_spd_address(unsigned int ctrl_num, |
| 211 | unsigned int slot, |
| 212 | unsigned int *addr) |
| 213 | { |
| 214 | } |
| 215 | |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 216 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 217 | unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 218 | { |
| 219 | unsigned int i; |
| 220 | unsigned int i2c_address = 0; |
| 221 | |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 222 | if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 223 | printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); |
| 224 | return; |
| 225 | } |
| 226 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 227 | for (i = 0; i < dimm_slots_per_ctrl; i++) { |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 228 | i2c_address = spd_i2c_addr[ctrl_num][i]; |
York Sun | b92557c | 2015-05-28 14:54:08 +0530 | [diff] [blame] | 229 | update_spd_address(ctrl_num, i, &i2c_address); |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 230 | get_spd(&(ctrl_dimms_spd[i]), i2c_address); |
| 231 | } |
| 232 | } |
| 233 | #else |
| 234 | void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 235 | unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl) |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 236 | { |
| 237 | } |
| 238 | #endif /* SPD_EEPROM_ADDRESSx */ |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 239 | |
| 240 | /* |
| 241 | * ASSUMPTIONS: |
| 242 | * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller |
| 243 | * - Same memory data bus width on all controllers |
| 244 | * |
| 245 | * NOTES: |
| 246 | * |
| 247 | * The memory controller and associated documentation use confusing |
| 248 | * terminology when referring to the orgranization of DRAM. |
| 249 | * |
| 250 | * Here is a terminology translation table: |
| 251 | * |
| 252 | * memory controller/documention |industry |this code |signals |
| 253 | * -------------------------------|-----------|-----------|----------------- |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 254 | * physical bank/bank |rank |rank |chip select (CS) |
| 255 | * logical bank/sub-bank |bank |bank |bank address (BA) |
| 256 | * page/row |row |page |row address |
| 257 | * ??? |column |column |column address |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 258 | * |
| 259 | * The naming confusion is further exacerbated by the descriptions of the |
| 260 | * memory controller interleaving feature, where accesses are interleaved |
| 261 | * _BETWEEN_ two seperate memory controllers. This is configured only in |
| 262 | * CS0_CONFIG[INTLV_CTL] of each memory controller. |
| 263 | * |
| 264 | * memory controller documentation | number of chip selects |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 265 | * | per memory controller supported |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 266 | * --------------------------------|----------------------------------------- |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 267 | * cache line interleaving | 1 (CS0 only) |
| 268 | * page interleaving | 1 (CS0 only) |
| 269 | * bank interleaving | 1 (CS0 only) |
| 270 | * superbank interleraving | depends on bank (chip select) |
| 271 | * | interleraving [rank interleaving] |
| 272 | * | mode used on every memory controller |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 273 | * |
| 274 | * Even further confusing is the existence of the interleaving feature |
| 275 | * _WITHIN_ each memory controller. The feature is referred to in |
| 276 | * documentation as chip select interleaving or bank interleaving, |
| 277 | * although it is configured in the DDR_SDRAM_CFG field. |
| 278 | * |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 279 | * Name of field | documentation name | this code |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 280 | * -----------------------------|-----------------------|------------------ |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 281 | * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving |
| 282 | * | interleaving |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 283 | */ |
| 284 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 285 | const char *step_string_tbl[] = { |
| 286 | "STEP_GET_SPD", |
| 287 | "STEP_COMPUTE_DIMM_PARMS", |
| 288 | "STEP_COMPUTE_COMMON_PARMS", |
| 289 | "STEP_GATHER_OPTS", |
| 290 | "STEP_ASSIGN_ADDRESSES", |
| 291 | "STEP_COMPUTE_REGS", |
| 292 | "STEP_PROGRAM_REGS", |
| 293 | "STEP_ALL" |
| 294 | }; |
| 295 | |
| 296 | const char * step_to_string(unsigned int step) { |
| 297 | |
| 298 | unsigned int s = __ilog2(step); |
| 299 | |
| 300 | if ((1 << s) != step) |
| 301 | return step_string_tbl[7]; |
| 302 | |
York Sun | 349689b | 2014-04-01 14:20:49 -0700 | [diff] [blame] | 303 | if (s >= ARRAY_SIZE(step_string_tbl)) { |
| 304 | printf("Error for the step in %s\n", __func__); |
| 305 | s = 0; |
| 306 | } |
| 307 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 308 | return step_string_tbl[s]; |
| 309 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 310 | |
York Sun | ef00227 | 2013-03-25 07:39:35 +0000 | [diff] [blame] | 311 | static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 312 | unsigned int dbw_cap_adj[]) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 313 | { |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 314 | unsigned int i, j; |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 315 | unsigned long long total_mem, current_mem_base, total_ctlr_mem; |
| 316 | unsigned long long rank_density, ctlr_density = 0; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 317 | unsigned int first_ctrl = pinfo->first_ctrl; |
| 318 | unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 319 | |
| 320 | /* |
| 321 | * If a reduced data width is requested, but the SPD |
| 322 | * specifies a physically wider device, adjust the |
| 323 | * computed dimm capacities accordingly before |
| 324 | * assigning addresses. |
| 325 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 326 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 327 | unsigned int found = 0; |
| 328 | |
| 329 | switch (pinfo->memctl_opts[i].data_bus_width) { |
| 330 | case 2: |
| 331 | /* 16-bit */ |
York Sun | 51d498f | 2011-05-27 07:25:51 +0800 | [diff] [blame] | 332 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 333 | unsigned int dw; |
| 334 | if (!pinfo->dimm_params[i][j].n_ranks) |
| 335 | continue; |
| 336 | dw = pinfo->dimm_params[i][j].primary_sdram_width; |
| 337 | if ((dw == 72 || dw == 64)) { |
| 338 | dbw_cap_adj[i] = 2; |
| 339 | break; |
| 340 | } else if ((dw == 40 || dw == 32)) { |
| 341 | dbw_cap_adj[i] = 1; |
| 342 | break; |
| 343 | } |
| 344 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 345 | break; |
| 346 | |
| 347 | case 1: |
| 348 | /* 32-bit */ |
| 349 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 350 | unsigned int dw; |
| 351 | dw = pinfo->dimm_params[i][j].data_width; |
| 352 | if (pinfo->dimm_params[i][j].n_ranks |
| 353 | && (dw == 72 || dw == 64)) { |
| 354 | /* |
| 355 | * FIXME: can't really do it |
| 356 | * like this because this just |
| 357 | * further reduces the memory |
| 358 | */ |
| 359 | found = 1; |
| 360 | break; |
| 361 | } |
| 362 | } |
| 363 | if (found) { |
| 364 | dbw_cap_adj[i] = 1; |
| 365 | } |
| 366 | break; |
| 367 | |
| 368 | case 0: |
| 369 | /* 64-bit */ |
| 370 | break; |
| 371 | |
| 372 | default: |
| 373 | printf("unexpected data bus width " |
| 374 | "specified controller %u\n", i); |
| 375 | return 1; |
| 376 | } |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 377 | debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 378 | } |
| 379 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 380 | current_mem_base = pinfo->mem_base; |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 381 | total_mem = 0; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 382 | if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) { |
| 383 | rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >> |
| 384 | dbw_cap_adj[first_ctrl]; |
| 385 | switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl & |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 386 | FSL_DDR_CS0_CS1_CS2_CS3) { |
| 387 | case FSL_DDR_CS0_CS1_CS2_CS3: |
| 388 | ctlr_density = 4 * rank_density; |
| 389 | break; |
| 390 | case FSL_DDR_CS0_CS1: |
| 391 | case FSL_DDR_CS0_CS1_AND_CS2_CS3: |
| 392 | ctlr_density = 2 * rank_density; |
| 393 | break; |
| 394 | case FSL_DDR_CS2_CS3: |
| 395 | default: |
| 396 | ctlr_density = rank_density; |
| 397 | break; |
| 398 | } |
| 399 | debug("rank density is 0x%llx, ctlr density is 0x%llx\n", |
| 400 | rank_density, ctlr_density); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 401 | for (i = first_ctrl; i <= last_ctrl; i++) { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 402 | if (pinfo->memctl_opts[i].memctl_interleaving) { |
| 403 | switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { |
York Sun | 6b1e125 | 2014-02-10 13:59:44 -0800 | [diff] [blame] | 404 | case FSL_DDR_256B_INTERLEAVING: |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 405 | case FSL_DDR_CACHE_LINE_INTERLEAVING: |
| 406 | case FSL_DDR_PAGE_INTERLEAVING: |
| 407 | case FSL_DDR_BANK_INTERLEAVING: |
| 408 | case FSL_DDR_SUPERBANK_INTERLEAVING: |
| 409 | total_ctlr_mem = 2 * ctlr_density; |
| 410 | break; |
| 411 | case FSL_DDR_3WAY_1KB_INTERLEAVING: |
| 412 | case FSL_DDR_3WAY_4KB_INTERLEAVING: |
| 413 | case FSL_DDR_3WAY_8KB_INTERLEAVING: |
| 414 | total_ctlr_mem = 3 * ctlr_density; |
| 415 | break; |
| 416 | case FSL_DDR_4WAY_1KB_INTERLEAVING: |
| 417 | case FSL_DDR_4WAY_4KB_INTERLEAVING: |
| 418 | case FSL_DDR_4WAY_8KB_INTERLEAVING: |
| 419 | total_ctlr_mem = 4 * ctlr_density; |
| 420 | break; |
| 421 | default: |
| 422 | panic("Unknown interleaving mode"); |
| 423 | } |
| 424 | pinfo->common_timing_params[i].base_address = |
| 425 | current_mem_base; |
| 426 | pinfo->common_timing_params[i].total_mem = |
| 427 | total_ctlr_mem; |
| 428 | total_mem = current_mem_base + total_ctlr_mem; |
| 429 | debug("ctrl %d base 0x%llx\n", i, current_mem_base); |
| 430 | debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); |
| 431 | } else { |
| 432 | /* when 3rd controller not interleaved */ |
| 433 | current_mem_base = total_mem; |
| 434 | total_ctlr_mem = 0; |
| 435 | pinfo->common_timing_params[i].base_address = |
| 436 | current_mem_base; |
| 437 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 438 | unsigned long long cap = |
| 439 | pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; |
| 440 | pinfo->dimm_params[i][j].base_address = |
| 441 | current_mem_base; |
| 442 | debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); |
| 443 | current_mem_base += cap; |
| 444 | total_ctlr_mem += cap; |
| 445 | } |
| 446 | debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); |
| 447 | pinfo->common_timing_params[i].total_mem = |
| 448 | total_ctlr_mem; |
| 449 | total_mem += total_ctlr_mem; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 450 | } |
| 451 | } |
| 452 | } else { |
| 453 | /* |
| 454 | * Simple linear assignment if memory |
| 455 | * controllers are not interleaved. |
| 456 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 457 | for (i = first_ctrl; i <= last_ctrl; i++) { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 458 | total_ctlr_mem = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 459 | pinfo->common_timing_params[i].base_address = |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 460 | current_mem_base; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 461 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 462 | /* Compute DIMM base addresses. */ |
| 463 | unsigned long long cap = |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 464 | pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i]; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 465 | pinfo->dimm_params[i][j].base_address = |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 466 | current_mem_base; |
| 467 | debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base); |
| 468 | current_mem_base += cap; |
| 469 | total_ctlr_mem += cap; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 470 | } |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 471 | debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 472 | pinfo->common_timing_params[i].total_mem = |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 473 | total_ctlr_mem; |
| 474 | total_mem += total_ctlr_mem; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 475 | } |
| 476 | } |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 477 | debug("Total mem by %s is 0x%llx\n", __func__, total_mem); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 478 | |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 479 | return total_mem; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 480 | } |
| 481 | |
York Sun | ef00227 | 2013-03-25 07:39:35 +0000 | [diff] [blame] | 482 | /* Use weak function to allow board file to override the address assignment */ |
| 483 | __attribute__((weak, alias("__step_assign_addresses"))) |
| 484 | unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, |
| 485 | unsigned int dbw_cap_adj[]); |
| 486 | |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 487 | unsigned long long |
Haiying Wang | fc0c2b6 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 488 | fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, |
| 489 | unsigned int size_only) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 490 | { |
| 491 | unsigned int i, j; |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 492 | unsigned long long total_mem = 0; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 493 | int assert_reset = 0; |
| 494 | unsigned int first_ctrl = pinfo->first_ctrl; |
| 495 | unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
| 496 | __maybe_unused int retval; |
| 497 | __maybe_unused bool goodspd = false; |
| 498 | __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 499 | |
| 500 | fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; |
| 501 | common_timing_params_t *timing_params = pinfo->common_timing_params; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 502 | if (pinfo->board_need_mem_reset) |
| 503 | assert_reset = pinfo->board_need_mem_reset(); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 504 | |
| 505 | /* data bus width capacity adjust shift amount */ |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 506 | unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS]; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 507 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 508 | for (i = first_ctrl; i <= last_ctrl; i++) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 509 | dbw_capacity_adjust[i] = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 510 | |
| 511 | debug("starting at step %u (%s)\n", |
| 512 | start_step, step_to_string(start_step)); |
| 513 | |
| 514 | switch (start_step) { |
| 515 | case STEP_GET_SPD: |
York Sun | 1b3e3c4 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 516 | #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 517 | /* STEP 1: Gather all DIMM SPD data */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 518 | for (i = first_ctrl; i <= last_ctrl; i++) { |
| 519 | fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i, |
| 520 | dimm_slots_per_ctrl); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 521 | } |
| 522 | |
| 523 | case STEP_COMPUTE_DIMM_PARMS: |
| 524 | /* STEP 2: Compute DIMM parameters from SPD data */ |
| 525 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 526 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 527 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 528 | generic_spd_eeprom_t *spd = |
| 529 | &(pinfo->spd_installed_dimms[i][j]); |
| 530 | dimm_params_t *pdimm = |
Wolfgang Denk | f12e454 | 2008-09-13 02:23:05 +0200 | [diff] [blame] | 531 | &(pinfo->dimm_params[i][j]); |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 532 | retval = compute_dimm_parameters( |
| 533 | i, spd, pdimm, j); |
York Sun | f2d264b | 2011-06-07 09:42:17 +0800 | [diff] [blame] | 534 | #ifdef CONFIG_SYS_DDR_RAW_TIMING |
York Sun | 66869f9 | 2015-03-19 09:30:26 -0700 | [diff] [blame] | 535 | if (!j && retval) { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 536 | printf("SPD error on controller %d! " |
| 537 | "Trying fallback to raw timing " |
| 538 | "calculation\n", i); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 539 | retval = fsl_ddr_get_dimm_params(pdimm, |
| 540 | i, j); |
York Sun | f2d264b | 2011-06-07 09:42:17 +0800 | [diff] [blame] | 541 | } |
| 542 | #else |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 543 | if (retval == 2) { |
| 544 | printf("Error: compute_dimm_parameters" |
| 545 | " non-zero returned FATAL value " |
| 546 | "for memctl=%u dimm=%u\n", i, j); |
| 547 | return 0; |
| 548 | } |
York Sun | f2d264b | 2011-06-07 09:42:17 +0800 | [diff] [blame] | 549 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 550 | if (retval) { |
| 551 | debug("Warning: compute_dimm_parameters" |
| 552 | " non-zero return value for memctl=%u " |
| 553 | "dimm=%u\n", i, j); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 554 | } else { |
| 555 | goodspd = true; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 556 | } |
| 557 | } |
| 558 | } |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 559 | if (!goodspd) { |
| 560 | /* |
| 561 | * No valid SPD found |
| 562 | * Throw an error if this is for main memory, i.e. |
| 563 | * first_ctrl == 0. Otherwise, siliently return 0 |
| 564 | * as the memory size. |
| 565 | */ |
| 566 | if (first_ctrl == 0) |
| 567 | printf("Error: No valid SPD detected.\n"); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 568 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 569 | return 0; |
| 570 | } |
Shaohui Xie | 98de369 | 2012-06-28 23:36:38 +0000 | [diff] [blame] | 571 | #elif defined(CONFIG_SYS_DDR_RAW_TIMING) |
York Sun | 1b3e3c4 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 572 | case STEP_COMPUTE_DIMM_PARMS: |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 573 | for (i = first_ctrl; i <= last_ctrl; i++) { |
York Sun | 1b3e3c4 | 2011-06-07 09:42:16 +0800 | [diff] [blame] | 574 | for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { |
| 575 | dimm_params_t *pdimm = |
| 576 | &(pinfo->dimm_params[i][j]); |
| 577 | fsl_ddr_get_dimm_params(pdimm, i, j); |
| 578 | } |
| 579 | } |
| 580 | debug("Filling dimm parameters from board specific file\n"); |
| 581 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 582 | case STEP_COMPUTE_COMMON_PARMS: |
| 583 | /* |
| 584 | * STEP 3: Compute a common set of timing parameters |
| 585 | * suitable for all of the DIMMs on each memory controller |
| 586 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 587 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 588 | debug("Computing lowest common DIMM" |
| 589 | " parameters for memctl=%u\n", i); |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 590 | compute_lowest_common_dimm_parameters |
| 591 | (i, |
| 592 | pinfo->dimm_params[i], |
| 593 | &timing_params[i], |
| 594 | CONFIG_DIMM_SLOTS_PER_CTLR); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 595 | } |
| 596 | |
| 597 | case STEP_GATHER_OPTS: |
| 598 | /* STEP 4: Gather configuration requirements from user */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 599 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 600 | debug("Reloading memory controller " |
| 601 | "configuration options for memctl=%u\n", i); |
| 602 | /* |
| 603 | * This "reloads" the memory controller options |
| 604 | * to defaults. If the user "edits" an option, |
| 605 | * next_step points to the step after this, |
| 606 | * which is currently STEP_ASSIGN_ADDRESSES. |
| 607 | */ |
| 608 | populate_memctl_options( |
York Sun | 5684842 | 2015-07-23 14:04:48 -0700 | [diff] [blame] | 609 | &timing_params[i], |
Haiying Wang | dfb4910 | 2008-10-03 12:36:55 -0400 | [diff] [blame] | 610 | &pinfo->memctl_opts[i], |
| 611 | pinfo->dimm_params[i], i); |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 612 | /* |
| 613 | * For RDIMMs, JEDEC spec requires clocks to be stable |
| 614 | * before reset signal is deasserted. For the boards |
| 615 | * using fixed parameters, this function should be |
| 616 | * be called from board init file. |
| 617 | */ |
Priyanka Jain | 0dd38a3 | 2013-09-25 10:41:19 +0530 | [diff] [blame] | 618 | if (timing_params[i].all_dimms_registered) |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 619 | assert_reset = 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 620 | } |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 621 | if (assert_reset && !size_only) { |
| 622 | if (pinfo->board_mem_reset) { |
| 623 | debug("Asserting mem reset\n"); |
| 624 | pinfo->board_mem_reset(); |
| 625 | } else { |
| 626 | debug("Asserting mem reset missing\n"); |
| 627 | } |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 628 | } |
| 629 | |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 630 | case STEP_ASSIGN_ADDRESSES: |
| 631 | /* STEP 5: Assign addresses to chip selects */ |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 632 | check_interleaving_options(pinfo); |
| 633 | total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust); |
York Sun | 349689b | 2014-04-01 14:20:49 -0700 | [diff] [blame] | 634 | debug("Total mem %llu assigned\n", total_mem); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 635 | |
| 636 | case STEP_COMPUTE_REGS: |
| 637 | /* STEP 6: compute controller register values */ |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 638 | debug("FSL Memory ctrl register computation\n"); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 639 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 640 | if (timing_params[i].ndimms_present == 0) { |
| 641 | memset(&ddr_reg[i], 0, |
| 642 | sizeof(fsl_ddr_cfg_regs_t)); |
| 643 | continue; |
| 644 | } |
| 645 | |
York Sun | 03e664d | 2015-01-06 13:18:50 -0800 | [diff] [blame] | 646 | compute_fsl_memctl_config_regs |
| 647 | (i, |
| 648 | &pinfo->memctl_opts[i], |
| 649 | &ddr_reg[i], &timing_params[i], |
| 650 | pinfo->dimm_params[i], |
| 651 | dbw_capacity_adjust[i], |
| 652 | size_only); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 653 | } |
| 654 | |
| 655 | default: |
| 656 | break; |
| 657 | } |
| 658 | |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 659 | { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 660 | /* |
| 661 | * Compute the amount of memory available just by |
| 662 | * looking for the highest valid CSn_BNDS value. |
| 663 | * This allows us to also experiment with using |
| 664 | * only CS0 when using dual-rank DIMMs. |
| 665 | */ |
| 666 | unsigned int max_end = 0; |
| 667 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 668 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 669 | for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) { |
| 670 | fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; |
| 671 | if (reg->cs[j].config & 0x80000000) { |
| 672 | unsigned int end; |
York Sun | d8556db | 2013-06-25 11:37:45 -0700 | [diff] [blame] | 673 | /* |
| 674 | * 0xfffffff is a special value we put |
| 675 | * for unused bnds |
| 676 | */ |
| 677 | if (reg->cs[j].bnds == 0xffffffff) |
| 678 | continue; |
| 679 | end = reg->cs[j].bnds & 0xffff; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 680 | if (end > max_end) { |
| 681 | max_end = end; |
| 682 | } |
| 683 | } |
| 684 | } |
| 685 | } |
| 686 | |
York Sun | 00ec3fd | 2013-10-28 16:36:02 -0700 | [diff] [blame] | 687 | total_mem = 1 + (((unsigned long long)max_end << 24ULL) | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 688 | 0xFFFFFFULL) - pinfo->mem_base; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 689 | } |
| 690 | |
| 691 | return total_mem; |
| 692 | } |
| 693 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 694 | phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 695 | { |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 696 | unsigned int i, first_ctrl, last_ctrl; |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 697 | #ifdef CONFIG_PPC |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 698 | unsigned int law_memctl = LAW_TRGT_IF_DDR_1; |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 699 | #endif |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 700 | unsigned long long total_memory; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 701 | int deassert_reset = 0; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 702 | |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 703 | first_ctrl = pinfo->first_ctrl; |
| 704 | last_ctrl = first_ctrl + pinfo->num_ctrls - 1; |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 705 | |
| 706 | /* Compute it once normally. */ |
York Sun | 6f5e1dc | 2011-09-16 13:21:35 -0700 | [diff] [blame] | 707 | #ifdef CONFIG_FSL_DDR_INTERACTIVE |
Heinrich Schuchardt | c670aee | 2020-10-07 18:11:48 +0200 | [diff] [blame] | 708 | if (tstc() && (getchar() == 'd')) { /* we got a key press of 'd' */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 709 | total_memory = fsl_ddr_interactive(pinfo, 0); |
James Yang | e8ba6c5 | 2013-01-07 14:01:03 +0000 | [diff] [blame] | 710 | } else if (fsl_ddr_interactive_env_var_exists()) { |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 711 | total_memory = fsl_ddr_interactive(pinfo, 1); |
York Sun | e750cfa | 2013-01-04 08:13:59 +0000 | [diff] [blame] | 712 | } else |
York Sun | 6f5e1dc | 2011-09-16 13:21:35 -0700 | [diff] [blame] | 713 | #endif |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 714 | total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 715 | |
York Sun | f31cfd1 | 2012-10-08 07:44:24 +0000 | [diff] [blame] | 716 | /* setup 3-way interleaving before enabling DDRC */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 717 | switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) { |
| 718 | case FSL_DDR_3WAY_1KB_INTERLEAVING: |
| 719 | case FSL_DDR_3WAY_4KB_INTERLEAVING: |
| 720 | case FSL_DDR_3WAY_8KB_INTERLEAVING: |
| 721 | fsl_ddr_set_intl3r( |
| 722 | pinfo->memctl_opts[first_ctrl]. |
| 723 | memctl_interleaving_mode); |
| 724 | break; |
| 725 | default: |
| 726 | break; |
York Sun | f31cfd1 | 2012-10-08 07:44:24 +0000 | [diff] [blame] | 727 | } |
| 728 | |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 729 | /* |
| 730 | * Program configuration registers. |
| 731 | * JEDEC specs requires clocks to be stable before deasserting reset |
| 732 | * for RDIMMs. Clocks start after chip select is enabled and clock |
| 733 | * control register is set. During step 1, all controllers have their |
| 734 | * registers set but not enabled. Step 2 proceeds after deasserting |
| 735 | * reset through board FPGA or GPIO. |
| 736 | * For non-registered DIMMs, initialization can go through but it is |
| 737 | * also OK to follow the same flow. |
| 738 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 739 | if (pinfo->board_need_mem_reset) |
| 740 | deassert_reset = pinfo->board_need_mem_reset(); |
| 741 | for (i = first_ctrl; i <= last_ctrl; i++) { |
| 742 | if (pinfo->common_timing_params[i].all_dimms_registered) |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 743 | deassert_reset = 1; |
| 744 | } |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 745 | for (i = first_ctrl; i <= last_ctrl; i++) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 746 | debug("Programming controller %u\n", i); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 747 | if (pinfo->common_timing_params[i].ndimms_present == 0) { |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 748 | debug("No dimms present on controller %u; " |
| 749 | "skipping programming\n", i); |
| 750 | continue; |
| 751 | } |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 752 | /* |
| 753 | * The following call with step = 1 returns before enabling |
| 754 | * the controller. It has to finish with step = 2 later. |
| 755 | */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 756 | fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i, |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 757 | deassert_reset ? 1 : 0); |
| 758 | } |
| 759 | if (deassert_reset) { |
| 760 | /* Use board FPGA or GPIO to deassert reset signal */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 761 | if (pinfo->board_mem_de_reset) { |
| 762 | debug("Deasserting mem reset\n"); |
| 763 | pinfo->board_mem_de_reset(); |
| 764 | } else { |
| 765 | debug("Deasserting mem reset missing\n"); |
| 766 | } |
| 767 | for (i = first_ctrl; i <= last_ctrl; i++) { |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 768 | /* Call with step = 2 to continue initialization */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 769 | fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), |
York Sun | c63e137 | 2013-06-25 11:37:48 -0700 | [diff] [blame] | 770 | i, 2); |
| 771 | } |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 772 | } |
| 773 | |
York Sun | e32d59a | 2015-01-06 13:18:55 -0800 | [diff] [blame] | 774 | #ifdef CONFIG_FSL_DDR_SYNC_REFRESH |
| 775 | fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl); |
| 776 | #endif |
| 777 | |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 778 | #ifdef CONFIG_PPC |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 779 | /* program LAWs */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 780 | for (i = first_ctrl; i <= last_ctrl; i++) { |
| 781 | if (pinfo->memctl_opts[i].memctl_interleaving) { |
| 782 | switch (pinfo->memctl_opts[i]. |
| 783 | memctl_interleaving_mode) { |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 784 | case FSL_DDR_CACHE_LINE_INTERLEAVING: |
| 785 | case FSL_DDR_PAGE_INTERLEAVING: |
| 786 | case FSL_DDR_BANK_INTERLEAVING: |
| 787 | case FSL_DDR_SUPERBANK_INTERLEAVING: |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 788 | if (i % 2) |
| 789 | break; |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 790 | if (i == 0) { |
| 791 | law_memctl = LAW_TRGT_IF_DDR_INTRLV; |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 792 | fsl_ddr_set_lawbar( |
| 793 | &pinfo->common_timing_params[i], |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 794 | law_memctl, i); |
| 795 | } |
York Sun | 51370d5 | 2016-12-28 08:43:45 -0800 | [diff] [blame] | 796 | #if CONFIG_SYS_NUM_DDR_CTLRS > 3 |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 797 | else if (i == 2) { |
| 798 | law_memctl = LAW_TRGT_IF_DDR_INTLV_34; |
| 799 | fsl_ddr_set_lawbar( |
| 800 | &pinfo->common_timing_params[i], |
| 801 | law_memctl, i); |
| 802 | } |
| 803 | #endif |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 804 | break; |
| 805 | case FSL_DDR_3WAY_1KB_INTERLEAVING: |
| 806 | case FSL_DDR_3WAY_4KB_INTERLEAVING: |
| 807 | case FSL_DDR_3WAY_8KB_INTERLEAVING: |
| 808 | law_memctl = LAW_TRGT_IF_DDR_INTLV_123; |
| 809 | if (i == 0) { |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 810 | fsl_ddr_set_lawbar( |
| 811 | &pinfo->common_timing_params[i], |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 812 | law_memctl, i); |
| 813 | } |
| 814 | break; |
| 815 | case FSL_DDR_4WAY_1KB_INTERLEAVING: |
| 816 | case FSL_DDR_4WAY_4KB_INTERLEAVING: |
| 817 | case FSL_DDR_4WAY_8KB_INTERLEAVING: |
| 818 | law_memctl = LAW_TRGT_IF_DDR_INTLV_1234; |
| 819 | if (i == 0) |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 820 | fsl_ddr_set_lawbar( |
| 821 | &pinfo->common_timing_params[i], |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 822 | law_memctl, i); |
| 823 | /* place holder for future 4-way interleaving */ |
| 824 | break; |
| 825 | default: |
| 826 | break; |
| 827 | } |
| 828 | } else { |
| 829 | switch (i) { |
| 830 | case 0: |
| 831 | law_memctl = LAW_TRGT_IF_DDR_1; |
| 832 | break; |
| 833 | case 1: |
| 834 | law_memctl = LAW_TRGT_IF_DDR_2; |
| 835 | break; |
| 836 | case 2: |
| 837 | law_memctl = LAW_TRGT_IF_DDR_3; |
| 838 | break; |
| 839 | case 3: |
| 840 | law_memctl = LAW_TRGT_IF_DDR_4; |
| 841 | break; |
| 842 | default: |
| 843 | break; |
| 844 | } |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 845 | fsl_ddr_set_lawbar(&pinfo->common_timing_params[i], |
| 846 | law_memctl, i); |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 847 | } |
| 848 | } |
York Sun | 9ac4ffb | 2013-09-30 14:20:51 -0700 | [diff] [blame] | 849 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 850 | |
York Sun | a4c6650 | 2012-08-17 08:22:39 +0000 | [diff] [blame] | 851 | debug("total_memory by %s = %llu\n", __func__, total_memory); |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 852 | |
| 853 | #if !defined(CONFIG_PHYS_64BIT) |
| 854 | /* Check for 4G or more. Bad. */ |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 855 | if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) { |
Shruti Kanetkar | 2f848f9 | 2013-08-15 11:25:37 -0500 | [diff] [blame] | 856 | puts("Detected "); |
| 857 | print_size(total_memory, " of memory\n"); |
Becky Bruce | 7ea3871 | 2010-12-17 17:17:59 -0600 | [diff] [blame] | 858 | printf(" This U-Boot only supports < 4G of DDR\n"); |
| 859 | printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); |
Simon Glass | f1683aa | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 860 | printf(" "); /* re-align to match init_dram print */ |
Kumar Gala | e7563af | 2009-06-11 23:42:35 -0500 | [diff] [blame] | 861 | total_memory = CONFIG_MAX_MEM_MAPPED; |
| 862 | } |
| 863 | #endif |
Kumar Gala | 58e5e9a | 2008-08-26 15:01:29 -0500 | [diff] [blame] | 864 | |
| 865 | return total_memory; |
| 866 | } |
Haiying Wang | fc0c2b6 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 867 | |
| 868 | /* |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 869 | * fsl_ddr_sdram(void) -- this is the main function to be |
Simon Glass | f1683aa | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 870 | * called by dram_init() in the board file. |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 871 | * |
| 872 | * It returns amount of memory configured in bytes. |
| 873 | */ |
| 874 | phys_size_t fsl_ddr_sdram(void) |
| 875 | { |
| 876 | fsl_ddr_info_t info; |
| 877 | |
| 878 | /* Reset info structure. */ |
| 879 | memset(&info, 0, sizeof(fsl_ddr_info_t)); |
| 880 | info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; |
| 881 | info.first_ctrl = 0; |
| 882 | info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; |
| 883 | info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; |
| 884 | info.board_need_mem_reset = board_need_mem_reset; |
| 885 | info.board_mem_reset = board_assert_mem_reset; |
| 886 | info.board_mem_de_reset = board_deassert_mem_reset; |
York Sun | 61bd2f7 | 2015-11-04 09:53:10 -0800 | [diff] [blame] | 887 | remove_unused_controllers(&info); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 888 | |
| 889 | return __fsl_ddr_sdram(&info); |
| 890 | } |
| 891 | |
| 892 | #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS |
| 893 | phys_size_t fsl_other_ddr_sdram(unsigned long long base, |
| 894 | unsigned int first_ctrl, |
| 895 | unsigned int num_ctrls, |
| 896 | unsigned int dimm_slots_per_ctrl, |
| 897 | int (*board_need_reset)(void), |
| 898 | void (*board_reset)(void), |
| 899 | void (*board_de_reset)(void)) |
| 900 | { |
| 901 | fsl_ddr_info_t info; |
| 902 | |
| 903 | /* Reset info structure. */ |
| 904 | memset(&info, 0, sizeof(fsl_ddr_info_t)); |
| 905 | info.mem_base = base; |
| 906 | info.first_ctrl = first_ctrl; |
| 907 | info.num_ctrls = num_ctrls; |
| 908 | info.dimm_slots_per_ctrl = dimm_slots_per_ctrl; |
| 909 | info.board_need_mem_reset = board_need_reset; |
| 910 | info.board_mem_reset = board_reset; |
| 911 | info.board_mem_de_reset = board_de_reset; |
| 912 | |
| 913 | return __fsl_ddr_sdram(&info); |
| 914 | } |
| 915 | #endif |
| 916 | |
| 917 | /* |
| 918 | * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the |
| 919 | * size of the total memory without setting ddr control registers. |
Haiying Wang | fc0c2b6 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 920 | */ |
| 921 | phys_size_t |
| 922 | fsl_ddr_sdram_size(void) |
| 923 | { |
| 924 | fsl_ddr_info_t info; |
| 925 | unsigned long long total_memory = 0; |
| 926 | |
| 927 | memset(&info, 0 , sizeof(fsl_ddr_info_t)); |
York Sun | 1d71efb | 2014-08-01 15:51:00 -0700 | [diff] [blame] | 928 | info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; |
| 929 | info.first_ctrl = 0; |
| 930 | info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; |
| 931 | info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; |
| 932 | info.board_need_mem_reset = NULL; |
Ed Swarthout | 81dfdee | 2016-01-14 12:28:04 -0600 | [diff] [blame] | 933 | remove_unused_controllers(&info); |
Haiying Wang | fc0c2b6 | 2010-12-01 10:35:31 -0500 | [diff] [blame] | 934 | |
| 935 | /* Compute it once normally. */ |
| 936 | total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1); |
| 937 | |
| 938 | return total_memory; |
| 939 | } |