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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Kumar Gala58e5e9a2008-08-26 15:01:29 -05002/*
York Sun34e026f2014-03-27 17:54:47 -07003 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05004 */
5
6/*
7 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
8 * Based on code from spd_sdram.c
9 * Author: James Yang [at freescale.com]
10 */
11
12#include <common.h>
Heiko Schocher09aa70f2019-08-26 17:28:34 +020013#include <dm.h>
Kumar Galac39f44d2011-01-31 22:18:47 -060014#include <i2c.h>
York Sun5614e712013-09-30 09:22:09 -070015#include <fsl_ddr_sdram.h>
York Sun5614e712013-09-30 09:22:09 -070016#include <fsl_ddr.h>
Simon Glass691d7192020-05-10 11:40:02 -060017#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060018#include <log.h>
Simon Glasscd93d622020-05-10 11:40:13 -060019#include <asm/bitops.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050020
York Sun6b9e3092014-02-10 13:59:43 -080021/*
22 * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
23 * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
24 * all Power SoCs. But it could be different for ARM SoCs. For example,
25 * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
26 * 0x00_8000_0000 ~ 0x00_ffff_ffff
27 * 0x80_8000_0000 ~ 0xff_ffff_ffff
28 */
29#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
Mario Six133ec602019-01-21 09:18:16 +010030#ifdef CONFIG_MPC83xx
31#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE
32#else
York Sun6b9e3092014-02-10 13:59:43 -080033#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
34#endif
Mario Six133ec602019-01-21 09:18:16 +010035#endif
York Sun6b9e3092014-02-10 13:59:43 -080036
York Sun9ac4ffb2013-09-30 14:20:51 -070037#ifdef CONFIG_PPC
38#include <asm/fsl_law.h>
39
York Suna4c66502012-08-17 08:22:39 +000040void fsl_ddr_set_lawbar(
Kumar Gala58e5e9a2008-08-26 15:01:29 -050041 const common_timing_params_t *memctl_common_params,
42 unsigned int memctl_interleaved,
43 unsigned int ctrl_num);
York Sun9ac4ffb2013-09-30 14:20:51 -070044#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -050045
York Sun9ac4ffb2013-09-30 14:20:51 -070046void fsl_ddr_set_intl3r(const unsigned int granule_size);
Kumar Galac39f44d2011-01-31 22:18:47 -060047#if defined(SPD_EEPROM_ADDRESS) || \
48 defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
49 defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
York Sun51370d52016-12-28 08:43:45 -080050#if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
51u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
Kumar Galac39f44d2011-01-31 22:18:47 -060052 [0][0] = SPD_EEPROM_ADDRESS,
53};
York Sun51370d52016-12-28 08:43:45 -080054#elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
55u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
York Sun639f3302011-08-26 11:32:41 -070056 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
57 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
58};
York Sun51370d52016-12-28 08:43:45 -080059#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
60u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
Kumar Galac39f44d2011-01-31 22:18:47 -060061 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
62 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
63};
York Sun51370d52016-12-28 08:43:45 -080064#elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
65u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
Kumar Galac39f44d2011-01-31 22:18:47 -060066 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
67 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
68 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
69 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
70};
York Sun51370d52016-12-28 08:43:45 -080071#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
72u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
York Suna4c66502012-08-17 08:22:39 +000073 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
74 [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */
75 [2][0] = SPD_EEPROM_ADDRESS3, /* controller 3 */
76};
York Sun51370d52016-12-28 08:43:45 -080077#elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
78u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
York Suna4c66502012-08-17 08:22:39 +000079 [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */
80 [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */
81 [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */
82 [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */
83 [2][0] = SPD_EEPROM_ADDRESS5, /* controller 3 */
84 [2][1] = SPD_EEPROM_ADDRESS6, /* controller 3 */
85};
86
Kumar Galac39f44d2011-01-31 22:18:47 -060087#endif
88
Igor Opaniuk2147a162021-02-09 13:52:45 +020089#if CONFIG_IS_ENABLED(DM_I2C)
Heiko Schocher09aa70f2019-08-26 17:28:34 +020090#define DEV_TYPE struct udevice
91#else
92/* Local udevice */
93struct ludevice {
94 u8 chip;
95};
96
97#define DEV_TYPE struct ludevice
98
99#endif
100
York Sun34e026f2014-03-27 17:54:47 -0700101#define SPD_SPA0_ADDRESS 0x36
102#define SPD_SPA1_ADDRESS 0x37
103
Heiko Schocher09aa70f2019-08-26 17:28:34 +0200104static int ddr_i2c_read(DEV_TYPE *dev, unsigned int addr,
105 int alen, uint8_t *buf, int len)
106{
107 int ret;
108
Igor Opaniuk2147a162021-02-09 13:52:45 +0200109#if CONFIG_IS_ENABLED(DM_I2C)
Heiko Schocher09aa70f2019-08-26 17:28:34 +0200110 ret = dm_i2c_read(dev, 0, buf, len);
111#else
112 ret = i2c_read(dev->chip, addr, alen, buf, len);
113#endif
114
115 return ret;
116}
117
118#ifdef CONFIG_SYS_FSL_DDR4
119static int ddr_i2c_dummy_write(unsigned int chip_addr)
120{
121 uint8_t buf = 0;
122
Igor Opaniuk2147a162021-02-09 13:52:45 +0200123#if CONFIG_IS_ENABLED(DM_I2C)
Heiko Schocher09aa70f2019-08-26 17:28:34 +0200124 struct udevice *dev;
125 int ret;
126
127 ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, chip_addr,
128 1, &dev);
129 if (ret) {
130 printf("%s: Cannot find udev for a bus %d\n", __func__,
131 CONFIG_SYS_SPD_BUS_NUM);
132 return ret;
133 }
134
135 return dm_i2c_write(dev, 0, &buf, 1);
136#else
137 return i2c_write(chip_addr, 0, 1, &buf, 1);
138#endif
139
140 return 0;
141}
142#endif
143
Kumar Galac39f44d2011-01-31 22:18:47 -0600144static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
145{
Valentin Longchamp0778bbe2013-10-18 11:47:19 +0200146 int ret;
Heiko Schocher09aa70f2019-08-26 17:28:34 +0200147 DEV_TYPE *dev;
Valentin Longchamp0778bbe2013-10-18 11:47:19 +0200148
Igor Opaniuk2147a162021-02-09 13:52:45 +0200149#if CONFIG_IS_ENABLED(DM_I2C)
Heiko Schocher09aa70f2019-08-26 17:28:34 +0200150 ret = i2c_get_chip_for_busnum(CONFIG_SYS_SPD_BUS_NUM, i2c_address,
151 1, &dev);
152 if (ret) {
153 printf("%s: Cannot find udev for a bus %d\n", __func__,
154 CONFIG_SYS_SPD_BUS_NUM);
155 return;
156 }
157#else /* Non DM I2C support - will be removed */
158 struct ludevice ldev = {
159 .chip = i2c_address,
160 };
161 dev = &ldev;
162
Valentin Longchamp0778bbe2013-10-18 11:47:19 +0200163 i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
Chuanhua Han0eba65d2019-07-10 21:00:20 +0800164#endif
165
York Sun34e026f2014-03-27 17:54:47 -0700166#ifdef CONFIG_SYS_FSL_DDR4
167 /*
168 * DDR4 SPD has 384 to 512 bytes
169 * To access the lower 256 bytes, we need to set EE page address to 0
170 * To access the upper 256 bytes, we need to set EE page address to 1
171 * See Jedec standar No. 21-C for detail
172 */
Heiko Schocher09aa70f2019-08-26 17:28:34 +0200173 ddr_i2c_dummy_write(SPD_SPA0_ADDRESS);
174 ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd, 256);
York Sun34e026f2014-03-27 17:54:47 -0700175 if (!ret) {
Heiko Schocher09aa70f2019-08-26 17:28:34 +0200176 ddr_i2c_dummy_write(SPD_SPA1_ADDRESS);
177 ret = ddr_i2c_read(dev, 0, 1, (uchar *)((ulong)spd + 256),
178 min(256,
179 (int)sizeof(generic_spd_eeprom_t)
180 - 256));
York Sun34e026f2014-03-27 17:54:47 -0700181 }
Chuanhua Han0eba65d2019-07-10 21:00:20 +0800182
183#else
Heiko Schocher09aa70f2019-08-26 17:28:34 +0200184 ret = ddr_i2c_read(dev, 0, 1, (uchar *)spd,
185 sizeof(generic_spd_eeprom_t));
York Sun34e026f2014-03-27 17:54:47 -0700186#endif
Kumar Galac39f44d2011-01-31 22:18:47 -0600187
188 if (ret) {
York Sun82968a72012-10-08 07:44:28 +0000189 if (i2c_address ==
190#ifdef SPD_EEPROM_ADDRESS
191 SPD_EEPROM_ADDRESS
192#elif defined(SPD_EEPROM_ADDRESS1)
193 SPD_EEPROM_ADDRESS1
194#endif
195 ) {
196 printf("DDR: failed to read SPD from address %u\n",
197 i2c_address);
198 } else {
199 debug("DDR: failed to read SPD from address %u\n",
200 i2c_address);
201 }
Kumar Galac39f44d2011-01-31 22:18:47 -0600202 memset(spd, 0, sizeof(generic_spd_eeprom_t));
203 }
204}
205
206__attribute__((weak, alias("__get_spd")))
207void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
208
York Sunb92557c2015-05-28 14:54:08 +0530209/* This function allows boards to update SPD address */
210__weak void update_spd_address(unsigned int ctrl_num,
211 unsigned int slot,
212 unsigned int *addr)
213{
214}
215
Kumar Galac39f44d2011-01-31 22:18:47 -0600216void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
York Sun1d71efb2014-08-01 15:51:00 -0700217 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
Kumar Galac39f44d2011-01-31 22:18:47 -0600218{
219 unsigned int i;
220 unsigned int i2c_address = 0;
221
York Sun51370d52016-12-28 08:43:45 -0800222 if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
Kumar Galac39f44d2011-01-31 22:18:47 -0600223 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
224 return;
225 }
226
York Sun1d71efb2014-08-01 15:51:00 -0700227 for (i = 0; i < dimm_slots_per_ctrl; i++) {
Kumar Galac39f44d2011-01-31 22:18:47 -0600228 i2c_address = spd_i2c_addr[ctrl_num][i];
York Sunb92557c2015-05-28 14:54:08 +0530229 update_spd_address(ctrl_num, i, &i2c_address);
Kumar Galac39f44d2011-01-31 22:18:47 -0600230 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
231 }
232}
233#else
234void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
York Sun1d71efb2014-08-01 15:51:00 -0700235 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
Kumar Galac39f44d2011-01-31 22:18:47 -0600236{
237}
238#endif /* SPD_EEPROM_ADDRESSx */
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500239
240/*
241 * ASSUMPTIONS:
242 * - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
243 * - Same memory data bus width on all controllers
244 *
245 * NOTES:
246 *
247 * The memory controller and associated documentation use confusing
248 * terminology when referring to the orgranization of DRAM.
249 *
250 * Here is a terminology translation table:
251 *
252 * memory controller/documention |industry |this code |signals
253 * -------------------------------|-----------|-----------|-----------------
Wolfgang Denkf12e4542008-09-13 02:23:05 +0200254 * physical bank/bank |rank |rank |chip select (CS)
255 * logical bank/sub-bank |bank |bank |bank address (BA)
256 * page/row |row |page |row address
257 * ??? |column |column |column address
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500258 *
259 * The naming confusion is further exacerbated by the descriptions of the
260 * memory controller interleaving feature, where accesses are interleaved
261 * _BETWEEN_ two seperate memory controllers. This is configured only in
262 * CS0_CONFIG[INTLV_CTL] of each memory controller.
263 *
264 * memory controller documentation | number of chip selects
Wolfgang Denkf12e4542008-09-13 02:23:05 +0200265 * | per memory controller supported
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500266 * --------------------------------|-----------------------------------------
Wolfgang Denkf12e4542008-09-13 02:23:05 +0200267 * cache line interleaving | 1 (CS0 only)
268 * page interleaving | 1 (CS0 only)
269 * bank interleaving | 1 (CS0 only)
270 * superbank interleraving | depends on bank (chip select)
271 * | interleraving [rank interleaving]
272 * | mode used on every memory controller
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500273 *
274 * Even further confusing is the existence of the interleaving feature
275 * _WITHIN_ each memory controller. The feature is referred to in
276 * documentation as chip select interleaving or bank interleaving,
277 * although it is configured in the DDR_SDRAM_CFG field.
278 *
Wolfgang Denkf12e4542008-09-13 02:23:05 +0200279 * Name of field | documentation name | this code
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500280 * -----------------------------|-----------------------|------------------
Wolfgang Denkf12e4542008-09-13 02:23:05 +0200281 * DDR_SDRAM_CFG[BA_INTLV_CTL] | Bank (chip select) | rank interleaving
282 * | interleaving
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500283 */
284
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500285const char *step_string_tbl[] = {
286 "STEP_GET_SPD",
287 "STEP_COMPUTE_DIMM_PARMS",
288 "STEP_COMPUTE_COMMON_PARMS",
289 "STEP_GATHER_OPTS",
290 "STEP_ASSIGN_ADDRESSES",
291 "STEP_COMPUTE_REGS",
292 "STEP_PROGRAM_REGS",
293 "STEP_ALL"
294};
295
296const char * step_to_string(unsigned int step) {
297
298 unsigned int s = __ilog2(step);
299
300 if ((1 << s) != step)
301 return step_string_tbl[7];
302
York Sun349689b2014-04-01 14:20:49 -0700303 if (s >= ARRAY_SIZE(step_string_tbl)) {
304 printf("Error for the step in %s\n", __func__);
305 s = 0;
306 }
307
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500308 return step_string_tbl[s];
309}
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500310
York Sunef002272013-03-25 07:39:35 +0000311static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
York Suna4c66502012-08-17 08:22:39 +0000312 unsigned int dbw_cap_adj[])
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500313{
York Sun1d71efb2014-08-01 15:51:00 -0700314 unsigned int i, j;
York Suna4c66502012-08-17 08:22:39 +0000315 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
316 unsigned long long rank_density, ctlr_density = 0;
York Sun1d71efb2014-08-01 15:51:00 -0700317 unsigned int first_ctrl = pinfo->first_ctrl;
318 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500319
320 /*
321 * If a reduced data width is requested, but the SPD
322 * specifies a physically wider device, adjust the
323 * computed dimm capacities accordingly before
324 * assigning addresses.
325 */
York Sun1d71efb2014-08-01 15:51:00 -0700326 for (i = first_ctrl; i <= last_ctrl; i++) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500327 unsigned int found = 0;
328
329 switch (pinfo->memctl_opts[i].data_bus_width) {
330 case 2:
331 /* 16-bit */
York Sun51d498f2011-05-27 07:25:51 +0800332 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
333 unsigned int dw;
334 if (!pinfo->dimm_params[i][j].n_ranks)
335 continue;
336 dw = pinfo->dimm_params[i][j].primary_sdram_width;
337 if ((dw == 72 || dw == 64)) {
338 dbw_cap_adj[i] = 2;
339 break;
340 } else if ((dw == 40 || dw == 32)) {
341 dbw_cap_adj[i] = 1;
342 break;
343 }
344 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500345 break;
346
347 case 1:
348 /* 32-bit */
349 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
350 unsigned int dw;
351 dw = pinfo->dimm_params[i][j].data_width;
352 if (pinfo->dimm_params[i][j].n_ranks
353 && (dw == 72 || dw == 64)) {
354 /*
355 * FIXME: can't really do it
356 * like this because this just
357 * further reduces the memory
358 */
359 found = 1;
360 break;
361 }
362 }
363 if (found) {
364 dbw_cap_adj[i] = 1;
365 }
366 break;
367
368 case 0:
369 /* 64-bit */
370 break;
371
372 default:
373 printf("unexpected data bus width "
374 "specified controller %u\n", i);
375 return 1;
376 }
York Suna4c66502012-08-17 08:22:39 +0000377 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500378 }
379
York Sun1d71efb2014-08-01 15:51:00 -0700380 current_mem_base = pinfo->mem_base;
York Suna4c66502012-08-17 08:22:39 +0000381 total_mem = 0;
York Sun1d71efb2014-08-01 15:51:00 -0700382 if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
383 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
384 dbw_cap_adj[first_ctrl];
385 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
York Suna4c66502012-08-17 08:22:39 +0000386 FSL_DDR_CS0_CS1_CS2_CS3) {
387 case FSL_DDR_CS0_CS1_CS2_CS3:
388 ctlr_density = 4 * rank_density;
389 break;
390 case FSL_DDR_CS0_CS1:
391 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
392 ctlr_density = 2 * rank_density;
393 break;
394 case FSL_DDR_CS2_CS3:
395 default:
396 ctlr_density = rank_density;
397 break;
398 }
399 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
400 rank_density, ctlr_density);
York Sun1d71efb2014-08-01 15:51:00 -0700401 for (i = first_ctrl; i <= last_ctrl; i++) {
York Suna4c66502012-08-17 08:22:39 +0000402 if (pinfo->memctl_opts[i].memctl_interleaving) {
403 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
York Sun6b1e1252014-02-10 13:59:44 -0800404 case FSL_DDR_256B_INTERLEAVING:
York Suna4c66502012-08-17 08:22:39 +0000405 case FSL_DDR_CACHE_LINE_INTERLEAVING:
406 case FSL_DDR_PAGE_INTERLEAVING:
407 case FSL_DDR_BANK_INTERLEAVING:
408 case FSL_DDR_SUPERBANK_INTERLEAVING:
409 total_ctlr_mem = 2 * ctlr_density;
410 break;
411 case FSL_DDR_3WAY_1KB_INTERLEAVING:
412 case FSL_DDR_3WAY_4KB_INTERLEAVING:
413 case FSL_DDR_3WAY_8KB_INTERLEAVING:
414 total_ctlr_mem = 3 * ctlr_density;
415 break;
416 case FSL_DDR_4WAY_1KB_INTERLEAVING:
417 case FSL_DDR_4WAY_4KB_INTERLEAVING:
418 case FSL_DDR_4WAY_8KB_INTERLEAVING:
419 total_ctlr_mem = 4 * ctlr_density;
420 break;
421 default:
422 panic("Unknown interleaving mode");
423 }
424 pinfo->common_timing_params[i].base_address =
425 current_mem_base;
426 pinfo->common_timing_params[i].total_mem =
427 total_ctlr_mem;
428 total_mem = current_mem_base + total_ctlr_mem;
429 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
430 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
431 } else {
432 /* when 3rd controller not interleaved */
433 current_mem_base = total_mem;
434 total_ctlr_mem = 0;
435 pinfo->common_timing_params[i].base_address =
436 current_mem_base;
437 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
438 unsigned long long cap =
439 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
440 pinfo->dimm_params[i][j].base_address =
441 current_mem_base;
442 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
443 current_mem_base += cap;
444 total_ctlr_mem += cap;
445 }
446 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
447 pinfo->common_timing_params[i].total_mem =
448 total_ctlr_mem;
449 total_mem += total_ctlr_mem;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500450 }
451 }
452 } else {
453 /*
454 * Simple linear assignment if memory
455 * controllers are not interleaved.
456 */
York Sun1d71efb2014-08-01 15:51:00 -0700457 for (i = first_ctrl; i <= last_ctrl; i++) {
York Suna4c66502012-08-17 08:22:39 +0000458 total_ctlr_mem = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500459 pinfo->common_timing_params[i].base_address =
York Suna4c66502012-08-17 08:22:39 +0000460 current_mem_base;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500461 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
462 /* Compute DIMM base addresses. */
463 unsigned long long cap =
York Suna4c66502012-08-17 08:22:39 +0000464 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500465 pinfo->dimm_params[i][j].base_address =
York Suna4c66502012-08-17 08:22:39 +0000466 current_mem_base;
467 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
468 current_mem_base += cap;
469 total_ctlr_mem += cap;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500470 }
York Suna4c66502012-08-17 08:22:39 +0000471 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500472 pinfo->common_timing_params[i].total_mem =
York Suna4c66502012-08-17 08:22:39 +0000473 total_ctlr_mem;
474 total_mem += total_ctlr_mem;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500475 }
476 }
York Suna4c66502012-08-17 08:22:39 +0000477 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500478
York Suna4c66502012-08-17 08:22:39 +0000479 return total_mem;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500480}
481
York Sunef002272013-03-25 07:39:35 +0000482/* Use weak function to allow board file to override the address assignment */
483__attribute__((weak, alias("__step_assign_addresses")))
484unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
485 unsigned int dbw_cap_adj[]);
486
Kumar Galae7563af2009-06-11 23:42:35 -0500487unsigned long long
Haiying Wangfc0c2b62010-12-01 10:35:31 -0500488fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
489 unsigned int size_only)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500490{
491 unsigned int i, j;
Kumar Galae7563af2009-06-11 23:42:35 -0500492 unsigned long long total_mem = 0;
York Sun1d71efb2014-08-01 15:51:00 -0700493 int assert_reset = 0;
494 unsigned int first_ctrl = pinfo->first_ctrl;
495 unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
496 __maybe_unused int retval;
497 __maybe_unused bool goodspd = false;
498 __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500499
500 fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
501 common_timing_params_t *timing_params = pinfo->common_timing_params;
York Sun1d71efb2014-08-01 15:51:00 -0700502 if (pinfo->board_need_mem_reset)
503 assert_reset = pinfo->board_need_mem_reset();
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500504
505 /* data bus width capacity adjust shift amount */
York Sun51370d52016-12-28 08:43:45 -0800506 unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500507
York Sun1d71efb2014-08-01 15:51:00 -0700508 for (i = first_ctrl; i <= last_ctrl; i++)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500509 dbw_capacity_adjust[i] = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500510
511 debug("starting at step %u (%s)\n",
512 start_step, step_to_string(start_step));
513
514 switch (start_step) {
515 case STEP_GET_SPD:
York Sun1b3e3c42011-06-07 09:42:16 +0800516#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500517 /* STEP 1: Gather all DIMM SPD data */
York Sun1d71efb2014-08-01 15:51:00 -0700518 for (i = first_ctrl; i <= last_ctrl; i++) {
519 fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
520 dimm_slots_per_ctrl);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500521 }
522
523 case STEP_COMPUTE_DIMM_PARMS:
524 /* STEP 2: Compute DIMM parameters from SPD data */
525
York Sun1d71efb2014-08-01 15:51:00 -0700526 for (i = first_ctrl; i <= last_ctrl; i++) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500527 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500528 generic_spd_eeprom_t *spd =
529 &(pinfo->spd_installed_dimms[i][j]);
530 dimm_params_t *pdimm =
Wolfgang Denkf12e4542008-09-13 02:23:05 +0200531 &(pinfo->dimm_params[i][j]);
York Sun03e664d2015-01-06 13:18:50 -0800532 retval = compute_dimm_parameters(
533 i, spd, pdimm, j);
York Sunf2d264b2011-06-07 09:42:17 +0800534#ifdef CONFIG_SYS_DDR_RAW_TIMING
York Sun66869f92015-03-19 09:30:26 -0700535 if (!j && retval) {
York Suna4c66502012-08-17 08:22:39 +0000536 printf("SPD error on controller %d! "
537 "Trying fallback to raw timing "
538 "calculation\n", i);
York Sun1d71efb2014-08-01 15:51:00 -0700539 retval = fsl_ddr_get_dimm_params(pdimm,
540 i, j);
York Sunf2d264b2011-06-07 09:42:17 +0800541 }
542#else
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500543 if (retval == 2) {
544 printf("Error: compute_dimm_parameters"
545 " non-zero returned FATAL value "
546 "for memctl=%u dimm=%u\n", i, j);
547 return 0;
548 }
York Sunf2d264b2011-06-07 09:42:17 +0800549#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500550 if (retval) {
551 debug("Warning: compute_dimm_parameters"
552 " non-zero return value for memctl=%u "
553 "dimm=%u\n", i, j);
York Sun1d71efb2014-08-01 15:51:00 -0700554 } else {
555 goodspd = true;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500556 }
557 }
558 }
York Sun1d71efb2014-08-01 15:51:00 -0700559 if (!goodspd) {
560 /*
561 * No valid SPD found
562 * Throw an error if this is for main memory, i.e.
563 * first_ctrl == 0. Otherwise, siliently return 0
564 * as the memory size.
565 */
566 if (first_ctrl == 0)
567 printf("Error: No valid SPD detected.\n");
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500568
York Sun1d71efb2014-08-01 15:51:00 -0700569 return 0;
570 }
Shaohui Xie98de3692012-06-28 23:36:38 +0000571#elif defined(CONFIG_SYS_DDR_RAW_TIMING)
York Sun1b3e3c42011-06-07 09:42:16 +0800572 case STEP_COMPUTE_DIMM_PARMS:
York Sun1d71efb2014-08-01 15:51:00 -0700573 for (i = first_ctrl; i <= last_ctrl; i++) {
York Sun1b3e3c42011-06-07 09:42:16 +0800574 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
575 dimm_params_t *pdimm =
576 &(pinfo->dimm_params[i][j]);
577 fsl_ddr_get_dimm_params(pdimm, i, j);
578 }
579 }
580 debug("Filling dimm parameters from board specific file\n");
581#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500582 case STEP_COMPUTE_COMMON_PARMS:
583 /*
584 * STEP 3: Compute a common set of timing parameters
585 * suitable for all of the DIMMs on each memory controller
586 */
York Sun1d71efb2014-08-01 15:51:00 -0700587 for (i = first_ctrl; i <= last_ctrl; i++) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500588 debug("Computing lowest common DIMM"
589 " parameters for memctl=%u\n", i);
York Sun03e664d2015-01-06 13:18:50 -0800590 compute_lowest_common_dimm_parameters
591 (i,
592 pinfo->dimm_params[i],
593 &timing_params[i],
594 CONFIG_DIMM_SLOTS_PER_CTLR);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500595 }
596
597 case STEP_GATHER_OPTS:
598 /* STEP 4: Gather configuration requirements from user */
York Sun1d71efb2014-08-01 15:51:00 -0700599 for (i = first_ctrl; i <= last_ctrl; i++) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500600 debug("Reloading memory controller "
601 "configuration options for memctl=%u\n", i);
602 /*
603 * This "reloads" the memory controller options
604 * to defaults. If the user "edits" an option,
605 * next_step points to the step after this,
606 * which is currently STEP_ASSIGN_ADDRESSES.
607 */
608 populate_memctl_options(
York Sun56848422015-07-23 14:04:48 -0700609 &timing_params[i],
Haiying Wangdfb49102008-10-03 12:36:55 -0400610 &pinfo->memctl_opts[i],
611 pinfo->dimm_params[i], i);
York Sunc63e1372013-06-25 11:37:48 -0700612 /*
613 * For RDIMMs, JEDEC spec requires clocks to be stable
614 * before reset signal is deasserted. For the boards
615 * using fixed parameters, this function should be
616 * be called from board init file.
617 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530618 if (timing_params[i].all_dimms_registered)
York Sunc63e1372013-06-25 11:37:48 -0700619 assert_reset = 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500620 }
York Sun1d71efb2014-08-01 15:51:00 -0700621 if (assert_reset && !size_only) {
622 if (pinfo->board_mem_reset) {
623 debug("Asserting mem reset\n");
624 pinfo->board_mem_reset();
625 } else {
626 debug("Asserting mem reset missing\n");
627 }
York Sunc63e1372013-06-25 11:37:48 -0700628 }
629
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500630 case STEP_ASSIGN_ADDRESSES:
631 /* STEP 5: Assign addresses to chip selects */
York Suna4c66502012-08-17 08:22:39 +0000632 check_interleaving_options(pinfo);
633 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
York Sun349689b2014-04-01 14:20:49 -0700634 debug("Total mem %llu assigned\n", total_mem);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500635
636 case STEP_COMPUTE_REGS:
637 /* STEP 6: compute controller register values */
York Suna4c66502012-08-17 08:22:39 +0000638 debug("FSL Memory ctrl register computation\n");
York Sun1d71efb2014-08-01 15:51:00 -0700639 for (i = first_ctrl; i <= last_ctrl; i++) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500640 if (timing_params[i].ndimms_present == 0) {
641 memset(&ddr_reg[i], 0,
642 sizeof(fsl_ddr_cfg_regs_t));
643 continue;
644 }
645
York Sun03e664d2015-01-06 13:18:50 -0800646 compute_fsl_memctl_config_regs
647 (i,
648 &pinfo->memctl_opts[i],
649 &ddr_reg[i], &timing_params[i],
650 pinfo->dimm_params[i],
651 dbw_capacity_adjust[i],
652 size_only);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500653 }
654
655 default:
656 break;
657 }
658
York Suna4c66502012-08-17 08:22:39 +0000659 {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500660 /*
661 * Compute the amount of memory available just by
662 * looking for the highest valid CSn_BNDS value.
663 * This allows us to also experiment with using
664 * only CS0 when using dual-rank DIMMs.
665 */
666 unsigned int max_end = 0;
667
York Sun1d71efb2014-08-01 15:51:00 -0700668 for (i = first_ctrl; i <= last_ctrl; i++) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500669 for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
670 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
671 if (reg->cs[j].config & 0x80000000) {
672 unsigned int end;
York Sund8556db2013-06-25 11:37:45 -0700673 /*
674 * 0xfffffff is a special value we put
675 * for unused bnds
676 */
677 if (reg->cs[j].bnds == 0xffffffff)
678 continue;
679 end = reg->cs[j].bnds & 0xffff;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500680 if (end > max_end) {
681 max_end = end;
682 }
683 }
684 }
685 }
686
York Sun00ec3fd2013-10-28 16:36:02 -0700687 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
York Sun1d71efb2014-08-01 15:51:00 -0700688 0xFFFFFFULL) - pinfo->mem_base;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500689 }
690
691 return total_mem;
692}
693
York Sun1d71efb2014-08-01 15:51:00 -0700694phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500695{
York Sun1d71efb2014-08-01 15:51:00 -0700696 unsigned int i, first_ctrl, last_ctrl;
York Sun9ac4ffb2013-09-30 14:20:51 -0700697#ifdef CONFIG_PPC
York Suna4c66502012-08-17 08:22:39 +0000698 unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
York Sun9ac4ffb2013-09-30 14:20:51 -0700699#endif
Kumar Galae7563af2009-06-11 23:42:35 -0500700 unsigned long long total_memory;
York Sun1d71efb2014-08-01 15:51:00 -0700701 int deassert_reset = 0;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500702
York Sun1d71efb2014-08-01 15:51:00 -0700703 first_ctrl = pinfo->first_ctrl;
704 last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500705
706 /* Compute it once normally. */
York Sun6f5e1dc2011-09-16 13:21:35 -0700707#ifdef CONFIG_FSL_DDR_INTERACTIVE
Heinrich Schuchardtc670aee2020-10-07 18:11:48 +0200708 if (tstc() && (getchar() == 'd')) { /* we got a key press of 'd' */
York Sun1d71efb2014-08-01 15:51:00 -0700709 total_memory = fsl_ddr_interactive(pinfo, 0);
James Yange8ba6c52013-01-07 14:01:03 +0000710 } else if (fsl_ddr_interactive_env_var_exists()) {
York Sun1d71efb2014-08-01 15:51:00 -0700711 total_memory = fsl_ddr_interactive(pinfo, 1);
York Sune750cfa2013-01-04 08:13:59 +0000712 } else
York Sun6f5e1dc2011-09-16 13:21:35 -0700713#endif
York Sun1d71efb2014-08-01 15:51:00 -0700714 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500715
York Sunf31cfd12012-10-08 07:44:24 +0000716 /* setup 3-way interleaving before enabling DDRC */
York Sun1d71efb2014-08-01 15:51:00 -0700717 switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
718 case FSL_DDR_3WAY_1KB_INTERLEAVING:
719 case FSL_DDR_3WAY_4KB_INTERLEAVING:
720 case FSL_DDR_3WAY_8KB_INTERLEAVING:
721 fsl_ddr_set_intl3r(
722 pinfo->memctl_opts[first_ctrl].
723 memctl_interleaving_mode);
724 break;
725 default:
726 break;
York Sunf31cfd12012-10-08 07:44:24 +0000727 }
728
York Sunc63e1372013-06-25 11:37:48 -0700729 /*
730 * Program configuration registers.
731 * JEDEC specs requires clocks to be stable before deasserting reset
732 * for RDIMMs. Clocks start after chip select is enabled and clock
733 * control register is set. During step 1, all controllers have their
734 * registers set but not enabled. Step 2 proceeds after deasserting
735 * reset through board FPGA or GPIO.
736 * For non-registered DIMMs, initialization can go through but it is
737 * also OK to follow the same flow.
738 */
York Sun1d71efb2014-08-01 15:51:00 -0700739 if (pinfo->board_need_mem_reset)
740 deassert_reset = pinfo->board_need_mem_reset();
741 for (i = first_ctrl; i <= last_ctrl; i++) {
742 if (pinfo->common_timing_params[i].all_dimms_registered)
York Sunc63e1372013-06-25 11:37:48 -0700743 deassert_reset = 1;
744 }
York Sun1d71efb2014-08-01 15:51:00 -0700745 for (i = first_ctrl; i <= last_ctrl; i++) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500746 debug("Programming controller %u\n", i);
York Sun1d71efb2014-08-01 15:51:00 -0700747 if (pinfo->common_timing_params[i].ndimms_present == 0) {
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500748 debug("No dimms present on controller %u; "
749 "skipping programming\n", i);
750 continue;
751 }
York Sunc63e1372013-06-25 11:37:48 -0700752 /*
753 * The following call with step = 1 returns before enabling
754 * the controller. It has to finish with step = 2 later.
755 */
York Sun1d71efb2014-08-01 15:51:00 -0700756 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
York Sunc63e1372013-06-25 11:37:48 -0700757 deassert_reset ? 1 : 0);
758 }
759 if (deassert_reset) {
760 /* Use board FPGA or GPIO to deassert reset signal */
York Sun1d71efb2014-08-01 15:51:00 -0700761 if (pinfo->board_mem_de_reset) {
762 debug("Deasserting mem reset\n");
763 pinfo->board_mem_de_reset();
764 } else {
765 debug("Deasserting mem reset missing\n");
766 }
767 for (i = first_ctrl; i <= last_ctrl; i++) {
York Sunc63e1372013-06-25 11:37:48 -0700768 /* Call with step = 2 to continue initialization */
York Sun1d71efb2014-08-01 15:51:00 -0700769 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
York Sunc63e1372013-06-25 11:37:48 -0700770 i, 2);
771 }
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500772 }
773
York Sune32d59a2015-01-06 13:18:55 -0800774#ifdef CONFIG_FSL_DDR_SYNC_REFRESH
775 fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
776#endif
777
York Sun9ac4ffb2013-09-30 14:20:51 -0700778#ifdef CONFIG_PPC
York Suna4c66502012-08-17 08:22:39 +0000779 /* program LAWs */
York Sun1d71efb2014-08-01 15:51:00 -0700780 for (i = first_ctrl; i <= last_ctrl; i++) {
781 if (pinfo->memctl_opts[i].memctl_interleaving) {
782 switch (pinfo->memctl_opts[i].
783 memctl_interleaving_mode) {
York Suna4c66502012-08-17 08:22:39 +0000784 case FSL_DDR_CACHE_LINE_INTERLEAVING:
785 case FSL_DDR_PAGE_INTERLEAVING:
786 case FSL_DDR_BANK_INTERLEAVING:
787 case FSL_DDR_SUPERBANK_INTERLEAVING:
York Sun1d71efb2014-08-01 15:51:00 -0700788 if (i % 2)
789 break;
York Suna4c66502012-08-17 08:22:39 +0000790 if (i == 0) {
791 law_memctl = LAW_TRGT_IF_DDR_INTRLV;
York Sun1d71efb2014-08-01 15:51:00 -0700792 fsl_ddr_set_lawbar(
793 &pinfo->common_timing_params[i],
York Suna4c66502012-08-17 08:22:39 +0000794 law_memctl, i);
795 }
York Sun51370d52016-12-28 08:43:45 -0800796#if CONFIG_SYS_NUM_DDR_CTLRS > 3
York Sun1d71efb2014-08-01 15:51:00 -0700797 else if (i == 2) {
798 law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
799 fsl_ddr_set_lawbar(
800 &pinfo->common_timing_params[i],
801 law_memctl, i);
802 }
803#endif
York Suna4c66502012-08-17 08:22:39 +0000804 break;
805 case FSL_DDR_3WAY_1KB_INTERLEAVING:
806 case FSL_DDR_3WAY_4KB_INTERLEAVING:
807 case FSL_DDR_3WAY_8KB_INTERLEAVING:
808 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
809 if (i == 0) {
York Sun1d71efb2014-08-01 15:51:00 -0700810 fsl_ddr_set_lawbar(
811 &pinfo->common_timing_params[i],
York Suna4c66502012-08-17 08:22:39 +0000812 law_memctl, i);
813 }
814 break;
815 case FSL_DDR_4WAY_1KB_INTERLEAVING:
816 case FSL_DDR_4WAY_4KB_INTERLEAVING:
817 case FSL_DDR_4WAY_8KB_INTERLEAVING:
818 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
819 if (i == 0)
York Sun1d71efb2014-08-01 15:51:00 -0700820 fsl_ddr_set_lawbar(
821 &pinfo->common_timing_params[i],
York Suna4c66502012-08-17 08:22:39 +0000822 law_memctl, i);
823 /* place holder for future 4-way interleaving */
824 break;
825 default:
826 break;
827 }
828 } else {
829 switch (i) {
830 case 0:
831 law_memctl = LAW_TRGT_IF_DDR_1;
832 break;
833 case 1:
834 law_memctl = LAW_TRGT_IF_DDR_2;
835 break;
836 case 2:
837 law_memctl = LAW_TRGT_IF_DDR_3;
838 break;
839 case 3:
840 law_memctl = LAW_TRGT_IF_DDR_4;
841 break;
842 default:
843 break;
844 }
York Sun1d71efb2014-08-01 15:51:00 -0700845 fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
846 law_memctl, i);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500847 }
848 }
York Sun9ac4ffb2013-09-30 14:20:51 -0700849#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500850
York Suna4c66502012-08-17 08:22:39 +0000851 debug("total_memory by %s = %llu\n", __func__, total_memory);
Kumar Galae7563af2009-06-11 23:42:35 -0500852
853#if !defined(CONFIG_PHYS_64BIT)
854 /* Check for 4G or more. Bad. */
York Sun1d71efb2014-08-01 15:51:00 -0700855 if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
Shruti Kanetkar2f848f92013-08-15 11:25:37 -0500856 puts("Detected ");
857 print_size(total_memory, " of memory\n");
Becky Bruce7ea38712010-12-17 17:17:59 -0600858 printf(" This U-Boot only supports < 4G of DDR\n");
859 printf(" You could rebuild it with CONFIG_PHYS_64BIT\n");
Simon Glassf1683aa2017-04-06 12:47:05 -0600860 printf(" "); /* re-align to match init_dram print */
Kumar Galae7563af2009-06-11 23:42:35 -0500861 total_memory = CONFIG_MAX_MEM_MAPPED;
862 }
863#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500864
865 return total_memory;
866}
Haiying Wangfc0c2b62010-12-01 10:35:31 -0500867
868/*
York Sun1d71efb2014-08-01 15:51:00 -0700869 * fsl_ddr_sdram(void) -- this is the main function to be
Simon Glassf1683aa2017-04-06 12:47:05 -0600870 * called by dram_init() in the board file.
York Sun1d71efb2014-08-01 15:51:00 -0700871 *
872 * It returns amount of memory configured in bytes.
873 */
874phys_size_t fsl_ddr_sdram(void)
875{
876 fsl_ddr_info_t info;
877
878 /* Reset info structure. */
879 memset(&info, 0, sizeof(fsl_ddr_info_t));
880 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
881 info.first_ctrl = 0;
882 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
883 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
884 info.board_need_mem_reset = board_need_mem_reset;
885 info.board_mem_reset = board_assert_mem_reset;
886 info.board_mem_de_reset = board_deassert_mem_reset;
York Sun61bd2f72015-11-04 09:53:10 -0800887 remove_unused_controllers(&info);
York Sun1d71efb2014-08-01 15:51:00 -0700888
889 return __fsl_ddr_sdram(&info);
890}
891
892#ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
893phys_size_t fsl_other_ddr_sdram(unsigned long long base,
894 unsigned int first_ctrl,
895 unsigned int num_ctrls,
896 unsigned int dimm_slots_per_ctrl,
897 int (*board_need_reset)(void),
898 void (*board_reset)(void),
899 void (*board_de_reset)(void))
900{
901 fsl_ddr_info_t info;
902
903 /* Reset info structure. */
904 memset(&info, 0, sizeof(fsl_ddr_info_t));
905 info.mem_base = base;
906 info.first_ctrl = first_ctrl;
907 info.num_ctrls = num_ctrls;
908 info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
909 info.board_need_mem_reset = board_need_reset;
910 info.board_mem_reset = board_reset;
911 info.board_mem_de_reset = board_de_reset;
912
913 return __fsl_ddr_sdram(&info);
914}
915#endif
916
917/*
918 * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
919 * size of the total memory without setting ddr control registers.
Haiying Wangfc0c2b62010-12-01 10:35:31 -0500920 */
921phys_size_t
922fsl_ddr_sdram_size(void)
923{
924 fsl_ddr_info_t info;
925 unsigned long long total_memory = 0;
926
927 memset(&info, 0 , sizeof(fsl_ddr_info_t));
York Sun1d71efb2014-08-01 15:51:00 -0700928 info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
929 info.first_ctrl = 0;
930 info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
931 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
932 info.board_need_mem_reset = NULL;
Ed Swarthout81dfdee2016-01-14 12:28:04 -0600933 remove_unused_controllers(&info);
Haiying Wangfc0c2b62010-12-01 10:35:31 -0500934
935 /* Compute it once normally. */
936 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
937
938 return total_memory;
939}