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wdenkdb2f721f2003-03-06 00:58:30 +00001/*
2 * (C) Copyright 2001
3 * Stuart Hughes <stuarth@lineo.com>
4 * This file is based on similar values for other boards found in other
5 * U-Boot config files, and some that I found in the mpc8260ads manual.
6 *
7 * Note: my board is a PILOT rev.
8 * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
wdenk7a8e9bed2003-05-31 18:35:21 +000030 * Config header file for a MPC8266ADS Pilot 16M Ram Simm, 8Mbytes Flash Simm
31 */
32
33/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020034 !! !!
wdenk7a8e9bed2003-05-31 18:35:21 +000035 !! This configuration requires JP3 to be in position 1-2 to work !!
Wolfgang Denk14d0a022010-10-07 21:51:12 +020036 !! To make it work for the default, the CONFIG_SYS_TEXT_BASE define in !!
wdenk7a8e9bed2003-05-31 18:35:21 +000037 !! board/mpc8266ads/config.mk must be changed from 0xfe000000 to !!
38 !! 0xfff00000 !!
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 !! The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
Wolfgang Denk2b792af2005-09-24 21:54:50 +020040 !! !!
wdenk8bde7f72003-06-27 21:31:46 +000041 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
wdenkdb2f721f2003-03-06 00:58:30 +000042 */
43
44#ifndef __CONFIG_H
45#define __CONFIG_H
46
47/*
48 * High Level Configuration Options
49 * (easy to change)
50 */
51
wdenkc837dcb2004-01-20 23:12:12 +000052#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
53#define CONFIG_MPC8266ADS 1 /* ...on motorola ADS board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050054#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkdb2f721f2003-03-06 00:58:30 +000055
Wolfgang Denk2ae18242010-10-06 09:05:45 +020056#define CONFIG_SYS_TEXT_BASE 0xfe000000
57
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050059#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenkdb2f721f2003-03-06 00:58:30 +000060
61/* allow serial and ethaddr to be overwritten */
62#define CONFIG_ENV_OVERWRITE
63
64/*
65 * select serial console configuration
66 *
67 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
68 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
69 * for SCC).
70 *
71 * if CONFIG_CONS_NONE is defined, then the serial console routines must
72 * defined elsewhere (for example, on the cogent platform, there are serial
73 * ports on the motherboard which are used for the serial console - see
74 * cogent/cma101/serial.[ch]).
75 */
76#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
77#define CONFIG_CONS_ON_SCC /* define if console on SCC */
78#undef CONFIG_CONS_NONE /* define if console on something else */
79#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
80
81/*
82 * select ethernet configuration
83 *
84 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
85 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
86 * for FCC)
87 *
88 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050089 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkdb2f721f2003-03-06 00:58:30 +000090 */
91#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
92#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
93#undef CONFIG_ETHER_NONE /* define if ether on something else */
94#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk5d232d02003-05-22 22:52:13 +000095#define CONFIG_MII /* MII PHY management */
96#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
97/*
98 * Port pins used for bit-banged MII communictions (if applicable).
99 */
100#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200101#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
102 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
103#define MDC_DECLARE MDIO_DECLARE
104
wdenk5d232d02003-05-22 22:52:13 +0000105#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
106#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
107#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
108
109#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
110 else iop->pdat &= ~0x00400000
111
112#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
113 else iop->pdat &= ~0x00200000
114
115#define MIIDELAY udelay(1)
wdenkdb2f721f2003-03-06 00:58:30 +0000116
117#if (CONFIG_ETHER_INDEX == 2)
118
119/*
120 * - Rx-CLK is CLK13
121 * - Tx-CLK is CLK14
122 * - Select bus for bd/buffers (see 28-13)
123 * - Half duplex
124 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000125# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
126# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127# define CONFIG_SYS_CPMFCR_RAMTYPE 0
128# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkdb2f721f2003-03-06 00:58:30 +0000129
130#endif /* CONFIG_ETHER_INDEX */
131
132/* other options */
133#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
135#define CONFIG_SYS_I2C_SLAVE 0x7F
136#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenkdb2f721f2003-03-06 00:58:30 +0000137
wdenk5d232d02003-05-22 22:52:13 +0000138/* PCI */
139#define CONFIG_PCI
140#define CONFIG_PCI_PNP
141#define CONFIG_PCI_BOOTDELAY 0
142#undef CONFIG_PCI_SCAN_SHOW
143
wdenkdb2f721f2003-03-06 00:58:30 +0000144/*-----------------------------------------------------------------------
145 * Definitions for Serial Presence Detect EEPROM address
146 * (to get SDRAM settings)
147 */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200148#define SPD_EEPROM_ADDRESS 0x50
wdenkdb2f721f2003-03-06 00:58:30 +0000149
wdenk5d232d02003-05-22 22:52:13 +0000150#define CONFIG_8260_CLKIN 66000000 /* in Hz */
wdenkdb2f721f2003-03-06 00:58:30 +0000151#define CONFIG_BAUDRATE 115200
152
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500153/*
154 * Command line configuration.
155 */
Rune Torgersen298cd4c2007-10-17 11:56:31 -0500156#include <config_cmd_default.h>
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500157
Rune Torgersen298cd4c2007-10-17 11:56:31 -0500158/* Commands we want, that are not part of default set */
159#define CONFIG_CMD_ASKENV /* ask for env variable */
160#define CONFIG_CMD_CACHE /* icache, dcache */
161#define CONFIG_CMD_DHCP /* DHCP Support */
162#define CONFIG_CMD_DIAG /* Diagnostics */
163#define CONFIG_CMD_IMMAP /* IMMR dump support */
164#define CONFIG_CMD_IRQ /* irqinfo */
165#define CONFIG_CMD_MII /* MII support */
166#define CONFIG_CMD_PCI /* pciinfo */
167#define CONFIG_CMD_PING /* ping support */
168#define CONFIG_CMD_PORTIO /* Port I/O */
169#define CONFIG_CMD_REGINFO /* Register dump */
170#define CONFIG_CMD_SAVES /* save S record dump */
171#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */
172
173/* Commands from default set we don't need */
174#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
175#undef CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
wdenkdb2f721f2003-03-06 00:58:30 +0000176
wdenk5d232d02003-05-22 22:52:13 +0000177/* Define a command string that is automatically executed when no character
178 * is read on the console interface withing "Boot Delay" after reset.
179 */
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200180#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
181#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenk5d232d02003-05-22 22:52:13 +0000182
wdenk42dfe7a2004-03-14 22:25:36 +0000183#ifdef CONFIG_BOOT_ROOT_INITRD
wdenk5d232d02003-05-22 22:52:13 +0000184#define CONFIG_BOOTCOMMAND \
185 "version;" \
186 "echo;" \
187 "bootp;" \
188 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100189 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk5d232d02003-05-22 22:52:13 +0000190 "bootm"
191#endif /* CONFIG_BOOT_ROOT_INITRD */
192
wdenk42dfe7a2004-03-14 22:25:36 +0000193#ifdef CONFIG_BOOT_ROOT_NFS
wdenk5d232d02003-05-22 22:52:13 +0000194#define CONFIG_BOOTCOMMAND \
195 "version;" \
196 "echo;" \
197 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100198 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
199 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk5d232d02003-05-22 22:52:13 +0000200 "bootm"
201#endif /* CONFIG_BOOT_ROOT_NFS */
202
Jon Loeliger7be044e2007-07-09 21:24:19 -0500203/*
204 * BOOTP options
wdenk5d232d02003-05-22 22:52:13 +0000205 */
Jon Loeliger7be044e2007-07-09 21:24:19 -0500206#define CONFIG_BOOTP_SUBNETMASK
207#define CONFIG_BOOTP_GATEWAY
208#define CONFIG_BOOTP_HOSTNAME
209#define CONFIG_BOOTP_BOOTPATH
210#define CONFIG_BOOTP_BOOTFILESIZE
211#define CONFIG_BOOTP_DNS
wdenk5d232d02003-05-22 22:52:13 +0000212
wdenkdb2f721f2003-03-06 00:58:30 +0000213#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkdb2f721f2003-03-06 00:58:30 +0000214
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500215#if defined(CONFIG_CMD_KGDB)
wdenkdb2f721f2003-03-06 00:58:30 +0000216#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
217#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
218#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
219#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
220#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
221#endif
222
223#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
224
225/*
226 * Miscellaneous configurable options
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_LONGHELP /* undef to save memory */
229#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500230#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000232#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000234#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
236#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
237#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
240#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenkdb2f721f2003-03-06 00:58:30 +0000241
wdenk5d232d02003-05-22 22:52:13 +0000242#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
wdenkdb2f721f2003-03-06 00:58:30 +0000243 /* for versions < 2.4.5-pre5 */
244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkdb2f721f2003-03-06 00:58:30 +0000246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkdb2f721f2003-03-06 00:58:30 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkdb2f721f2003-03-06 00:58:30 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_FLASH_BASE 0xFE000000
wdenk5d232d02003-05-22 22:52:13 +0000252#define FLASH_BASE 0xFE000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
254#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
255#define CONFIG_SYS_FLASH_SIZE 8
256#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
257#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
wdenkdb2f721f2003-03-06 00:58:30 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#undef CONFIG_SYS_FLASH_CHECKSUM
wdenkdb2f721f2003-03-06 00:58:30 +0000260
261/* this is stuff came out of the Motorola docs */
262/* Only change this if you also change the Hardware configuration Word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
wdenkdb2f721f2003-03-06 00:58:30 +0000264
wdenkdb2f721f2003-03-06 00:58:30 +0000265/* Set IMMR to 0xF0000000 or above to boot Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_IMMR 0xF0000000
267#define CONFIG_SYS_BCSR 0xF8000000
268#define CONFIG_SYS_PCI_INT 0xF8200000 /* PCI interrupt controller */
wdenkdb2f721f2003-03-06 00:58:30 +0000269
270/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
271 */
272/*#define CONFIG_VERY_BIG_RAM 1*/
273
274/* What should be the base address of SDRAM DIMM and how big is
275 * it (in Mbytes)? This will normally auto-configure via the SPD.
276*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_SDRAM_BASE 0x00000000
278#define CONFIG_SYS_SDRAM_SIZE 16
wdenkdb2f721f2003-03-06 00:58:30 +0000279
280#define SDRAM_SPD_ADDR 0x50
281
wdenkdb2f721f2003-03-06 00:58:30 +0000282/*-----------------------------------------------------------------------
283 * BR2,BR3 - Base Register
284 * Ref: Section 10.3.1 on page 10-14
285 * OR2,OR3 - Option Register
286 * Ref: Section 10.3.2 on page 10-16
287 *-----------------------------------------------------------------------
288 */
289
290/* Bank 2,3 - SDRAM DIMM
291 */
292
293/* The BR2 is configured as follows:
294 *
295 * - Base address of 0x00000000
296 * - 64 bit port size (60x bus only)
297 * - Data errors checking is disabled
298 * - Read and write access
299 * - SDRAM 60x bus
300 * - Access are handled by the memory controller according to MSEL
301 * - Not used for atomic operations
302 * - No data pipelining is done
303 * - Valid
304 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000306 BRx_PS_64 |\
307 BRx_MS_SDRAM_P |\
308 BRx_V)
309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000311 BRx_PS_64 |\
312 BRx_MS_SDRAM_P |\
313 BRx_V)
314
315/* With a 64 MB DIMM, the OR2 is configured as follows:
316 *
317 * - 64 MB
318 * - 4 internal banks per device
319 * - Row start address bit is A8 with PSDMR[PBI] = 0
320 * - 12 row address lines
321 * - Back-to-back page mode
322 * - Internal bank interleaving within save device enabled
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#if (CONFIG_SYS_SDRAM_SIZE == 64)
325#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE) |\
wdenkdb2f721f2003-03-06 00:58:30 +0000326 ORxS_BPD_4 |\
327 ORxS_ROWST_PBI0_A8 |\
328 ORxS_NUMR_12)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#elif (CONFIG_SYS_SDRAM_SIZE == 16)
330#define CONFIG_SYS_OR2_PRELIM (0xFF000C80)
wdenkdb2f721f2003-03-06 00:58:30 +0000331#else
332#error "INVALID SDRAM CONFIGURATION"
333#endif
334
335/*-----------------------------------------------------------------------
336 * PSDMR - 60x Bus SDRAM Mode Register
337 * Ref: Section 10.3.3 on page 10-21
338 *-----------------------------------------------------------------------
339 */
340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#if (CONFIG_SYS_SDRAM_SIZE == 64)
wdenkdb2f721f2003-03-06 00:58:30 +0000342/* With a 64 MB DIMM, the PSDMR is configured as follows:
343 *
344 * - Bank Based Interleaving,
345 * - Refresh Enable,
346 * - Address Multiplexing where A5 is output on A14 pin
347 * (A6 on A15, and so on),
348 * - use address pins A14-A16 as bank select,
349 * - A9 is output on SDA10 during an ACTIVATE command,
350 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
351 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
352 * is 3 clocks,
353 * - earliest timing for READ/WRITE command after ACTIVATE command is
354 * 2 clocks,
355 * - earliest timing for PRECHARGE after last data was read is 1 clock,
356 * - earliest timing for PRECHARGE after last data was written is 1 clock,
357 * - CAS Latency is 2.
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenkdb2f721f2003-03-06 00:58:30 +0000360 PSDMR_SDAM_A14_IS_A5 |\
361 PSDMR_BSMA_A14_A16 |\
362 PSDMR_SDA10_PBI0_A9 |\
363 PSDMR_RFRC_7_CLK |\
364 PSDMR_PRETOACT_3W |\
365 PSDMR_ACTTORW_2W |\
366 PSDMR_LDOTOPRE_1C |\
367 PSDMR_WRC_1C |\
368 PSDMR_CL_2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#elif (CONFIG_SYS_SDRAM_SIZE == 16)
wdenkdb2f721f2003-03-06 00:58:30 +0000370/* With a 16 MB DIMM, the PSDMR is configured as follows:
371 *
372 * configuration parameters found in Motorola documentation
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_PSDMR (0x016EB452)
wdenkdb2f721f2003-03-06 00:58:30 +0000375#else
376#error "INVALID SDRAM CONFIGURATION"
377#endif
378
wdenkdb2f721f2003-03-06 00:58:30 +0000379#define RS232EN_1 0x02000002
380#define RS232EN_2 0x01000001
381#define FETHIEN 0x08000008
382#define FETH_RST 0x04000004
383
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200385#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200386#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkdb2f721f2003-03-06 00:58:30 +0000388
wdenk7a8e9bed2003-05-31 18:35:21 +0000389/* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */
wdenk5d232d02003-05-22 22:52:13 +0000390/* 0x0EB2B645 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\
wdenk5d232d02003-05-22 22:52:13 +0000392 ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB010 ) |\
393 ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
394 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
wdenkdb2f721f2003-03-06 00:58:30 +0000395 )
wdenk5d232d02003-05-22 22:52:13 +0000396
wdenk7a8e9bed2003-05-31 18:35:21 +0000397/* Use this HRCW for booting from address 0xfff0000 (JP3 in setting 2-3) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398/* #define CONFIG_SYS_HRCW_MASTER 0x0cb23645 */
wdenkdb2f721f2003-03-06 00:58:30 +0000399
wdenk8bde7f72003-06-27 21:31:46 +0000400/* This value should actually be situated in the first 256 bytes of the FLASH
wdenkdb2f721f2003-03-06 00:58:30 +0000401 which on the standard MPC8266ADS board is at address 0xFF800000
402 The linker script places it at 0xFFF00000 instead.
403
wdenk8bde7f72003-06-27 21:31:46 +0000404 It still works, however, as long as the ADS board jumper JP3 is set to
405 position 2-3 so the board is using the BCSR as Hardware Configuration Word
wdenkdb2f721f2003-03-06 00:58:30 +0000406
wdenk8bde7f72003-06-27 21:31:46 +0000407 If you want to use the one defined here instead, ust copy the first 256 bytes from
408 0xfff00000 to 0xff800000 (for 8MB flash)
wdenkdb2f721f2003-03-06 00:58:30 +0000409
410 - Rune
411
wdenk7a8e9bed2003-05-31 18:35:21 +0000412*/
wdenkdb2f721f2003-03-06 00:58:30 +0000413
414/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_HRCW_SLAVE1 0
416#define CONFIG_SYS_HRCW_SLAVE2 0
417#define CONFIG_SYS_HRCW_SLAVE3 0
418#define CONFIG_SYS_HRCW_SLAVE4 0
419#define CONFIG_SYS_HRCW_SLAVE5 0
420#define CONFIG_SYS_HRCW_SLAVE6 0
421#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkdb2f721f2003-03-06 00:58:30 +0000422
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200423#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Peter Tyserd98b0522010-10-14 23:33:24 -0500424
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
426# define CONFIG_SYS_RAMBOOT
wdenkdb2f721f2003-03-06 00:58:30 +0000427#endif
428
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
430#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
431#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdb2f721f2003-03-06 00:58:30 +0000432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200434# define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200436# define CONFIG_ENV_SECT_SIZE 0x40000
wdenkdb2f721f2003-03-06 00:58:30 +0000437#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200438# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200440# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#endif /* CONFIG_SYS_RAMBOOT */
wdenkdb2f721f2003-03-06 00:58:30 +0000442
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger1cc4c452007-07-04 22:30:28 -0500444#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkdb2f721f2003-03-06 00:58:30 +0000446#endif
447
wdenk7a8e9bed2003-05-31 18:35:21 +0000448/*-----------------------------------------------------------------------
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200449 * HIDx - Hardware Implementation-dependent Registers 2-11
wdenk7a8e9bed2003-05-31 18:35:21 +0000450 *-----------------------------------------------------------------------
451 * HID0 also contains cache control - initially enable both caches and
452 * invalidate contents, then the final state leaves only the instruction
453 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
454 * but Soft reset does not.
455 *
456 * HID1 has only read-only information - nothing to set.
457 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458/*#define CONFIG_SYS_HID0_INIT 0 */
459#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenk7a8e9bed2003-05-31 18:35:21 +0000460 HID0_DCE |\
461 HID0_ICFI |\
462 HID0_DCI |\
463 HID0_IFEM |\
464 HID0_ABE)
465
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
wdenkdb2f721f2003-03-06 00:58:30 +0000467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_HID2 0
wdenkdb2f721f2003-03-06 00:58:30 +0000469
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_SYPCR 0xFFFFFFC3
471#define CONFIG_SYS_BCR 0x004C0000
472#define CONFIG_SYS_SIUMCR 0x4E64C000
473#define CONFIG_SYS_SCCR 0x00000000
wdenkdb2f721f2003-03-06 00:58:30 +0000474
wdenk5d232d02003-05-22 22:52:13 +0000475/* local bus memory map
476 *
477 * 0x00000000-0x03FFFFFF 64MB SDRAM
478 * 0x80000000-0x9FFFFFFF 512MB outbound prefetchable PCI memory window
479 * 0xA0000000-0xBFFFFFFF 512MB outbound non-prefetchable PCI memory window
480 * 0xF0000000-0xF001FFFF 128KB MPC8266 internal memory
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200481 * 0xF4000000-0xF7FFFFFF 64MB outbound PCI I/O window
wdenk5d232d02003-05-22 22:52:13 +0000482 * 0xF8000000-0xF8007FFF 32KB BCSR
483 * 0xF8100000-0xF8107FFF 32KB ATM UNI
484 * 0xF8200000-0xF8207FFF 32KB PCI interrupt controller
485 * 0xF8300000-0xF8307FFF 32KB EEPROM
486 * 0xFE000000-0xFFFFFFFF 32MB flash
487 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_BR0_PRELIM 0xFE001801 /* flash */
489#define CONFIG_SYS_OR0_PRELIM 0xFE000836
490#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x1801) /* BCSR */
491#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
492#define CONFIG_SYS_BR4_PRELIM 0xF8300801 /* EEPROM */
493#define CONFIG_SYS_OR4_PRELIM 0xFFFF8846
494#define CONFIG_SYS_BR5_PRELIM 0xF8100801 /* PM5350 ATM UNI */
495#define CONFIG_SYS_OR5_PRELIM 0xFFFF8E36
496#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
497#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
wdenk5d232d02003-05-22 22:52:13 +0000498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_RMR 0x0001
500#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
501#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
502#define CONFIG_SYS_RCCR 0
503#define CONFIG_SYS_MPTPR 0x00001900
504#define CONFIG_SYS_PSRT 0x00000021
wdenkdb2f721f2003-03-06 00:58:30 +0000505
wdenk65bd0e22003-09-18 10:45:21 +0000506/* This address must not exist */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_RESET_ADDRESS 0xFCFFFF00
wdenkdb2f721f2003-03-06 00:58:30 +0000508
wdenk5d232d02003-05-22 22:52:13 +0000509/* PCI Memory map (if different from default map */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
511#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
512#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
wdenk8bde7f72003-06-27 21:31:46 +0000513 PICMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000514
wdenk8bde7f72003-06-27 21:31:46 +0000515/*
wdenk5d232d02003-05-22 22:52:13 +0000516 * These are the windows that allow the CPU to access PCI address space.
wdenk8bde7f72003-06-27 21:31:46 +0000517 * All three PCI master windows, which allow the CPU to access PCI
518 * prefetch, non prefetch, and IO space (see below), must all fit within
wdenk5d232d02003-05-22 22:52:13 +0000519 * these windows.
520 */
521
522/* PCIBR0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_PCI_MSTR0_LOCAL 0x80000000 /* Local base */
524#define CONFIG_SYS_PCIMSK0_MASK PCIMSK_1GB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000525/* PCIBR1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#define CONFIG_SYS_PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
527#define CONFIG_SYS_PCIMSK1_MASK PCIMSK_64MB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000528
wdenk8bde7f72003-06-27 21:31:46 +0000529/*
wdenk5d232d02003-05-22 22:52:13 +0000530 * Master window that allows the CPU to access PCI Memory (prefetch).
531 * This window will be setup with the first set of Outbound ATU registers
532 * in the bridge.
533 */
534
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
536#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
537#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
538#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
539#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000540
wdenk8bde7f72003-06-27 21:31:46 +0000541/*
wdenk5d232d02003-05-22 22:52:13 +0000542 * Master window that allows the CPU to access PCI Memory (non-prefetch).
543 * This window will be setup with the second set of Outbound ATU registers
544 * in the bridge.
545 */
546
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
548#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
549#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
550#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
551#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
wdenk5d232d02003-05-22 22:52:13 +0000552
wdenk8bde7f72003-06-27 21:31:46 +0000553/*
wdenk5d232d02003-05-22 22:52:13 +0000554 * Master window that allows the CPU to access PCI IO space.
555 * This window will be setup with the third set of Outbound ATU registers
556 * in the bridge.
557 */
558
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
560#define CONFIG_SYS_PCI_MSTR_IO_BUS 0xF4000000 /* PCI base */
561#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
562#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
563#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_64MB | POCMR_ENABLE | POCMR_PCI_IO)
wdenk5d232d02003-05-22 22:52:13 +0000564
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200565/*
566 * JFFS2 partitions
567 *
568 */
569/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100570#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200571#define CONFIG_JFFS2_DEV "nor0"
572#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
573#define CONFIG_JFFS2_PART_OFFSET 0x00000000
574
575/* mtdparts command line support */
576/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100577#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200578#define MTDIDS_DEFAULT ""
579#define MTDPARTS_DEFAULT ""
580*/
wdenk5d232d02003-05-22 22:52:13 +0000581
wdenkdb2f721f2003-03-06 00:58:30 +0000582#endif /* __CONFIG_H */