blob: a730f5c4fec0903fd3aa9f7d2be82a06b3f25538 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Tom Warren4e5ae092011-06-17 06:27:28 +00002/*
Allen Martin00a27492012-08-31 08:30:00 +00003 * NVIDIA Tegra20 GPIO handling.
Stephen Warrenfe828572015-09-25 10:44:08 -06004 * (C) Copyright 2010-2012,2015
Tom Warren4e5ae092011-06-17 06:27:28 +00005 * NVIDIA Corporation <www.nvidia.com>
Tom Warren4e5ae092011-06-17 06:27:28 +00006 */
7
8/*
9 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
10 * Tom Warren (twarren@nvidia.com)
11 */
12
13#include <common.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060014#include <dm.h>
15#include <malloc.h>
16#include <errno.h>
17#include <fdtdec.h>
Tom Warren4e5ae092011-06-17 06:27:28 +000018#include <asm/io.h>
19#include <asm/bitops.h>
Tom Warren150c2492012-09-19 15:50:56 -070020#include <asm/arch/tegra.h>
Tom Warren4e5ae092011-06-17 06:27:28 +000021#include <asm/gpio.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060022#include <dm/device-internal.h>
Simon Glass838aa5c2015-01-05 20:05:33 -070023#include <dt-bindings/gpio/gpio.h>
Simon Glass2fccd2d2014-09-03 17:37:03 -060024
Stephen Warrenfe828572015-09-25 10:44:08 -060025static const int CONFIG_SFIO = 0;
26static const int CONFIG_GPIO = 1;
27static const int DIRECTION_INPUT = 0;
28static const int DIRECTION_OUTPUT = 1;
29
Simon Glass2fccd2d2014-09-03 17:37:03 -060030struct tegra_gpio_platdata {
31 struct gpio_ctlr_bank *bank;
32 const char *port_name; /* Name of port, e.g. "B" */
33 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
34};
Tom Warren4e5ae092011-06-17 06:27:28 +000035
Simon Glass2fccd2d2014-09-03 17:37:03 -060036/* Information about each port at run-time */
37struct tegra_port_info {
Simon Glass2fccd2d2014-09-03 17:37:03 -060038 struct gpio_ctlr_bank *bank;
39 int base_gpio; /* Port number for this port (0, 1,.., n-1) */
40};
Tom Warren4e5ae092011-06-17 06:27:28 +000041
Stephen Warrenfe828572015-09-25 10:44:08 -060042/* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
Joe Hershberger365d6072011-11-11 15:55:36 -060043static int get_config(unsigned gpio)
Tom Warren4e5ae092011-06-17 06:27:28 +000044{
Joe Hershberger365d6072011-11-11 15:55:36 -060045 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
46 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000047 u32 u;
48 int type;
49
Joe Hershberger365d6072011-11-11 15:55:36 -060050 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
Stephen Warrenfe828572015-09-25 10:44:08 -060051 type = (u >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +000052
53 debug("get_config: port = %d, bit = %d is %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060054 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
Tom Warren4e5ae092011-06-17 06:27:28 +000055
Stephen Warrenfe828572015-09-25 10:44:08 -060056 return type ? CONFIG_GPIO : CONFIG_SFIO;
Tom Warren4e5ae092011-06-17 06:27:28 +000057}
58
Stephen Warrenfe828572015-09-25 10:44:08 -060059/* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
Joe Hershberger365d6072011-11-11 15:55:36 -060060static void set_config(unsigned gpio, int type)
Tom Warren4e5ae092011-06-17 06:27:28 +000061{
Joe Hershberger365d6072011-11-11 15:55:36 -060062 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
63 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000064 u32 u;
65
66 debug("set_config: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060067 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
Tom Warren4e5ae092011-06-17 06:27:28 +000068
Joe Hershberger365d6072011-11-11 15:55:36 -060069 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
Stephen Warrenfe828572015-09-25 10:44:08 -060070 if (type != CONFIG_SFIO)
Joe Hershberger365d6072011-11-11 15:55:36 -060071 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +000072 else
Joe Hershberger365d6072011-11-11 15:55:36 -060073 u &= ~(1 << GPIO_BIT(gpio));
74 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +000075}
76
Joe Hershberger365d6072011-11-11 15:55:36 -060077/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
78static int get_direction(unsigned gpio)
Tom Warren4e5ae092011-06-17 06:27:28 +000079{
Joe Hershberger365d6072011-11-11 15:55:36 -060080 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
81 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000082 u32 u;
83 int dir;
84
Joe Hershberger365d6072011-11-11 15:55:36 -060085 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
86 dir = (u >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +000087
88 debug("get_direction: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -060089 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
Tom Warren4e5ae092011-06-17 06:27:28 +000090
Stephen Warrenfe828572015-09-25 10:44:08 -060091 return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
Tom Warren4e5ae092011-06-17 06:27:28 +000092}
93
Joe Hershberger365d6072011-11-11 15:55:36 -060094/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
95static void set_direction(unsigned gpio, int output)
Tom Warren4e5ae092011-06-17 06:27:28 +000096{
Joe Hershberger365d6072011-11-11 15:55:36 -060097 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
98 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +000099 u32 u;
100
101 debug("set_direction: port = %d, bit = %d, %s\n",
Joe Hershberger365d6072011-11-11 15:55:36 -0600102 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
Tom Warren4e5ae092011-06-17 06:27:28 +0000103
Joe Hershberger365d6072011-11-11 15:55:36 -0600104 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
Stephen Warrenfe828572015-09-25 10:44:08 -0600105 if (output != DIRECTION_INPUT)
Joe Hershberger365d6072011-11-11 15:55:36 -0600106 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +0000107 else
Joe Hershberger365d6072011-11-11 15:55:36 -0600108 u &= ~(1 << GPIO_BIT(gpio));
109 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000110}
111
Joe Hershberger365d6072011-11-11 15:55:36 -0600112/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
113static void set_level(unsigned gpio, int high)
Tom Warren4e5ae092011-06-17 06:27:28 +0000114{
Joe Hershberger365d6072011-11-11 15:55:36 -0600115 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
116 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
Tom Warren4e5ae092011-06-17 06:27:28 +0000117 u32 u;
118
119 debug("set_level: port = %d, bit %d == %d\n",
Joe Hershberger365d6072011-11-11 15:55:36 -0600120 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
Tom Warren4e5ae092011-06-17 06:27:28 +0000121
Joe Hershberger365d6072011-11-11 15:55:36 -0600122 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000123 if (high)
Joe Hershberger365d6072011-11-11 15:55:36 -0600124 u |= 1 << GPIO_BIT(gpio);
Tom Warren4e5ae092011-06-17 06:27:28 +0000125 else
Joe Hershberger365d6072011-11-11 15:55:36 -0600126 u &= ~(1 << GPIO_BIT(gpio));
127 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000128}
129
130/*
131 * Generic_GPIO primitives.
132 */
133
Joe Hershberger365d6072011-11-11 15:55:36 -0600134/* set GPIO pin 'gpio' as an input */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600135static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000136{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600137 struct tegra_port_info *state = dev_get_priv(dev);
Tom Warren4e5ae092011-06-17 06:27:28 +0000138
139 /* Configure GPIO direction as input. */
Stephen Warrenfe828572015-09-25 10:44:08 -0600140 set_direction(state->base_gpio + offset, DIRECTION_INPUT);
Tom Warren4e5ae092011-06-17 06:27:28 +0000141
Stephen Warren0c35e3a2015-09-23 12:13:00 -0600142 /* Enable the pin as a GPIO */
143 set_config(state->base_gpio + offset, 1);
144
Tom Warren4e5ae092011-06-17 06:27:28 +0000145 return 0;
146}
147
Joe Hershberger365d6072011-11-11 15:55:36 -0600148/* set GPIO pin 'gpio' as an output, with polarity 'value' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600149static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
150 int value)
Tom Warren4e5ae092011-06-17 06:27:28 +0000151{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600152 struct tegra_port_info *state = dev_get_priv(dev);
153 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000154
155 /* Configure GPIO output value. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600156 set_level(gpio, value);
Tom Warren4e5ae092011-06-17 06:27:28 +0000157
158 /* Configure GPIO direction as output. */
Stephen Warrenfe828572015-09-25 10:44:08 -0600159 set_direction(gpio, DIRECTION_OUTPUT);
Tom Warren4e5ae092011-06-17 06:27:28 +0000160
Stephen Warren0c35e3a2015-09-23 12:13:00 -0600161 /* Enable the pin as a GPIO */
162 set_config(state->base_gpio + offset, 1);
163
Tom Warren4e5ae092011-06-17 06:27:28 +0000164 return 0;
165}
166
Joe Hershberger365d6072011-11-11 15:55:36 -0600167/* read GPIO IN value of pin 'gpio' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600168static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000169{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600170 struct tegra_port_info *state = dev_get_priv(dev);
171 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000172 int val;
173
Simon Glass2fccd2d2014-09-03 17:37:03 -0600174 debug("%s: pin = %d (port %d:bit %d)\n", __func__,
175 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
176
Simon Glass651827c2016-01-30 16:37:45 -0700177 if (get_direction(gpio) == DIRECTION_INPUT)
178 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
179 else
180 val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
Tom Warren4e5ae092011-06-17 06:27:28 +0000181
Joe Hershberger365d6072011-11-11 15:55:36 -0600182 return (val >> GPIO_BIT(gpio)) & 1;
Tom Warren4e5ae092011-06-17 06:27:28 +0000183}
184
Joe Hershberger365d6072011-11-11 15:55:36 -0600185/* write GPIO OUT value to pin 'gpio' */
Simon Glass2fccd2d2014-09-03 17:37:03 -0600186static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
Tom Warren4e5ae092011-06-17 06:27:28 +0000187{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600188 struct tegra_port_info *state = dev_get_priv(dev);
189 int gpio = state->base_gpio + offset;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600190
Tom Warren4e5ae092011-06-17 06:27:28 +0000191 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
Simon Glass2fccd2d2014-09-03 17:37:03 -0600192 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
Tom Warren4e5ae092011-06-17 06:27:28 +0000193
194 /* Configure GPIO output value. */
Joe Hershberger365d6072011-11-11 15:55:36 -0600195 set_level(gpio, value);
196
197 return 0;
Tom Warren4e5ae092011-06-17 06:27:28 +0000198}
199
Stephen Warreneceb3f22014-04-22 14:37:53 -0600200void gpio_config_table(const struct tegra_gpio_config *config, int len)
201{
202 int i;
203
204 for (i = 0; i < len; i++) {
205 switch (config[i].init) {
206 case TEGRA_GPIO_INIT_IN:
Stephen Warrenfe828572015-09-25 10:44:08 -0600207 set_direction(config[i].gpio, DIRECTION_INPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600208 break;
209 case TEGRA_GPIO_INIT_OUT0:
Stephen Warrenf9d3cab2015-09-23 12:12:59 -0600210 set_level(config[i].gpio, 0);
Stephen Warrenfe828572015-09-25 10:44:08 -0600211 set_direction(config[i].gpio, DIRECTION_OUTPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600212 break;
213 case TEGRA_GPIO_INIT_OUT1:
Stephen Warrenf9d3cab2015-09-23 12:12:59 -0600214 set_level(config[i].gpio, 1);
Stephen Warrenfe828572015-09-25 10:44:08 -0600215 set_direction(config[i].gpio, DIRECTION_OUTPUT);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600216 break;
217 }
Stephen Warrenfe828572015-09-25 10:44:08 -0600218 set_config(config[i].gpio, CONFIG_GPIO);
Stephen Warreneceb3f22014-04-22 14:37:53 -0600219 }
220}
221
Simon Glass2fccd2d2014-09-03 17:37:03 -0600222static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
Tom Warren4e5ae092011-06-17 06:27:28 +0000223{
Simon Glass2fccd2d2014-09-03 17:37:03 -0600224 struct tegra_port_info *state = dev_get_priv(dev);
225 int gpio = state->base_gpio + offset;
Tom Warren4e5ae092011-06-17 06:27:28 +0000226
Simon Glass2fccd2d2014-09-03 17:37:03 -0600227 if (!get_config(gpio))
228 return GPIOF_FUNC;
229 else if (get_direction(gpio))
230 return GPIOF_OUTPUT;
231 else
232 return GPIOF_INPUT;
Tom Warren4e5ae092011-06-17 06:27:28 +0000233}
Simon Glass2fccd2d2014-09-03 17:37:03 -0600234
Simon Glass838aa5c2015-01-05 20:05:33 -0700235static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
Simon Glass3a571232017-05-18 20:09:18 -0600236 struct ofnode_phandle_args *args)
Simon Glass838aa5c2015-01-05 20:05:33 -0700237{
238 int gpio, port, ret;
239
240 gpio = args->args[0];
241 port = gpio / TEGRA_GPIOS_PER_PORT;
242 ret = device_get_child(dev, port, &desc->dev);
243 if (ret)
244 return ret;
245 desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
246 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
247
248 return 0;
249}
250
Simon Glass2fccd2d2014-09-03 17:37:03 -0600251static const struct dm_gpio_ops gpio_tegra_ops = {
Simon Glass2fccd2d2014-09-03 17:37:03 -0600252 .direction_input = tegra_gpio_direction_input,
253 .direction_output = tegra_gpio_direction_output,
254 .get_value = tegra_gpio_get_value,
255 .set_value = tegra_gpio_set_value,
256 .get_function = tegra_gpio_get_function,
Simon Glass838aa5c2015-01-05 20:05:33 -0700257 .xlate = tegra_gpio_xlate,
Simon Glass2fccd2d2014-09-03 17:37:03 -0600258};
259
260/**
261 * Returns the name of a GPIO port
262 *
263 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
264 *
265 * @base_port: Base port number (0, 1..n-1)
266 * @return allocated string containing the name
267 */
268static char *gpio_port_name(int base_port)
269{
270 char *name, *s;
271
272 name = malloc(3);
273 if (name) {
274 s = name;
275 *s++ = 'A' + (base_port % 26);
276 if (base_port >= 26)
277 *s++ = *name;
278 *s = '\0';
279 }
280
281 return name;
282}
283
284static const struct udevice_id tegra_gpio_ids[] = {
285 { .compatible = "nvidia,tegra30-gpio" },
286 { .compatible = "nvidia,tegra20-gpio" },
287 { }
288};
289
290static int gpio_tegra_probe(struct udevice *dev)
291{
Simon Glasse564f052015-03-05 12:25:20 -0700292 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Simon Glass2fccd2d2014-09-03 17:37:03 -0600293 struct tegra_port_info *priv = dev->priv;
294 struct tegra_gpio_platdata *plat = dev->platdata;
295
296 /* Only child devices have ports */
297 if (!plat)
298 return 0;
299
300 priv->bank = plat->bank;
301 priv->base_gpio = plat->base_gpio;
302
303 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
304 uc_priv->bank_name = plat->port_name;
305
306 return 0;
307}
308
309/**
310 * We have a top-level GPIO device with no actual GPIOs. It has a child
311 * device for each Tegra port.
312 */
313static int gpio_tegra_bind(struct udevice *parent)
314{
315 struct tegra_gpio_platdata *plat = parent->platdata;
316 struct gpio_ctlr *ctlr;
317 int bank_count;
318 int bank;
319 int ret;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600320
321 /* If this is a child device, there is nothing to do here */
322 if (plat)
323 return 0;
324
Simon Glassbdfb3412015-03-03 08:02:59 -0700325 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
326#ifdef CONFIG_SPL_BUILD
327 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
328 bank_count = TEGRA_GPIO_BANKS;
329#else
330 {
331 int len;
332
Simon Glass2fccd2d2014-09-03 17:37:03 -0600333 /*
334 * This driver does not make use of interrupts, other than to figure
335 * out the number of GPIO banks
336 */
Simon Glass56f5c402017-07-25 08:30:03 -0600337 len = dev_read_size(parent, "interrupts");
338 if (len < 0)
339 return len;
Simon Glass2fccd2d2014-09-03 17:37:03 -0600340 bank_count = len / 3 / sizeof(u32);
Simon Glass56f5c402017-07-25 08:30:03 -0600341 ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
342 if ((ulong)ctlr == FDT_ADDR_T_NONE)
343 return -EINVAL;
Simon Glassbdfb3412015-03-03 08:02:59 -0700344 }
345#endif
Simon Glass2fccd2d2014-09-03 17:37:03 -0600346 for (bank = 0; bank < bank_count; bank++) {
347 int port;
348
349 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
350 struct tegra_gpio_platdata *plat;
351 struct udevice *dev;
352 int base_port;
353
354 plat = calloc(1, sizeof(*plat));
355 if (!plat)
356 return -ENOMEM;
357 plat->bank = &ctlr->gpio_bank[bank];
358 base_port = bank * TEGRA_PORTS_PER_BANK + port;
359 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
360 plat->port_name = gpio_port_name(base_port);
361
362 ret = device_bind(parent, parent->driver,
363 plat->port_name, plat, -1, &dev);
364 if (ret)
365 return ret;
Simon Glasse160f7d2017-01-17 16:52:55 -0700366 dev_set_of_offset(dev, dev_of_offset(parent));
Simon Glass2fccd2d2014-09-03 17:37:03 -0600367 }
368 }
369
370 return 0;
371}
372
373U_BOOT_DRIVER(gpio_tegra) = {
374 .name = "gpio_tegra",
375 .id = UCLASS_GPIO,
376 .of_match = tegra_gpio_ids,
377 .bind = gpio_tegra_bind,
378 .probe = gpio_tegra_probe,
379 .priv_auto_alloc_size = sizeof(struct tegra_port_info),
380 .ops = &gpio_tegra_ops,
381};