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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0cb61d7dddb0d8c087f6df46a74815950668c97b / . / include / ppc405.h
blob: a0dbbc3d961c7902c62b0f8431f09b00115a58ba [file] [log] [blame]
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]1/*----------------------------------------------------------------------------+
2|
3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
9|
10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
13|
14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
17|
18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20+----------------------------------------------------------------------------*/
21
22#ifndef __PPC405_H__
23#define __PPC405_H__
24
25/*--------------------------------------------------------------------- */
26/* Special Purpose Registers */
27/*--------------------------------------------------------------------- */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]28 #define srr2 0x3de /* save/restore register 2 */
29 #define srr3 0x3df /* save/restore register 3 */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]30 #define dbsr 0x3f0 /* debug status register */
31 #define dbcr0 0x3f2 /* debug control register 0 */
32 #define dbcr1 0x3bd /* debug control register 1 */
33 #define iac1 0x3f4 /* instruction address comparator 1 */
34 #define iac2 0x3f5 /* instruction address comparator 2 */
35 #define iac3 0x3b4 /* instruction address comparator 3 */
36 #define iac4 0x3b5 /* instruction address comparator 4 */
37 #define dac1 0x3f6 /* data address comparator 1 */
38 #define dac2 0x3f7 /* data address comparator 2 */
39 #define dccr 0x3fa /* data cache control register */
40 #define iccr 0x3fb /* instruction cache control register */
41 #define esr 0x3d4 /* execption syndrome register */
42 #define dear 0x3d5 /* data exeption address register */
43 #define evpr 0x3d6 /* exeption vector prefix register */
44 #define tsr 0x3d8 /* timer status register */
45 #define tcr 0x3da /* timer control register */
46 #define pit 0x3db /* programmable interval timer */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]47 #define sgr 0x3b9 /* storage guarded reg */
48 #define dcwr 0x3ba /* data cache write-thru reg*/
49 #define sler 0x3bb /* storage little-endian reg */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]50 #define cdbcr 0x3d7 /* cache debug cntrl reg */
51 #define icdbdr 0x3d3 /* instr cache dbug data reg*/
52 #define ccr0 0x3b3 /* core configuration register */
53 #define dvc1 0x3b6 /* data value compare register 1 */
54 #define dvc2 0x3b7 /* data value compare register 2 */
55 #define pid 0x3b1 /* process ID */
56 #define su0r 0x3bc /* storage user-defined register 0 */
57 #define zpr 0x3b0 /* zone protection regsiter */
58
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]59 #define tbl 0x11c /* time base lower - privileged write */
60 #define tbu 0x11d /* time base upper - privileged write */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]61
62 #define sprg4r 0x104 /* Special purpose general 4 - read only */
63 #define sprg5r 0x105 /* Special purpose general 5 - read only */
64 #define sprg6r 0x106 /* Special purpose general 6 - read only */
65 #define sprg7r 0x107 /* Special purpose general 7 - read only */
66 #define sprg4w 0x114 /* Special purpose general 4 - write only */
67 #define sprg5w 0x115 /* Special purpose general 5 - write only */
68 #define sprg6w 0x116 /* Special purpose general 6 - write only */
69 #define sprg7w 0x117 /* Special purpose general 7 - write only */
70
71/******************************************************************************
72 * Special for PPC405GP
73 ******************************************************************************/
74
75/******************************************************************************
76 * DMA
77 ******************************************************************************/
78#define DMA_DCR_BASE 0x100
79#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
80#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
81#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
82#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
83#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
84#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
85#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
86#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
87#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
88#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
89#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
90#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
91#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
92#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
93#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
94#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
95#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
96#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
97#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
98#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
99#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
100#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
101#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
102
103/******************************************************************************
104 * Universal interrupt controller
105 ******************************************************************************/
106#define UIC_DCR_BASE 0xc0
107#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
108#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
109#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
110#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
111#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
112#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
113#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
114#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
115#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
116
117/*-----------------------------------------------------------------------------+
118| Universal interrupt controller interrupts
119+-----------------------------------------------------------------------------*/
120#define UIC_UART0 0x80000000 /* UART 0 */
121#define UIC_UART1 0x40000000 /* UART 1 */
122#define UIC_IIC 0x20000000 /* IIC */
123#define UIC_EXT_MAST 0x10000000 /* External Master */
124#define UIC_PCI 0x08000000 /* PCI write to command reg */
125#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
126#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
127#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
128#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
129#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
130#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
131#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
132#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
133#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
134#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
135#define UIC_ENET 0x00010000 /* Ethernet */
136#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
137#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error */
138#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
139#define UIC_EXT0 0x00000040 /* External interrupt 0 */
140#define UIC_EXT1 0x00000020 /* External interrupt 1 */
141#define UIC_EXT2 0x00000010 /* External interrupt 2 */
142#define UIC_EXT3 0x00000008 /* External interrupt 3 */
143#define UIC_EXT4 0x00000004 /* External interrupt 4 */
144#define UIC_EXT5 0x00000002 /* External interrupt 5 */
145#define UIC_EXT6 0x00000001 /* External interrupt 6 */
146
147/******************************************************************************
148 * SDRAM Controller
149 ******************************************************************************/
150#define SDRAM_DCR_BASE 0x10
151#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
152#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
153 /* values for memcfga register - indirect addressing of these regs */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]154#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]155 #define mem_besra 0x00 /* bus error syndrome reg a */
156 #define mem_besrsa 0x04 /* bus error syndrome reg set a */
157 #define mem_besrb 0x08 /* bus error syndrome reg b */
158 #define mem_besrsb 0x0c /* bus error syndrome reg set b */
159 #define mem_bear 0x10 /* bus error address reg */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]160#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]161 #define mem_mcopt1 0x20 /* memory controller options 1 */
162 #define mem_rtr 0x30 /* refresh timer reg */
163 #define mem_pmit 0x34 /* power management idle timer */
164 #define mem_mb0cf 0x40 /* memory bank 0 configuration */
165 #define mem_mb1cf 0x44 /* memory bank 1 configuration */
166 #define mem_mb2cf 0x48 /* memory bank 2 configuration */
167 #define mem_mb3cf 0x4c /* memory bank 3 configuration */
168 #define mem_sdtr1 0x80 /* timing reg 1 */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]169#ifndef CONFIG_405EP
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]170 #define mem_ecccf 0x94 /* ECC configuration */
171 #define mem_eccerr 0x98 /* ECC error status */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]172#endif
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]173
174/******************************************************************************
175 * Decompression Controller
176 ******************************************************************************/
177#define DECOMP_DCR_BASE 0x14
178#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
179#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
180 /* values for kiar register - indirect addressing of these regs */
181 #define kitor0 0x00 /* index table origin register 0 */
182 #define kitor1 0x01 /* index table origin register 1 */
183 #define kitor2 0x02 /* index table origin register 2 */
184 #define kitor3 0x03 /* index table origin register 3 */
185 #define kaddr0 0x04 /* address decode definition regsiter 0 */
186 #define kaddr1 0x05 /* address decode definition regsiter 1 */
187 #define kconf 0x40 /* decompression core config register */
188 #define kid 0x41 /* decompression core ID register */
189 #define kver 0x42 /* decompression core version # reg */
190 #define kpear 0x50 /* bus error addr reg (PLB addr) */
191 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
192 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
193 #define kesr0s 0x53 /* bus error status reg 0 (set) */
194 /* There are 0x400 of the following registers, from krom0 to krom3ff*/
195 /* Only the first one is given here. */
196 #define krom0 0x400 /* SRAM/ROM read/write */
197
198/******************************************************************************
199 * Power Management
200 ******************************************************************************/
201#define POWERMAN_DCR_BASE 0xb8
202#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
203#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
204#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
205
206/******************************************************************************
207 * Extrnal Bus Controller
208 ******************************************************************************/
209#define EBC_DCR_BASE 0x12
210#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
211#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
212 /* values for ebccfga register - indirect addressing of these regs */
213 #define pb0cr 0x00 /* periph bank 0 config reg */
214 #define pb1cr 0x01 /* periph bank 1 config reg */
215 #define pb2cr 0x02 /* periph bank 2 config reg */
216 #define pb3cr 0x03 /* periph bank 3 config reg */
217 #define pb4cr 0x04 /* periph bank 4 config reg */
218 #define pb5cr 0x05 /* periph bank 5 config reg */
219 #define pb6cr 0x06 /* periph bank 6 config reg */
220 #define pb7cr 0x07 /* periph bank 7 config reg */
221 #define pb0ap 0x10 /* periph bank 0 access parameters */
222 #define pb1ap 0x11 /* periph bank 1 access parameters */
223 #define pb2ap 0x12 /* periph bank 2 access parameters */
224 #define pb3ap 0x13 /* periph bank 3 access parameters */
225 #define pb4ap 0x14 /* periph bank 4 access parameters */
226 #define pb5ap 0x15 /* periph bank 5 access parameters */
227 #define pb6ap 0x16 /* periph bank 6 access parameters */
228 #define pb7ap 0x17 /* periph bank 7 access parameters */
229 #define pbear 0x20 /* periph bus error addr reg */
230 #define pbesr0 0x21 /* periph bus error status reg 0 */
231 #define pbesr1 0x22 /* periph bus error status reg 1 */
232 #define epcr 0x23 /* external periph control reg */
233
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]234#ifdef CONFIG_405EP
235/******************************************************************************
236 * Control
237 ******************************************************************************/
238#define CNTRL_DCR_BASE 0x0f0
239#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
240#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
241#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
242#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
243#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
244#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
245
246#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
247#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
248#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
249#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
250#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
251#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
252#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
253#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
254#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
255#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
256
257/* Bit definitions */
258#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
259#define PLLMR0_CPU_DIV_BYPASS 0x00000000
260#define PLLMR0_CPU_DIV_2 0x00100000
261#define PLLMR0_CPU_DIV_3 0x00200000
262#define PLLMR0_CPU_DIV_4 0x00300000
263
264#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
265#define PLLMR0_CPU_PLB_DIV_1 0x00000000
266#define PLLMR0_CPU_PLB_DIV_2 0x00010000
267#define PLLMR0_CPU_PLB_DIV_3 0x00020000
268#define PLLMR0_CPU_PLB_DIV_4 0x00030000
269
270#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
271#define PLLMR0_OPB_PLB_DIV_1 0x00000000
272#define PLLMR0_OPB_PLB_DIV_2 0x00001000
273#define PLLMR0_OPB_PLB_DIV_3 0x00002000
274#define PLLMR0_OPB_PLB_DIV_4 0x00003000
275
276#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
277#define PLLMR0_EXB_PLB_DIV_2 0x00000000
278#define PLLMR0_EXB_PLB_DIV_3 0x00000100
279#define PLLMR0_EXB_PLB_DIV_4 0x00000200
280#define PLLMR0_EXB_PLB_DIV_5 0x00000300
281
282#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
283#define PLLMR0_MAL_PLB_DIV_1 0x00000000
284#define PLLMR0_MAL_PLB_DIV_2 0x00000010
285#define PLLMR0_MAL_PLB_DIV_3 0x00000020
286#define PLLMR0_MAL_PLB_DIV_4 0x00000030
287
288#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
289#define PLLMR0_PCI_PLB_DIV_1 0x00000000
290#define PLLMR0_PCI_PLB_DIV_2 0x00000001
291#define PLLMR0_PCI_PLB_DIV_3 0x00000002
292#define PLLMR0_PCI_PLB_DIV_4 0x00000003
293
294#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
295#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
296#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
297#define PLLMR1_FBMUL_DIV_16 0x00000000
298#define PLLMR1_FBMUL_DIV_1 0x00100000
299#define PLLMR1_FBMUL_DIV_2 0x00200000
300#define PLLMR1_FBMUL_DIV_3 0x00300000
301#define PLLMR1_FBMUL_DIV_4 0x00400000
302#define PLLMR1_FBMUL_DIV_5 0x00500000
303#define PLLMR1_FBMUL_DIV_6 0x00600000
304#define PLLMR1_FBMUL_DIV_7 0x00700000
305#define PLLMR1_FBMUL_DIV_8 0x00800000
306#define PLLMR1_FBMUL_DIV_9 0x00900000
307#define PLLMR1_FBMUL_DIV_10 0x00A00000
308#define PLLMR1_FBMUL_DIV_11 0x00B00000
309#define PLLMR1_FBMUL_DIV_12 0x00C00000
310#define PLLMR1_FBMUL_DIV_13 0x00D00000
311#define PLLMR1_FBMUL_DIV_14 0x00E00000
312#define PLLMR1_FBMUL_DIV_15 0x00F00000
313
314#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
315#define PLLMR1_FWDVA_DIV_8 0x00000000
316#define PLLMR1_FWDVA_DIV_7 0x00010000
317#define PLLMR1_FWDVA_DIV_6 0x00020000
318#define PLLMR1_FWDVA_DIV_5 0x00030000
319#define PLLMR1_FWDVA_DIV_4 0x00040000
320#define PLLMR1_FWDVA_DIV_3 0x00050000
321#define PLLMR1_FWDVA_DIV_2 0x00060000
322#define PLLMR1_FWDVA_DIV_1 0x00070000
323#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
324#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
325
326/* Defines for CPC0_EPRCSR register */
327#define CPC0_EPRCSR_E0NFE 0x80000000
328#define CPC0_EPRCSR_E1NFE 0x40000000
329#define CPC0_EPRCSR_E1RPP 0x00000080
330#define CPC0_EPRCSR_E0RPP 0x00000040
331#define CPC0_EPRCSR_E1ERP 0x00000020
332#define CPC0_EPRCSR_E0ERP 0x00000010
333#define CPC0_EPRCSR_E1PCI 0x00000002
334#define CPC0_EPRCSR_E0PCI 0x00000001
335
336/* Defines for CPC0_PCI Register */
337#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
338#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
339#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
340
341/* Defines for CPC0_BOOR Register */
342#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
343
344/* Defines for CPC0_PLLMR1 Register fields */
345#define PLL_ACTIVE 0x80000000
346#define CPC0_PLLMR1_SSCS 0x80000000
347#define PLL_RESET 0x40000000
348#define CPC0_PLLMR1_PLLR 0x40000000
349 /* Feedback multiplier */
350#define PLL_FBKDIV 0x00F00000
351#define CPC0_PLLMR1_FBDV 0x00F00000
352#define PLL_FBKDIV_16 0x00000000
353#define PLL_FBKDIV_1 0x00100000
354#define PLL_FBKDIV_2 0x00200000
355#define PLL_FBKDIV_3 0x00300000
356#define PLL_FBKDIV_4 0x00400000
357#define PLL_FBKDIV_5 0x00500000
358#define PLL_FBKDIV_6 0x00600000
359#define PLL_FBKDIV_7 0x00700000
360#define PLL_FBKDIV_8 0x00800000
361#define PLL_FBKDIV_9 0x00900000
362#define PLL_FBKDIV_10 0x00A00000
363#define PLL_FBKDIV_11 0x00B00000
364#define PLL_FBKDIV_12 0x00C00000
365#define PLL_FBKDIV_13 0x00D00000
366#define PLL_FBKDIV_14 0x00E00000
367#define PLL_FBKDIV_15 0x00F00000
368 /* Forward A divisor */
369#define PLL_FWDDIVA 0x00070000
370#define CPC0_PLLMR1_FWDVA 0x00070000
371#define PLL_FWDDIVA_8 0x00000000
372#define PLL_FWDDIVA_7 0x00010000
373#define PLL_FWDDIVA_6 0x00020000
374#define PLL_FWDDIVA_5 0x00030000
375#define PLL_FWDDIVA_4 0x00040000
376#define PLL_FWDDIVA_3 0x00050000
377#define PLL_FWDDIVA_2 0x00060000
378#define PLL_FWDDIVA_1 0x00070000
379 /* Forward B divisor */
380#define PLL_FWDDIVB 0x00007000
381#define CPC0_PLLMR1_FWDVB 0x00007000
382#define PLL_FWDDIVB_8 0x00000000
383#define PLL_FWDDIVB_7 0x00001000
384#define PLL_FWDDIVB_6 0x00002000
385#define PLL_FWDDIVB_5 0x00003000
386#define PLL_FWDDIVB_4 0x00004000
387#define PLL_FWDDIVB_3 0x00005000
388#define PLL_FWDDIVB_2 0x00006000
389#define PLL_FWDDIVB_1 0x00007000
390 /* PLL tune bits */
391#define PLL_TUNE_MASK 0x000003FF
392#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
393#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
394#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
395#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
396#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
397#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
398#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
399
400/* Defines for CPC0_PLLMR0 Register fields */
401 /* CPU divisor */
402#define PLL_CPUDIV 0x00300000
403#define CPC0_PLLMR0_CCDV 0x00300000
404#define PLL_CPUDIV_1 0x00000000
405#define PLL_CPUDIV_2 0x00100000
406#define PLL_CPUDIV_3 0x00200000
407#define PLL_CPUDIV_4 0x00300000
408 /* PLB divisor */
409#define PLL_PLBDIV 0x00030000
410#define CPC0_PLLMR0_CBDV 0x00030000
411#define PLL_PLBDIV_1 0x00000000
412#define PLL_PLBDIV_2 0x00010000
413#define PLL_PLBDIV_3 0x00020000
414#define PLL_PLBDIV_4 0x00030000
415 /* OPB divisor */
416#define PLL_OPBDIV 0x00003000
417#define CPC0_PLLMR0_OPDV 0x00003000
418#define PLL_OPBDIV_1 0x00000000
419#define PLL_OPBDIV_2 0x00001000
420#define PLL_OPBDIV_3 0x00002000
421#define PLL_OPBDIV_4 0x00003000
422 /* EBC divisor */
423#define PLL_EXTBUSDIV 0x00000300
424#define CPC0_PLLMR0_EPDV 0x00000300
425#define PLL_EXTBUSDIV_2 0x00000000
426#define PLL_EXTBUSDIV_3 0x00000100
427#define PLL_EXTBUSDIV_4 0x00000200
428#define PLL_EXTBUSDIV_5 0x00000300
429 /* MAL divisor */
430#define PLL_MALDIV 0x00000030
431#define CPC0_PLLMR0_MPDV 0x00000030
432#define PLL_MALDIV_1 0x00000000
433#define PLL_MALDIV_2 0x00000010
434#define PLL_MALDIV_3 0x00000020
435#define PLL_MALDIV_4 0x00000030
436 /* PCI divisor */
437#define PLL_PCIDIV 0x00000003
438#define CPC0_PLLMR0_PPFD 0x00000003
439#define PLL_PCIDIV_1 0x00000000
440#define PLL_PCIDIV_2 0x00000001
441#define PLL_PCIDIV_3 0x00000002
442#define PLL_PCIDIV_4 0x00000003
443
444/*
445 *-------------------------------------------------------------------------------
446 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
447 * assuming a 33.3MHz input clock to the 405EP.
448 *-------------------------------------------------------------------------------
449 */
450#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]451 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
452 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]453#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]454 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
455 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]456
457#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]458 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
459 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]460#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]461 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
462 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]463#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]464 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
465 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]466#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]467 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
468 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]469#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]470 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
471 PLL_MALDIV_1 | PLL_PCIDIV_4)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]472#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]473 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
474 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]475
476/*
477 * PLL Voltage Controlled Oscillator (VCO) definitions
478 * Maximum and minimum values (in MHz) for correct PLL operation.
479 */
480#define VCO_MIN 500
481#define VCO_MAX 1000
482#else /* #ifdef CONFIG_405EP */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]483/******************************************************************************
484 * Control
485 ******************************************************************************/
486#define CNTRL_DCR_BASE 0x0b0
487#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
488#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
489#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
490#define reset (CNTRL_DCR_BASE+0x3) /* reset register */
491#define strap (CNTRL_DCR_BASE+0x4) /* strap register */
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]492
493#define ecr (0xaa) /* edge conditioner register (405gpr) */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]494
495/* Bit definitions */
496#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
497#define PLLMR_FWD_DIV_BYPASS 0xE0000000
498#define PLLMR_FWD_DIV_3 0xA0000000
499#define PLLMR_FWD_DIV_4 0x80000000
500#define PLLMR_FWD_DIV_6 0x40000000
501
502#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
503#define PLLMR_FB_DIV_1 0x02000000
504#define PLLMR_FB_DIV_2 0x04000000
505#define PLLMR_FB_DIV_3 0x06000000
506#define PLLMR_FB_DIV_4 0x08000000
507
508#define PLLMR_TUNING_MASK 0x01F80000
509
510#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
511#define PLLMR_CPU_PLB_DIV_1 0x00000000
512#define PLLMR_CPU_PLB_DIV_2 0x00020000
513#define PLLMR_CPU_PLB_DIV_3 0x00040000
514#define PLLMR_CPU_PLB_DIV_4 0x00060000
515
516#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
517#define PLLMR_OPB_PLB_DIV_1 0x00000000
518#define PLLMR_OPB_PLB_DIV_2 0x00008000
519#define PLLMR_OPB_PLB_DIV_3 0x00010000
520#define PLLMR_OPB_PLB_DIV_4 0x00018000
521
522#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
523#define PLLMR_PCI_PLB_DIV_1 0x00000000
524#define PLLMR_PCI_PLB_DIV_2 0x00002000
525#define PLLMR_PCI_PLB_DIV_3 0x00004000
526#define PLLMR_PCI_PLB_DIV_4 0x00006000
527
528#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
529#define PLLMR_EXB_PLB_DIV_2 0x00000000
530#define PLLMR_EXB_PLB_DIV_3 0x00000800
531#define PLLMR_EXB_PLB_DIV_4 0x00001000
532#define PLLMR_EXB_PLB_DIV_5 0x00001800
533
534/* definitions for PPC405GPr (new mode strapping) */
535#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
536
537#define PSR_PLL_FWD_MASK 0xC0000000
538#define PSR_PLL_FDBACK_MASK 0x30000000
539#define PSR_PLL_TUNING_MASK 0x0E000000
540#define PSR_PLB_CPU_MASK 0x01800000
541#define PSR_OPB_PLB_MASK 0x00600000
542#define PSR_PCI_PLB_MASK 0x00180000
543#define PSR_EB_PLB_MASK 0x00060000
544#define PSR_ROM_WIDTH_MASK 0x00018000
545#define PSR_ROM_LOC 0x00004000
546#define PSR_PCI_ASYNC_EN 0x00001000
547#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
548#define PSR_PCI_ARBIT_EN 0x00000400
549#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
550
551/*
552 * PLL Voltage Controlled Oscillator (VCO) definitions
553 * Maximum and minimum values (in MHz) for correct PLL operation.
554 */
555#define VCO_MIN 400
556#define VCO_MAX 800
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]557#endif /* #ifdef CONFIG_405EP */
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]558
559/******************************************************************************
560 * Memory Access Layer
561 ******************************************************************************/
562#define MAL_DCR_BASE 0x180
563#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
564#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
565#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
566#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
567#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
568#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
569#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
570#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
571#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
572#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
573#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
574#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
575#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
576#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
577#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
578#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
579
580/*-----------------------------------------------------------------------------
581| IIC Register Offsets
582'----------------------------------------------------------------------------*/
583#define IICMDBUF 0x00
584#define IICSDBUF 0x02
585#define IICLMADR 0x04
586#define IICHMADR 0x05
587#define IICCNTL 0x06
588#define IICMDCNTL 0x07
589#define IICSTS 0x08
590#define IICEXTSTS 0x09
591#define IICLSADR 0x0A
592#define IICHSADR 0x0B
593#define IICCLKDIV 0x0C
594#define IICINTRMSK 0x0D
595#define IICXFRCNT 0x0E
596#define IICXTCNTLSS 0x0F
597#define IICDIRECTCNTL 0x10
598
599/*-----------------------------------------------------------------------------
600| UART Register Offsets
601'----------------------------------------------------------------------------*/
602#define DATA_REG 0x00
603#define DL_LSB 0x00
604#define DL_MSB 0x01
605#define INT_ENABLE 0x01
606#define FIFO_CONTROL 0x02
607#define LINE_CONTROL 0x03
608#define MODEM_CONTROL 0x04
609#define LINE_STATUS 0x05
610#define MODEM_STATUS 0x06
611#define SCRATCH 0x07
612
613/******************************************************************************
614 * On Chip Memory
615 ******************************************************************************/
616#define OCM_DCR_BASE 0x018
617#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
618#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
619#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
620#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
621
stroeseb867d702003-05-23 11:18:02 +0000[diff] [blame]622/******************************************************************************
623 * GPIO macro register defines
624 ******************************************************************************/
625#define GPIO_BASE 0xEF600700
626#define GPIO0_OR (GPIO_BASE+0x0)
627#define GPIO0_TCR (GPIO_BASE+0x4)
628#define GPIO0_OSRH (GPIO_BASE+0x8)
629#define GPIO0_OSRL (GPIO_BASE+0xC)
630#define GPIO0_TSRH (GPIO_BASE+0x10)
631#define GPIO0_TSRL (GPIO_BASE+0x14)
632#define GPIO0_ODR (GPIO_BASE+0x18)
633#define GPIO0_IR (GPIO_BASE+0x1C)
634#define GPIO0_RR1 (GPIO_BASE+0x20)
635#define GPIO0_RR2 (GPIO_BASE+0x24)
636#define GPIO0_ISR1H (GPIO_BASE+0x30)
637#define GPIO0_ISR1L (GPIO_BASE+0x34)
638#define GPIO0_ISR2H (GPIO_BASE+0x38)
639#define GPIO0_ISR2L (GPIO_BASE+0x3C)
640
wdenk0442ed82002-11-03 10:24:00 +0000[diff] [blame]641
642/*
643 * Macro for accessing the indirect EBC register
644 */
645#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
646#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
647
648
649#ifndef __ASSEMBLY__
650
651typedef struct
652{
653 unsigned long pllFwdDiv;
654 unsigned long pllFwdDivB;
655 unsigned long pllFbkDiv;
656 unsigned long pllPlbDiv;
657 unsigned long pllPciDiv;
658 unsigned long pllExtBusDiv;
659 unsigned long pllOpbDiv;
660 unsigned long freqVCOMhz; /* in MHz */
661 unsigned long freqProcessor;
662 unsigned long freqPLB;
663 unsigned long freqPCI;
664 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
665 unsigned long pciClkSync; /* PCI clock is synchronous */
666} PPC405_SYS_INFO;
667
668#endif /* _ASMLANGUAGE */
669
670#define RESET_VECTOR 0xfffffffc
671#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
672 line aligned data. */
673
674#endif /* __PPC405_H__ */