blob: b7c4a603095219c009bc289d99e32868d02bf44e [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00007 */
8
wdenk0ac6f8b2004-07-09 23:27:13 +00009/*
10 * mpc8560ads board configuration file
11 *
12 * Please refer to doc/README.mpc85xx for more info.
13 *
14 * Make sure you change the MAC address and other network params first,
15 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000022#define CONFIG_BOOKE 1 /* BOOKE */
23#define CONFIG_E500 1 /* BOOKE e500 family */
24#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050025#define CONFIG_CPM2 1 /* has CPM2 */
wdenk0ac6f8b2004-07-09 23:27:13 +000026#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
Kumar Galaf0600542008-06-11 00:44:10 -050027#define CONFIG_MPC8560 1
wdenk42d1f032003-10-15 23:53:47 +000028
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029/*
30 * default CCARBAR is at 0xff700000
31 * assume U-Boot is less than 0.5MB
32 */
33#define CONFIG_SYS_TEXT_BASE 0xfff80000
34
wdenk0ac6f8b2004-07-09 23:27:13 +000035#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000036#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050037#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020038#define CONFIG_TSEC_ENET /* tsec ethernet support */
Andy Flemingccc091a2007-05-08 17:27:43 -050039#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000040#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060041#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Peter Tyser004eca02009-09-16 22:03:08 -050042#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk42d1f032003-10-15 23:53:47 +000043
wdenk0ac6f8b2004-07-09 23:27:13 +000044/*
45 * sysclk for MPC85xx
46 *
47 * Two valid values are:
48 * 33000000
49 * 66000000
50 *
51 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000052 * is likely the desired value here, so that is now the default.
53 * The board, however, can run at 66MHz. In any event, this value
54 * must match the settings of some switches. Details can be found
55 * in the README.mpc85xxads.
wdenk0ac6f8b2004-07-09 23:27:13 +000056 */
57
wdenk9aea9532004-08-01 23:02:45 +000058#ifndef CONFIG_SYS_CLK_FREQ
59#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000060#endif
61
wdenk9aea9532004-08-01 23:02:45 +000062
wdenk0ac6f8b2004-07-09 23:27:13 +000063/*
64 * These can be toggled for performance analysis, otherwise use default.
65 */
66#define CONFIG_L2_CACHE /* toggle L2 cache */
67#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000068
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk42d1f032003-10-15 23:53:47 +000070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
72#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000073
Timur Tabie46fedf2011-08-04 18:03:41 -050074#define CONFIG_SYS_CCSRBAR 0xe0000000
75#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000076
Jon Loeliger8b625112008-03-18 11:12:44 -050077/* DDR Setup */
78#define CONFIG_FSL_DDR1
79#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
80#define CONFIG_DDR_SPD
81#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000082
Jon Loeliger8b625112008-03-18 11:12:44 -050083#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
84
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
86#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +000087
Jon Loeliger8b625112008-03-18 11:12:44 -050088#define CONFIG_NUM_DDR_CONTROLLERS 1
89#define CONFIG_DIMM_SLOTS_PER_CTLR 1
90#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +000091
Jon Loeliger8b625112008-03-18 11:12:44 -050092/* I2C addresses of SPD EEPROMs */
93#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +000094
Jon Loeliger8b625112008-03-18 11:12:44 -050095/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
97#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
98#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
99#define CONFIG_SYS_DDR_TIMING_1 0x37344321
100#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
101#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
102#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
103#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000104
wdenk0ac6f8b2004-07-09 23:27:13 +0000105/*
106 * SDRAM on the Local Bus
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
109#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
112#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
115#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
116#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
117#undef CONFIG_SYS_FLASH_CHECKSUM
118#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
119#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000120
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200121#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
124#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000125#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000127#endif
128
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200129#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_CFI
131#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk0ac6f8b2004-07-09 23:27:13 +0000132
133#undef CONFIG_CLOCKS_IN_MHZ
wdenk42d1f032003-10-15 23:53:47 +0000134
wdenk42d1f032003-10-15 23:53:47 +0000135
wdenk0ac6f8b2004-07-09 23:27:13 +0000136/*
137 * Local Bus Definitions
138 */
139
140/*
141 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000143 *
144 * For BR2, need:
145 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
146 * port-size = 32-bits = BR2[19:20] = 11
147 * no parity checking = BR2[21:22] = 00
148 * SDRAM for MSEL = BR2[24:26] = 011
149 * Valid = BR[31] = 1
150 *
151 * 0 4 8 12 16 20 24 28
152 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
153 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000155 * FIXME: the top 17 bits of BR2.
156 */
157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000159
160/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000162 *
163 * For OR2, need:
164 * 64MB mask for AM, OR2[0:7] = 1111 1100
165 * XAM, OR2[17:18] = 11
166 * 9 columns OR2[19-21] = 010
167 * 13 rows OR2[23-25] = 100
168 * EAD set for extra time OR[31] = 1
169 *
170 * 0 4 8 12 16 20 24 28
171 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
172 */
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
177#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
178#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
179#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000180
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500181#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
182 | LSDMR_RFCR5 \
183 | LSDMR_PRETOACT3 \
184 | LSDMR_ACTTORW3 \
185 | LSDMR_BL8 \
186 | LSDMR_WRC2 \
187 | LSDMR_CL3 \
188 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000189 )
190
191/*
192 * SDRAM Controller configuration sequence.
193 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500194#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
195#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
196#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
197#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
198#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000199
wdenk42d1f032003-10-15 23:53:47 +0000200
wdenk9aea9532004-08-01 23:02:45 +0000201/*
202 * 32KB, 8-bit wide for ADS config reg
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_BR4_PRELIM 0xf8000801
205#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
206#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_INIT_RAM_LOCK 1
209#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200210#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000211
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200212#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
216#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000217
218/* Serial Port */
wdenk0ac6f8b2004-07-09 23:27:13 +0000219#define CONFIG_CONS_ON_SCC /* define if console on SCC */
220#undef CONFIG_CONS_NONE /* define if console on something else */
221#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
wdenk42d1f032003-10-15 23:53:47 +0000222
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200223#define CONFIG_BAUDRATE 115200
wdenk42d1f032003-10-15 23:53:47 +0000224
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000226 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
227
228/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_HUSH_PARSER
230#ifdef CONFIG_SYS_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000231#endif
232
Matthew McClintock0e163872006-06-28 10:43:36 -0500233/* pass open firmware flat tree */
Kumar Gala5ce71582007-11-28 22:40:31 -0600234#define CONFIG_OF_LIBFDT 1
235#define CONFIG_OF_BOARD_SETUP 1
236#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500237
Jon Loeliger20476722006-10-20 15:50:15 -0500238/*
239 * I2C
240 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200241#define CONFIG_SYS_I2C
242#define CONFIG_SYS_I2C_FSL
243#define CONFIG_SYS_FSL_I2C_SPEED 400000
244#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
245#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
246#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk42d1f032003-10-15 23:53:47 +0000247
wdenk0ac6f8b2004-07-09 23:27:13 +0000248/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600249#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600250#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600251#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk42d1f032003-10-15 23:53:47 +0000253
wdenk0ac6f8b2004-07-09 23:27:13 +0000254/*
255 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300256 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000257 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600258#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600259#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600260#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600262#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600263#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
265#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000266
267#if defined(CONFIG_PCI)
268
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200269#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000270
271#undef CONFIG_EEPRO100
wdenk42d1f032003-10-15 23:53:47 +0000272#undef CONFIG_TULIP
wdenk0ac6f8b2004-07-09 23:27:13 +0000273
274#if !defined(CONFIG_PCI_PNP)
275 #define PCI_ENET0_IOADDR 0xe0000000
276 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200277 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000278#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000279
280#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000282
283#endif /* CONFIG_PCI */
284
285
Andy Flemingccc091a2007-05-08 17:27:43 -0500286#ifdef CONFIG_TSEC_ENET
wdenk0ac6f8b2004-07-09 23:27:13 +0000287
Andy Flemingccc091a2007-05-08 17:27:43 -0500288#ifndef CONFIG_MII
wdenk0ac6f8b2004-07-09 23:27:13 +0000289#define CONFIG_MII 1 /* MII PHY management */
Andy Flemingccc091a2007-05-08 17:27:43 -0500290#endif
Kim Phillips255a35772007-05-16 16:52:19 -0500291#define CONFIG_TSEC1 1
292#define CONFIG_TSEC1_NAME "TSEC0"
293#define CONFIG_TSEC2 1
294#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000295#define TSEC1_PHY_ADDR 0
296#define TSEC2_PHY_ADDR 1
297#define TSEC1_PHYIDX 0
298#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500299#define TSEC1_FLAGS TSEC_GIGABIT
300#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500301
302/* Options are: TSEC[0-1] */
303#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000304
Andy Flemingccc091a2007-05-08 17:27:43 -0500305#endif /* CONFIG_TSEC_ENET */
wdenk0ac6f8b2004-07-09 23:27:13 +0000306
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200307#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
Andy Flemingccc091a2007-05-08 17:27:43 -0500308
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200309#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk0ac6f8b2004-07-09 23:27:13 +0000310#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
311
312#if (CONFIG_ETHER_INDEX == 2)
wdenk42d1f032003-10-15 23:53:47 +0000313 /*
314 * - Rx-CLK is CLK13
315 * - Tx-CLK is CLK14
316 * - Select bus for bd/buffers
317 * - Full duplex
318 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000319 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
320 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
322 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk42d1f032003-10-15 23:53:47 +0000323 #define FETH2_RST 0x01
wdenk0ac6f8b2004-07-09 23:27:13 +0000324#elif (CONFIG_ETHER_INDEX == 3)
wdenk42d1f032003-10-15 23:53:47 +0000325 /* need more definitions here for FE3 */
326 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200327#endif /* CONFIG_ETHER_INDEX */
wdenk0ac6f8b2004-07-09 23:27:13 +0000328
Andy Flemingccc091a2007-05-08 17:27:43 -0500329#ifndef CONFIG_MII
330#define CONFIG_MII 1 /* MII PHY management */
331#endif
332
wdenk0ac6f8b2004-07-09 23:27:13 +0000333#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
334
wdenk42d1f032003-10-15 23:53:47 +0000335/*
336 * GPIO pins used for bit-banged MII communications
337 */
338#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200339#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
340 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
341#define MDC_DECLARE MDIO_DECLARE
342
wdenk42d1f032003-10-15 23:53:47 +0000343#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
344#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
345#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
346
347#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
348 else iop->pdat &= ~0x00400000
349
350#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
351 else iop->pdat &= ~0x00200000
352
353#define MIIDELAY udelay(1)
wdenk0ac6f8b2004-07-09 23:27:13 +0000354
wdenk42d1f032003-10-15 23:53:47 +0000355#endif
356
wdenk0ac6f8b2004-07-09 23:27:13 +0000357
358/*
359 * Environment
360 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200362 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200364 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
365 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000366#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200368 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200370 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000371#endif
372
wdenk0ac6f8b2004-07-09 23:27:13 +0000373#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000375
Jon Loeliger2835e512007-06-13 13:22:08 -0500376/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500377 * BOOTP options
378 */
379#define CONFIG_BOOTP_BOOTFILESIZE
380#define CONFIG_BOOTP_BOOTPATH
381#define CONFIG_BOOTP_GATEWAY
382#define CONFIG_BOOTP_HOSTNAME
383
384
385/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500386 * Command line configuration.
387 */
388#include <config_cmd_default.h>
389
390#define CONFIG_CMD_PING
391#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600392#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500393#define CONFIG_CMD_IRQ
394#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500395#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500396
397#if defined(CONFIG_PCI)
398 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000399#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000400
Jon Loeliger2835e512007-06-13 13:22:08 -0500401#if defined(CONFIG_ETHER_ON_FCC)
402 #define CONFIG_CMD_MII
403#endif
404
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500406 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500407 #undef CONFIG_CMD_LOADS
408#endif
409
wdenk42d1f032003-10-15 23:53:47 +0000410
wdenk0ac6f8b2004-07-09 23:27:13 +0000411#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000412
413/*
414 * Miscellaneous configurable options
415 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500417#define CONFIG_CMDLINE_EDITING /* Command-line editing */
418#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000420
Jon Loeliger2835e512007-06-13 13:22:08 -0500421#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000423#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000425#endif
426
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
428#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
429#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000430
431/*
432 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500433 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000434 * the maximum mapped by the Linux kernel during initialization.
435 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500436#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
437#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000438
Jon Loeliger2835e512007-06-13 13:22:08 -0500439#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000440#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
441#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
442#endif
443
wdenk9aea9532004-08-01 23:02:45 +0000444
445/*
446 * Environment Configuration
447 */
448
wdenk0ac6f8b2004-07-09 23:27:13 +0000449/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000450#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500451#define CONFIG_HAS_ETH0
wdenk0ac6f8b2004-07-09 23:27:13 +0000452#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000453#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000454#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000455#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000456#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
Kumar Gala5ce71582007-11-28 22:40:31 -0600457#define CONFIG_HAS_ETH3
458#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
wdenk42d1f032003-10-15 23:53:47 +0000459#endif
460
wdenk0ac6f8b2004-07-09 23:27:13 +0000461#define CONFIG_IPADDR 192.168.1.253
462
463#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000464#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000465#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000466
467#define CONFIG_SERVERIP 192.168.1.1
468#define CONFIG_GATEWAYIP 192.168.1.1
469#define CONFIG_NETMASK 255.255.255.0
470
471#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
472
wdenk9aea9532004-08-01 23:02:45 +0000473#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
wdenk0ac6f8b2004-07-09 23:27:13 +0000474#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
475
476#define CONFIG_BAUDRATE 115200
477
wdenk9aea9532004-08-01 23:02:45 +0000478#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming6b44a442008-07-14 20:04:40 -0500479 "netdev=eth0\0" \
480 "consoledev=ttyCPM\0" \
481 "ramdiskaddr=1000000\0" \
482 "ramdiskfile=your.ramdisk.u-boot\0" \
483 "fdtaddr=400000\0" \
484 "fdtfile=mpc8560ads.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000485
wdenk9aea9532004-08-01 23:02:45 +0000486#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500487 "setenv bootargs root=/dev/nfs rw " \
488 "nfsroot=$serverip:$rootpath " \
489 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
490 "console=$consoledev,$baudrate $othbootargs;" \
491 "tftp $loadaddr $bootfile;" \
492 "tftp $fdtaddr $fdtfile;" \
493 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000494
495#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500496 "setenv bootargs root=/dev/ram rw " \
497 "console=$consoledev,$baudrate $othbootargs;" \
498 "tftp $ramdiskaddr $ramdiskfile;" \
499 "tftp $loadaddr $bootfile;" \
500 "tftp $fdtaddr $fdtfile;" \
501 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000502
503#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000504
505#endif /* __CONFIG_H */