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esw@bus-elektronik.de4324c752012-01-16 00:22:02 +00001/*
2 * (C) Copyright 2009-2012
3 * Jens Scharsig <esw@bus-elekronik.de>
4 * BuS Elektronik GmbH & Co. KG
5 *
6 * Configuation settings for the VL_MA2SC board.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
esw@bus-elektronik.de4324c752012-01-16 00:22:02 +00009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*--------------------------------------------------------------------------*/
15
esw@bus-elektronik.de4324c752012-01-16 00:22:02 +000016#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */
17#define CONFIG_AT91FAMILY
18#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
19#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
20#define CONFIG_ARCH_CPU_INIT
21#define CONFIG_MISC_INIT_R
22
23#include <asm/hardware.h>
24
25#define MACH_TYPE_VL_MA2SC 2412
26#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
27
28#define CONFIG_SYS_DCACHE_OFF
29
30#ifdef CONFIG_RAMLOAD
31#define CONFIG_SYS_TEXT_BASE 0x21000000
32#else
33#define CONFIG_SYS_TEXT_BASE 0x00000000
34#endif
35#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
36
37#define CONFIG_IDENT_STRING " on MiS Activ 2"
38#define CONFIG_VERSION_VARIABLE
39#define CONFIG_AT91_GPIO
40
41#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
42#define CONFIG_SYS_USE_NORFLASH
43#define CONFIG_SYS_USE_BOOT_NORFLASH
44#endif
45
46#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
47#define CONFIG_SETUP_MEMORY_TAGS
48#define CONFIG_INITRD_TAG
49
50#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
51#define CONFIG_SKIP_LOWLEVEL_INIT
52#endif
53
54/*
55 * Hardware drivers
56 */
57
58#define CONFIG_BOARD_EARLY_INIT_F
59
60#define CONFIG_WATCHDOG
61
62#define CONFIG_ATMEL_USART
63#define CONFIG_USART_BASE ATMEL_BASE_DBGU
64#define CONFIG_USART_ID ATMEL_ID_SYS
65
66/* LCD */
67#define CONFIG_LCD
68#define CONFIG_ATMEL_LCD
69#define CONFIG_SPLASH_SCREEN
70#define CONFIG_SYS_BLACK_ON_WHITE
71#define LCD_BPP LCD_COLOR8
72#define CONFIG_ATMEL_LCD_BGR555
73
74#define CONFIG_SYS_CONSOLE_IS_IN_ENV
75#define CONFIG_BOOTDELAY 3
76
77/*
78 * BOOTP options
79 */
80#define CONFIG_BOOTP_BOOTFILESIZE
81#define CONFIG_BOOTP_BOOTPATH
82#define CONFIG_BOOTP_GATEWAY
83#define CONFIG_BOOTP_HOSTNAME
84
85/*
86 * Command line configuration.
87 */
88#include <config_cmd_default.h>
89#undef CONFIG_CMD_BDI
90#undef CONFIG_CMD_FPGA
91#undef CONFIG_CMD_IMI
92#undef CONFIG_CMD_LOADS
93
94#define CONFIG_CMD_BMP
95#define CONFIG_CMD_DATE
96#define CONFIG_CMD_DHCP
97#define CONFIG_CMD_I2C
98#define CONFIG_CMD_NAND
99#define CONFIG_CMD_MII
100#define CONFIG_CMD_PING
101#define CONFIG_CMD_MD5SUM
102#define CONFIG_CMD_SHA1SUM
103/*
104#define CONFIG_CMD_SPI
105*/
106#define CONFIG_CMD_FAT
107#define CONFIG_CMD_USB
108
109#define CONFIG_SYS_LONGHELP
110#define CONFIG_MD5
111#define CONFIG_SHA1
112
113/*----------------------------------------------------------------------------
114 * Hardware confuguration
115 *---------------------------------------------------------------------------*/
116
117/* USB */
118#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800119#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
esw@bus-elektronik.de4324c752012-01-16 00:22:02 +0000120#define CONFIG_USB_OHCI_NEW
121#define CONFIG_DOS_PARTITION
122#define CONFIG_SYS_USB_OHCI_CPU_INIT
123#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
124#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
125#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
126#define CONFIG_USB_STORAGE
127#define CONFIG_AT91C_PQFP_UHPBUG
128
129/* I2C-Bus */
130
131#define CONFIG_SYS_I2C_SPEED 50000
132#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
133
134#ifndef CONFIG_HARD_I2C
Heiko Schocherea818db2013-01-29 08:53:15 +0100135#define CONFIG_SYS_I2C
136#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
137#define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
138#define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
esw@bus-elektronik.de4324c752012-01-16 00:22:02 +0000139
140/* Software I2C driver configuration */
esw@bus-elektronik.de4324c752012-01-16 00:22:02 +0000141#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
142
143#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
144#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
145
146#define I2C_INIT i2c_init_board();
147#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
148#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
149#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
150#define I2C_SDA(bit) \
151 do { \
152 if (bit) \
153 writel(AT91_PIN_SDA, &pio->piob.sodr); \
154 else \
155 writel(AT91_PIN_SDA, &pio->piob.codr); \
156 } while (0);
157#define I2C_SCL(bit) \
158 do { \
159 if (bit) \
160 writel(AT91_PIN_SCL, &pio->piob.sodr); \
161 else \
162 writel(AT91_PIN_SCL, &pio->piob.codr); \
163 } while (0);
164#endif
165
166/* I2C-RTC */
167
168#ifdef CONFIG_CMD_DATE
169#define CONFIG_RTC_DS1338
170#define CONFIG_SYS_I2C_RTC_ADDR 0x68
171#endif
172
173/* EEPROM */
174
175#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
176#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
177
178/* define PDC[31:16] as DATA[31:16] */
179#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
180#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
181
182/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
183#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
184 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
185 AT91_MATRIX_CSA_EBI_CS1A)
186
187/* user reset enable */
188#define CONFIG_SYS_RSTC_RMR_VAL \
189 (AT91_RSTC_KEY | \
190 AT91_RSTC_MR_URSTEN | \
191 AT91_RSTC_MR_ERSTL(15))
192
193/* Disable Watchdog */
194#define CONFIG_SYS_WDTC_WDMR_VAL \
195 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
196 AT91_WDT_MR_WDV(0xFFF) | \
197 AT91_WDT_MR_WDDIS | \
198 AT91_WDT_MR_WDD(0xFFF))
199
200/* clocks */
201
esw@bus-elektronik.de4324c752012-01-16 00:22:02 +0000202#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
203
204#define MHZ180
205#if defined(MHZ199)
206/* 199,8994 MHZ */
207#define MASTER_PLL_MUL 911
208#define MASTER_PLL_DIV 56
209#define MASTER_PLL_OUT 2
210#elif defined(MHZ180)
211/* 180 MHZ */
212#define MASTER_PLL_MUL 1875
213#define MASTER_PLL_DIV 128
214#define MASTER_PLL_OUT 2
215#elif defined(MHZTEST)
216/* Test MHZ */
217#define CONFIG_DISPLAY_CPUINFO
218#define MASTER_PLL_MUL 8
219#define MASTER_PLL_DIV 1
220#define MASTER_PLL_OUT 2
221#else
222/* 176.9472 MHZ */
223#define MASTER_PLL_MUL 72
224#define MASTER_PLL_DIV 5
225#define MASTER_PLL_OUT 2
226#endif
227
228#define CONFIG_SYS_MOR_VAL \
229 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
230
231#define CONFIG_SYS_PLLAR_VAL \
232 (AT91_PMC_PLLAR_29 | \
233 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
234 AT91_PMC_PLLXR_PLLCOUNT(63) | \
235 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
236 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
237
238/* PCK/2 = MCK Master Clock from PLLA */
239#define CONFIG_SYS_MCKR1_VAL \
240 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
241 AT91_PMC_MCKR_MDIV_2)
242
243/* PCK/2 = MCK Master Clock from PLLA */
244#define CONFIG_SYS_MCKR2_VAL \
245 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
246 AT91_PMC_MCKR_MDIV_2)
247
248/* SDRAM */
249#define CONFIG_NR_DRAM_BANKS 1
250#define CONFIG_SYS_SDRAM_BASE 0x20000000
251#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
252#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
253
254#define CONFIG_SYS_SDRC_MR_VAL1 0
255#define CONFIG_SYS_SDRC_TR_VAL1 700
256#define CONFIG_SYS_SDRC_CR_VAL \
257 (AT91_SDRAMC_NC_9 | \
258 AT91_SDRAMC_NR_13 | \
259 AT91_SDRAMC_NB_4 | \
260 AT91_SDRAMC_CAS_3 | \
261 AT91_SDRAMC_DBW_32 | \
262 (2 << 8) | /* Write Recovery Delay */ \
263 (7 << 12) | /* Row Cycle Delay */ \
264 (2 << 16) | /* Row Precharge Delay */ \
265 (2 << 20) | /* Row to Column Delay */ \
266 (5 << 24) | /* Active to Precharge Delay */ \
267 (8 << 28)) /* Exit Self Refresh to Active Delay */
268
269#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
270#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
271#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
272#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
273#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
274#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
275#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
276#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
277#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
278#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
279#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
280#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
281#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
282#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
283#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
284#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
285#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
286#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
287
288/* NOR flash */
289
290#define CONFIG_FLASH_SHOW_PROGRESS 45
291#define CONFIG_SYS_FLASH_CFI
292#define CONFIG_FLASH_CFI_DRIVER
293#define PHYS_FLASH_1 0x10000000
294#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
295#define CONFIG_SYS_MAX_FLASH_SECT 256
296#define CONFIG_SYS_MAX_FLASH_BANKS 1
297
298#define CONFIG_ENV_IS_IN_FLASH
299#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
300
301/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
302#define CONFIG_SYS_SMC0_SETUP0_VAL \
303 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
304 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
305#define CONFIG_SYS_SMC0_PULSE0_VAL \
306 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
307 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
308#define CONFIG_SYS_SMC0_CYCLE0_VAL \
309 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
310#define CONFIG_SYS_SMC0_MODE0_VAL \
311 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
312 AT91_SMC_MODE_DBW_16 | \
313 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
314
315/* NAND flash */
316#ifdef CONFIG_CMD_NAND
317#define CONFIG_NAND_ATMEL
318#define CONFIG_SYS_MAX_NAND_DEVICE 1
319#define CONFIG_SYS_NAND_BASE 0x40000000
320#define CONFIG_SYS_NAND_DBW_8 1
321#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
322#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
323#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
324#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0
325#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
326#endif
327
328/* Ethernet */
329#define CONFIG_MACB
330#define CONFIG_RMII
331#define CONFIG_NET_MULTI
332#define CONFIG_NET_RETRY_COUNT 5
333
334#define CONFIG_OVERWRITE_ETHADDR_ONCE
335
336#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
337
338#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
339#define CONFIG_SYS_MEMTEST_END 0x21e00000
340
341/* Address and size of Primary Environment Sector */
342#ifdef CONFIG_ENV_IS_IN_FLASH
343#define CONFIG_ENV_SIZE 0x20000
344#else
345#define CONFIG_ENV_SIZE 0x2000
346#endif
347
348#define CONFIG_BAUDRATE 115200
349#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
350 38400, 57600, 9600 }
351
352#define CONFIG_SYS_PROMPT "U-Boot> "
353#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
354#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
355#define CONFIG_SYS_PBSIZE \
356 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
357#define CONFIG_CMDLINE_EDITING
358#define CONFIG_AUTO_COMPLETE
359
360/*
361 * Size of malloc() pool
362 */
363#define CONFIG_SYS_MALLOC_LEN \
364 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
365#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
366
esw@bus-elektronik.de4324c752012-01-16 00:22:02 +0000367#ifndef CONFIG_RAMLOAD
368#define CONFIG_BOOTCOMMAND "run nfsboot"
369#endif
370#define CONFIG_BOOT_RETRY_TIME -1
371#define CONFIG_BOOT_RETRY_MIN 15
372
373#define CONFIG_NFSBOOTCOMMAND \
374 "dhcp $(copy_addr) $(kernelname);" \
375 "run bootargsdefaults;" \
376 "set bootargs $(bootargs) boot=nfs " \
377 ";echo $(bootargs)" \
378 ";bootm"
379
380#define CONFIG_EXTRA_ENV_SETTINGS \
381 "ubootaddr=10000000\0" \
382 "splashimage=10080000\0" \
383 "kerneladdr=100A0000\0" \
384 "kernelsize=00800000\0" \
385 "minifsaddr=108A0000\0" \
386 "minifssize=00060000\0" \
387 "rootfsaddr=10900000\0" \
388 "copy_addr=20200000\0" \
389 "rootfssize=01700000\0" \
390 "kernelname=uImage_vl_ma2sc\0" \
391 "bootargsdefaults=set bootargs " \
392 "console=ttyS0,115200 " \
393 "video=atmel_lcdfb " \
394 "mem=62M " \
395 "panic=10 " \
396 "boardrevison=\\\"${revision}\\\" " \
397 "uboot=\\\"${ver}\\\" " \
398 "\0" \
399 "update_all=run update_kernel;run update_root;" \
400 "run update_splash; run update_uboot\0" \
401 "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
402 "dhcp $(copy_addr) $(kernelname);" \
403 "erase $(kerneladdr) +$(kernelsize);" \
404 "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
405 "protect on $(kerneladdr) +$(kernelsize)" \
406 "\0" \
407 "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
408 "dhcp $(copy_addr) vl_ma2sc.root;" \
409 "erase $(rootfsaddr) +$(rootfssize);" \
410 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
411 "\0" \
412 "update_splash=protect off $(splashimage) +20000;" \
413 "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
414 "erase $(splashimage) +20000;" \
415 "cp.b $(fileaddr) 10080000 $(filesize);" \
416 "protect on $(splashimage) +20000\0" \
417 "update_uboot=protect off 10000000 1005FFFF;" \
418 "dhcp $(copy_addr) u-boot_vl_ma2sc;" \
419 "erase 10000000 1005FFFF;" \
420 "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
421 "protect on 10000000 1005FFFF;reset\0" \
422 "emergency=run bootargsdefaults;" \
423 "set bootargs $(bootargs) root=initramfs boot=emergency " \
424 ";bootm $(kerneladdr)\0" \
425 "netemergency=run bootargsdefaults;" \
426 "dhcp $(copy_addr) $(kernelname);" \
427 "set bootargs $(bootargs) root=initramfs boot=emergency " \
428 ";bootm $(copy_addr)\0" \
429 "norboot=run bootargsdefaults;" \
430 "set bootargs $(bootargs) root=initramfs boot=local quiet " \
431 ";bootm $(kerneladdr)\0" \
432 "nandboot=run bootargsdefaults;" \
433 "set bootargs $(bootargs) root=initramfs boot=nand " \
434 ";bootm $(kerneladdr)\0" \
435 "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
436 "clearenv=protect off 10060000 1007FFFF;" \
437 "erase 10060000 1007FFFF;reset\0" \
438 " "
439
esw@bus-elektronik.de4324c752012-01-16 00:22:02 +0000440#endif