blob: 6e5d50700c07d359f0452cf462fd502b34ff21ac [file] [log] [blame]
Mario Six0e0674f2019-01-21 09:17:30 +01001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * Copyright (C) 2007 Logic Product Development, Inc.
7 * Peter Barada <peterb@logicpd.com>
8 *
9 * Copyright (C) 2007 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * (C) Copyright 2010
13 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
14 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/*
20 * High Level Configuration Options
21 */
22
Mario Six0e0674f2019-01-21 09:17:30 +010023#define CONFIG_HOSTNAME "kmvect1"
24#define CONFIG_KM_BOARD_NAME "kmvect1"
25/* at end of uboot partition, before env */
26#define CONFIG_SYS_QE_FW_ADDR 0xF00B0000
Mario Six0e890d42019-01-21 09:17:32 +010027
Mario Sixfb1b0992019-01-21 09:17:34 +010028/* include common defines/options for all Keymile boards */
29#include "km/keymile-common.h"
30#include "km/km-powerpc.h"
Mario Sixaed7d0e2019-01-21 09:18:23 +010031#include "km/km-mpc83xx.h"
32#include "km/km-mpc8309.h"
Mario Six0e0674f2019-01-21 09:17:30 +010033
34#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
35 0x0000c000 | \
36 MxMR_WLFx_2X)
Mario Six0e0674f2019-01-21 09:17:30 +010037/*
Mario Six0e0674f2019-01-21 09:17:30 +010038 * QE UEC ethernet configuration
39 */
40#define CONFIG_MV88E6352_SWITCH
41#define CONFIG_KM_MVEXTSW_ADDR 0x10
42
43/* ethernet port connected to simple switch 88e6122 (UEC0) */
44#define CONFIG_UEC_ETH1
45#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
46#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
47#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
48
49#define CONFIG_FIXED_PHY 0xFFFFFFFF
50#define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */
51#define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
52 {devnum, speed, duplex}
53#define CONFIG_SYS_FIXED_PHY_PORTS \
54 CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL)
55
56#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
57#define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
58#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
59#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
60
Mario Six0e0674f2019-01-21 09:17:30 +010061#endif /* __CONFIG_H */