blob: 75ac993bc6450c341bab0eecdf611b4eada3845d [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05302/**
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +05305 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05306 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +053010 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/ep0.c) and ported
11 * to uboot.
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053012 *
Kishon Vijay Abraham I30c31d52015-02-23 18:39:52 +053013 * commit c00552ebaf : Merge 3.18-rc7 into usb-next
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053014 */
Jean-Jacques Hiblot4d3825c2018-11-29 10:52:50 +010015#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070016#include <cpu_func.h>
Sean Andersondf5eabc2020-09-15 10:45:16 -040017#include <dm.h>
Simon Glass336d4612020-02-03 07:36:16 -070018#include <dm/device_compat.h>
Simon Glasseb41d8a2020-05-10 11:40:08 -060019#include <linux/bug.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053020#include <linux/kernel.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053021#include <linux/list.h>
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053022
23#include <linux/usb/ch9.h>
24#include <linux/usb/gadget.h>
25#include <linux/usb/composite.h>
26
27#include "core.h"
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053028#include "gadget.h"
29#include "io.h"
30
Kishon Vijay Abraham Ib6d959a2015-02-23 18:40:00 +053031#include "linux-compat.h"
32
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053033static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
34static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
35 struct dwc3_ep *dep, struct dwc3_request *req);
36
37static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
38{
39 switch (state) {
40 case EP0_UNCONNECTED:
41 return "Unconnected";
42 case EP0_SETUP_PHASE:
43 return "Setup Phase";
44 case EP0_DATA_PHASE:
45 return "Data Phase";
46 case EP0_STATUS_PHASE:
47 return "Status Phase";
48 default:
49 return "UNKNOWN";
50 }
51}
52
53static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +053054 u32 len, u32 type, unsigned chain)
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053055{
56 struct dwc3_gadget_ep_cmd_params params;
57 struct dwc3_trb *trb;
58 struct dwc3_ep *dep;
59
60 int ret;
61
62 dep = dwc->eps[epnum];
63 if (dep->flags & DWC3_EP_BUSY) {
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +053064 dev_vdbg(dwc->dev, "%s still busy", dep->name);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053065 return 0;
66 }
67
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +053068 trb = &dwc->ep0_trb[dep->free_slot];
69
70 if (chain)
71 dep->free_slot++;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053072
73 trb->bpl = lower_32_bits(buf_dma);
74 trb->bph = upper_32_bits(buf_dma);
75 trb->size = len;
76 trb->ctrl = type;
77
78 trb->ctrl |= (DWC3_TRB_CTRL_HWO
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053079 | DWC3_TRB_CTRL_ISP_IMI);
80
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +053081 if (chain)
82 trb->ctrl |= DWC3_TRB_CTRL_CHN;
83 else
84 trb->ctrl |= (DWC3_TRB_CTRL_IOC
85 | DWC3_TRB_CTRL_LST);
86
Philipp Tomsichb7bf4a92017-04-06 16:58:52 +020087 dwc3_flush_cache((uintptr_t)buf_dma, len);
88 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
Kishon Vijay Abraham I526a50f2015-02-23 18:40:13 +053089
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +053090 if (chain)
91 return 0;
92
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053093 memset(&params, 0, sizeof(params));
94 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
95 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
96
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +053097 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
98 DWC3_DEPCMD_STARTTRANSFER, &params);
99 if (ret < 0) {
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530100 dev_dbg(dwc->dev, "%s STARTTRANSFER failed", dep->name);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530101 return ret;
102 }
103
104 dep->flags |= DWC3_EP_BUSY;
105 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
106 dep->number);
107
108 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
109
110 return 0;
111}
112
113static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
114 struct dwc3_request *req)
115{
116 struct dwc3 *dwc = dep->dwc;
117
118 req->request.actual = 0;
119 req->request.status = -EINPROGRESS;
120 req->epnum = dep->number;
121
122 list_add_tail(&req->list, &dep->request_list);
123
124 /*
125 * Gadget driver might not be quick enough to queue a request
126 * before we get a Transfer Not Ready event on this endpoint.
127 *
128 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
129 * flag is set, it's telling us that as soon as Gadget queues the
130 * required request, we should kick the transfer here because the
131 * IRQ we were waiting for is long gone.
132 */
133 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
134 unsigned direction;
135
136 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
137
138 if (dwc->ep0state != EP0_DATA_PHASE) {
139 dev_WARN(dwc->dev, "Unexpected pending request\n");
140 return 0;
141 }
142
143 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
144
145 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
146 DWC3_EP0_DIR_IN);
147
148 return 0;
149 }
150
151 /*
152 * In case gadget driver asked us to delay the STATUS phase,
153 * handle it here.
154 */
155 if (dwc->delayed_status) {
156 unsigned direction;
157
158 direction = !dwc->ep0_expect_in;
159 dwc->delayed_status = false;
160 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
161
162 if (dwc->ep0state == EP0_STATUS_PHASE)
163 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
164 else
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530165 dev_dbg(dwc->dev, "too early for delayed status");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530166
167 return 0;
168 }
169
170 /*
171 * Unfortunately we have uncovered a limitation wrt the Data Phase.
172 *
173 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
174 * come before issueing Start Transfer command, but if we do, we will
175 * miss situations where the host starts another SETUP phase instead of
176 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
177 * Layer Compliance Suite.
178 *
179 * The problem surfaces due to the fact that in case of back-to-back
180 * SETUP packets there will be no XferNotReady(DATA) generated and we
181 * will be stuck waiting for XferNotReady(DATA) forever.
182 *
183 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
184 * it tells us to start Data Phase right away. It also mentions that if
185 * we receive a SETUP phase instead of the DATA phase, core will issue
186 * XferComplete for the DATA phase, before actually initiating it in
187 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
188 * can only be used to print some debugging logs, as the core expects
189 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
190 * just so it completes right away, without transferring anything and,
191 * only then, we can go back to the SETUP phase.
192 *
193 * Because of this scenario, SNPS decided to change the programming
194 * model of control transfers and support on-demand transfers only for
195 * the STATUS phase. To fix the issue we have now, we will always wait
196 * for gadget driver to queue the DATA phase's struct usb_request, then
197 * start it right away.
198 *
199 * If we're actually in a 2-stage transfer, we will wait for
200 * XferNotReady(STATUS).
201 */
202 if (dwc->three_stage_setup) {
203 unsigned direction;
204
205 direction = dwc->ep0_expect_in;
206 dwc->ep0state = EP0_DATA_PHASE;
207
208 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
209
210 dep->flags &= ~DWC3_EP0_DIR_IN;
211 }
212
213 return 0;
214}
215
216int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
217 gfp_t gfp_flags)
218{
219 struct dwc3_request *req = to_dwc3_request(request);
220 struct dwc3_ep *dep = to_dwc3_ep(ep);
221 struct dwc3 *dwc = dep->dwc;
222
223 unsigned long flags;
224
225 int ret;
226
227 spin_lock_irqsave(&dwc->lock, flags);
228 if (!dep->endpoint.desc) {
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530229 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s",
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530230 request, dep->name);
231 ret = -ESHUTDOWN;
232 goto out;
233 }
234
235 /* we share one TRB for ep0/1 */
236 if (!list_empty(&dep->request_list)) {
237 ret = -EBUSY;
238 goto out;
239 }
240
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530241 dev_vdbg(dwc->dev, "queueing request %p to %s length %d state '%s'",
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530242 request, dep->name, request->length,
243 dwc3_ep0_state_string(dwc->ep0state));
244
245 ret = __dwc3_gadget_ep0_queue(dep, req);
246
247out:
248 spin_unlock_irqrestore(&dwc->lock, flags);
249
250 return ret;
251}
252
253static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
254{
255 struct dwc3_ep *dep;
256
257 /* reinitialize physical ep1 */
258 dep = dwc->eps[1];
259 dep->flags = DWC3_EP_ENABLED;
260
261 /* stall is always issued on EP0 */
262 dep = dwc->eps[0];
263 __dwc3_gadget_ep_set_halt(dep, 1, false);
264 dep->flags = DWC3_EP_ENABLED;
265 dwc->delayed_status = false;
266
267 if (!list_empty(&dep->request_list)) {
268 struct dwc3_request *req;
269
270 req = next_request(&dep->request_list);
271 dwc3_gadget_giveback(dep, req, -ECONNRESET);
272 }
273
274 dwc->ep0state = EP0_SETUP_PHASE;
275 dwc3_ep0_out_start(dwc);
276}
277
278int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
279{
280 struct dwc3_ep *dep = to_dwc3_ep(ep);
281 struct dwc3 *dwc = dep->dwc;
282
283 dwc3_ep0_stall_and_restart(dwc);
284
285 return 0;
286}
287
288int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
289{
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530290 unsigned long flags;
291 int ret;
292
293 spin_lock_irqsave(&dwc->lock, flags);
294 ret = __dwc3_gadget_ep0_set_halt(ep, value);
295 spin_unlock_irqrestore(&dwc->lock, flags);
296
297 return ret;
298}
299
300void dwc3_ep0_out_start(struct dwc3 *dwc)
301{
302 int ret;
303
304 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +0530305 DWC3_TRBCTL_CONTROL_SETUP, 0);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530306 WARN_ON(ret < 0);
307}
308
309static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
310{
311 struct dwc3_ep *dep;
312 u32 windex = le16_to_cpu(wIndex_le);
313 u32 epnum;
314
315 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
316 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
317 epnum |= 1;
318
319 dep = dwc->eps[epnum];
320 if (dep->flags & DWC3_EP_ENABLED)
321 return dep;
322
323 return NULL;
324}
325
326static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
327{
328}
329/*
330 * ch 9.4.5
331 */
332static int dwc3_ep0_handle_status(struct dwc3 *dwc,
333 struct usb_ctrlrequest *ctrl)
334{
335 struct dwc3_ep *dep;
336 u32 recip;
337 u32 reg;
338 u16 usb_status = 0;
339 __le16 *response_pkt;
340
341 recip = ctrl->bRequestType & USB_RECIP_MASK;
342 switch (recip) {
343 case USB_RECIP_DEVICE:
344 /*
345 * LTM will be set once we know how to set this in HW.
346 */
347 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
348
349 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
350 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
351 if (reg & DWC3_DCTL_INITU1ENA)
352 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
353 if (reg & DWC3_DCTL_INITU2ENA)
354 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
355 }
356
357 break;
358
359 case USB_RECIP_INTERFACE:
360 /*
361 * Function Remote Wake Capable D0
362 * Function Remote Wakeup D1
363 */
364 break;
365
366 case USB_RECIP_ENDPOINT:
367 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
368 if (!dep)
369 return -EINVAL;
370
371 if (dep->flags & DWC3_EP_STALL)
372 usb_status = 1 << USB_ENDPOINT_HALT;
373 break;
374 default:
375 return -EINVAL;
376 }
377
378 response_pkt = (__le16 *) dwc->setup_buf;
379 *response_pkt = cpu_to_le16(usb_status);
380
381 dep = dwc->eps[0];
382 dwc->ep0_usb_req.dep = dep;
383 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
384 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
385 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
386
387 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
388}
389
390static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
391 struct usb_ctrlrequest *ctrl, int set)
392{
393 struct dwc3_ep *dep;
394 u32 recip;
395 u32 wValue;
396 u32 wIndex;
397 u32 reg;
398 int ret;
399 enum usb_device_state state;
400
401 wValue = le16_to_cpu(ctrl->wValue);
402 wIndex = le16_to_cpu(ctrl->wIndex);
403 recip = ctrl->bRequestType & USB_RECIP_MASK;
404 state = dwc->gadget.state;
405
406 switch (recip) {
407 case USB_RECIP_DEVICE:
408
409 switch (wValue) {
410 case USB_DEVICE_REMOTE_WAKEUP:
411 break;
412 /*
413 * 9.4.1 says only only for SS, in AddressState only for
414 * default control pipe
415 */
416 case USB_DEVICE_U1_ENABLE:
417 if (state != USB_STATE_CONFIGURED)
418 return -EINVAL;
419 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
420 return -EINVAL;
421
422 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
423 if (set)
424 reg |= DWC3_DCTL_INITU1ENA;
425 else
426 reg &= ~DWC3_DCTL_INITU1ENA;
427 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
428 break;
429
430 case USB_DEVICE_U2_ENABLE:
431 if (state != USB_STATE_CONFIGURED)
432 return -EINVAL;
433 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
434 return -EINVAL;
435
436 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
437 if (set)
438 reg |= DWC3_DCTL_INITU2ENA;
439 else
440 reg &= ~DWC3_DCTL_INITU2ENA;
441 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
442 break;
443
444 case USB_DEVICE_LTM_ENABLE:
445 return -EINVAL;
446
447 case USB_DEVICE_TEST_MODE:
448 if ((wIndex & 0xff) != 0)
449 return -EINVAL;
450 if (!set)
451 return -EINVAL;
452
453 dwc->test_mode_nr = wIndex >> 8;
454 dwc->test_mode = true;
455 break;
456 default:
457 return -EINVAL;
458 }
459 break;
460
461 case USB_RECIP_INTERFACE:
462 switch (wValue) {
463 case USB_INTRF_FUNC_SUSPEND:
464 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
465 /* XXX enable Low power suspend */
466 ;
467 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
468 /* XXX enable remote wakeup */
469 ;
470 break;
471 default:
472 return -EINVAL;
473 }
474 break;
475
476 case USB_RECIP_ENDPOINT:
477 switch (wValue) {
478 case USB_ENDPOINT_HALT:
479 dep = dwc3_wIndex_to_dep(dwc, wIndex);
480 if (!dep)
481 return -EINVAL;
482 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
483 break;
484 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
485 if (ret)
486 return -EINVAL;
487 break;
488 default:
489 return -EINVAL;
490 }
491 break;
492
493 default:
494 return -EINVAL;
495 }
496
497 return 0;
498}
499
500static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
501{
502 enum usb_device_state state = dwc->gadget.state;
503 u32 addr;
504 u32 reg;
505
506 addr = le16_to_cpu(ctrl->wValue);
507 if (addr > 127) {
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530508 dev_dbg(dwc->dev, "invalid device address %d", addr);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530509 return -EINVAL;
510 }
511
512 if (state == USB_STATE_CONFIGURED) {
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530513 dev_dbg(dwc->dev, "trying to set address when configured");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530514 return -EINVAL;
515 }
516
517 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
518 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
519 reg |= DWC3_DCFG_DEVADDR(addr);
520 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
521
522 if (addr)
523 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
524 else
525 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
526
527 return 0;
528}
529
530static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
531{
532 int ret;
533
534 spin_unlock(&dwc->lock);
535 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
536 spin_lock(&dwc->lock);
537 return ret;
538}
539
540static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
541{
542 enum usb_device_state state = dwc->gadget.state;
543 u32 cfg;
544 int ret;
545 u32 reg;
546
547 dwc->start_config_issued = false;
548 cfg = le16_to_cpu(ctrl->wValue);
549
550 switch (state) {
551 case USB_STATE_DEFAULT:
552 return -EINVAL;
553
554 case USB_STATE_ADDRESS:
555 ret = dwc3_ep0_delegate_req(dwc, ctrl);
556 /* if the cfg matches and the cfg is non zero */
557 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
558
559 /*
560 * only change state if set_config has already
561 * been processed. If gadget driver returns
562 * USB_GADGET_DELAYED_STATUS, we will wait
563 * to change the state on the next usb_ep_queue()
564 */
565 if (ret == 0)
566 usb_gadget_set_state(&dwc->gadget,
567 USB_STATE_CONFIGURED);
568
569 /*
570 * Enable transition to U1/U2 state when
571 * nothing is pending from application.
572 */
573 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
574 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
575 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
576
577 dwc->resize_fifos = true;
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530578 dev_dbg(dwc->dev, "resize FIFOs flag SET");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530579 }
580 break;
581
582 case USB_STATE_CONFIGURED:
583 ret = dwc3_ep0_delegate_req(dwc, ctrl);
584 if (!cfg && !ret)
585 usb_gadget_set_state(&dwc->gadget,
586 USB_STATE_ADDRESS);
587 break;
588 default:
589 ret = -EINVAL;
590 }
591 return ret;
592}
593
594static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
595{
596 struct dwc3_ep *dep = to_dwc3_ep(ep);
597 struct dwc3 *dwc = dep->dwc;
598
599 u32 param = 0;
600 u32 reg;
601
602 struct timing {
603 u8 u1sel;
604 u8 u1pel;
605 u16 u2sel;
606 u16 u2pel;
607 } __packed timing;
608
609 int ret;
610
611 memcpy(&timing, req->buf, sizeof(timing));
612
613 dwc->u1sel = timing.u1sel;
614 dwc->u1pel = timing.u1pel;
615 dwc->u2sel = le16_to_cpu(timing.u2sel);
616 dwc->u2pel = le16_to_cpu(timing.u2pel);
617
618 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
619 if (reg & DWC3_DCTL_INITU2ENA)
620 param = dwc->u2pel;
621 if (reg & DWC3_DCTL_INITU1ENA)
622 param = dwc->u1pel;
623
624 /*
625 * According to Synopsys Databook, if parameter is
626 * greater than 125, a value of zero should be
627 * programmed in the register.
628 */
629 if (param > 125)
630 param = 0;
631
632 /* now that we have the time, issue DGCMD Set Sel */
633 ret = dwc3_send_gadget_generic_command(dwc,
634 DWC3_DGCMD_SET_PERIODIC_PAR, param);
635 WARN_ON(ret < 0);
636}
637
638static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
639{
640 struct dwc3_ep *dep;
641 enum usb_device_state state = dwc->gadget.state;
642 u16 wLength;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530643
644 if (state == USB_STATE_DEFAULT)
645 return -EINVAL;
646
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530647 wLength = le16_to_cpu(ctrl->wLength);
648
649 if (wLength != 6) {
650 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
651 wLength);
652 return -EINVAL;
653 }
654
655 /*
656 * To handle Set SEL we need to receive 6 bytes from Host. So let's
657 * queue a usb_request for 6 bytes.
658 *
659 * Remember, though, this controller can't handle non-wMaxPacketSize
660 * aligned transfers on the OUT direction, so we queue a request for
661 * wMaxPacketSize instead.
662 */
663 dep = dwc->eps[0];
664 dwc->ep0_usb_req.dep = dep;
665 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
666 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
667 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
668
669 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
670}
671
672static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
673{
674 u16 wLength;
675 u16 wValue;
676 u16 wIndex;
677
678 wValue = le16_to_cpu(ctrl->wValue);
679 wLength = le16_to_cpu(ctrl->wLength);
680 wIndex = le16_to_cpu(ctrl->wIndex);
681
682 if (wIndex || wLength)
683 return -EINVAL;
684
685 /*
686 * REVISIT It's unclear from Databook what to do with this
687 * value. For now, just cache it.
688 */
689 dwc->isoch_delay = wValue;
690
691 return 0;
692}
693
694static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
695{
696 int ret;
697
698 switch (ctrl->bRequest) {
699 case USB_REQ_GET_STATUS:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530700 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530701 ret = dwc3_ep0_handle_status(dwc, ctrl);
702 break;
703 case USB_REQ_CLEAR_FEATURE:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530704 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530705 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
706 break;
707 case USB_REQ_SET_FEATURE:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530708 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530709 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
710 break;
711 case USB_REQ_SET_ADDRESS:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530712 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530713 ret = dwc3_ep0_set_address(dwc, ctrl);
714 break;
715 case USB_REQ_SET_CONFIGURATION:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530716 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530717 ret = dwc3_ep0_set_config(dwc, ctrl);
718 break;
719 case USB_REQ_SET_SEL:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530720 dev_vdbg(dwc->dev, "USB_REQ_SET_SEL");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530721 ret = dwc3_ep0_set_sel(dwc, ctrl);
722 break;
723 case USB_REQ_SET_ISOCH_DELAY:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530724 dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530725 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
726 break;
727 default:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530728 dev_vdbg(dwc->dev, "Forwarding to gadget driver");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530729 ret = dwc3_ep0_delegate_req(dwc, ctrl);
730 break;
731 }
732
733 return ret;
734}
735
736static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
737 const struct dwc3_event_depevt *event)
738{
739 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
740 int ret = -EINVAL;
741 u32 len;
742
743 if (!dwc->gadget_driver)
744 goto out;
745
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530746 len = le16_to_cpu(ctrl->wLength);
747 if (!len) {
748 dwc->three_stage_setup = false;
749 dwc->ep0_expect_in = false;
750 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
751 } else {
752 dwc->three_stage_setup = true;
753 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
754 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
755 }
756
757 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
758 ret = dwc3_ep0_std_request(dwc, ctrl);
759 else
760 ret = dwc3_ep0_delegate_req(dwc, ctrl);
761
762 if (ret == USB_GADGET_DELAYED_STATUS)
763 dwc->delayed_status = true;
764
765out:
766 if (ret < 0)
767 dwc3_ep0_stall_and_restart(dwc);
768}
769
770static void dwc3_ep0_complete_data(struct dwc3 *dwc,
771 const struct dwc3_event_depevt *event)
772{
773 struct dwc3_request *r = NULL;
774 struct usb_request *ur;
775 struct dwc3_trb *trb;
776 struct dwc3_ep *ep0;
Kishon Vijay Abraham I1f78f8f2015-02-23 18:40:14 +0530777 unsigned transfer_size = 0;
778 unsigned maxp;
779 void *buf;
780 u32 transferred = 0;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530781 u32 status;
782 u32 length;
783 u8 epnum;
784
785 epnum = event->endpoint_number;
786 ep0 = dwc->eps[0];
787
788 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
789
790 trb = dwc->ep0_trb;
791
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530792 r = next_request(&ep0->request_list);
793 if (!r)
794 return;
795
Philipp Tomsichb7bf4a92017-04-06 16:58:52 +0200796 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
Kishon Vijay Abraham I526a50f2015-02-23 18:40:13 +0530797
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530798 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
799 if (status == DWC3_TRBSTS_SETUP_PENDING) {
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530800 dev_dbg(dwc->dev, "Setup Pending received");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530801
802 if (r)
803 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
804
805 return;
806 }
807
808 ur = &r->request;
Kishon Vijay Abraham I1f78f8f2015-02-23 18:40:14 +0530809 buf = ur->buf;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530810
811 length = trb->size & DWC3_TRB_SIZE_MASK;
812
Kishon Vijay Abraham I1f78f8f2015-02-23 18:40:14 +0530813 maxp = ep0->endpoint.maxpacket;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530814
Kishon Vijay Abraham I1f78f8f2015-02-23 18:40:14 +0530815 if (dwc->ep0_bounced) {
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +0530816 /*
817 * Handle the first TRB before handling the bounce buffer if
818 * the request length is greater than the bounce buffer size.
819 */
820 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
821 transfer_size = (ur->length / maxp) * maxp;
822 transferred = transfer_size - length;
823 buf = (u8 *)buf + transferred;
824 ur->actual += transferred;
825
826 trb++;
Philipp Tomsichb7bf4a92017-04-06 16:58:52 +0200827 dwc3_flush_cache((uintptr_t)trb, sizeof(*trb));
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +0530828 length = trb->size & DWC3_TRB_SIZE_MASK;
829
830 ep0->free_slot = 0;
831 }
832
Kishon Vijay Abraham I1f78f8f2015-02-23 18:40:14 +0530833 transfer_size = roundup((ur->length - transfer_size),
834 maxp);
835 transferred = min_t(u32, ur->length - transferred,
836 transfer_size - length);
Philipp Tomsichb7bf4a92017-04-06 16:58:52 +0200837 dwc3_flush_cache((uintptr_t)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
Kishon Vijay Abraham I1f78f8f2015-02-23 18:40:14 +0530838 memcpy(buf, dwc->ep0_bounce, transferred);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530839 } else {
840 transferred = ur->length - length;
841 }
842
843 ur->actual += transferred;
844
845 if ((epnum & 1) && ur->actual < ur->length) {
846 /* for some reason we did not get everything out */
847
848 dwc3_ep0_stall_and_restart(dwc);
849 } else {
850 dwc3_gadget_giveback(ep0, r, 0);
851
852 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
853 ur->length && ur->zero) {
854 int ret;
855
856 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
857
858 ret = dwc3_ep0_start_trans(dwc, epnum,
859 dwc->ctrl_req_addr, 0,
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +0530860 DWC3_TRBCTL_CONTROL_DATA, 0);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530861 WARN_ON(ret < 0);
862 }
863 }
864}
865
866static void dwc3_ep0_complete_status(struct dwc3 *dwc,
867 const struct dwc3_event_depevt *event)
868{
869 struct dwc3_request *r;
870 struct dwc3_ep *dep;
871 struct dwc3_trb *trb;
872 u32 status;
873
874 dep = dwc->eps[0];
875 trb = dwc->ep0_trb;
876
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530877 if (!list_empty(&dep->request_list)) {
878 r = next_request(&dep->request_list);
879
880 dwc3_gadget_giveback(dep, r, 0);
881 }
882
883 if (dwc->test_mode) {
884 int ret;
885
886 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
887 if (ret < 0) {
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530888 dev_dbg(dwc->dev, "Invalid Test #%d",
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530889 dwc->test_mode_nr);
890 dwc3_ep0_stall_and_restart(dwc);
891 return;
892 }
893 }
894
895 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
896 if (status == DWC3_TRBSTS_SETUP_PENDING)
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530897 dev_dbg(dwc->dev, "Setup Pending received");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530898
899 dwc->ep0state = EP0_SETUP_PHASE;
900 dwc3_ep0_out_start(dwc);
901}
902
903static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
904 const struct dwc3_event_depevt *event)
905{
906 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
907
908 dep->flags &= ~DWC3_EP_BUSY;
909 dep->resource_index = 0;
910 dwc->setup_packet_pending = false;
911
912 switch (dwc->ep0state) {
913 case EP0_SETUP_PHASE:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530914 dev_vdbg(dwc->dev, "Setup Phase");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530915 dwc3_ep0_inspect_setup(dwc, event);
916 break;
917
918 case EP0_DATA_PHASE:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530919 dev_vdbg(dwc->dev, "Data Phase");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530920 dwc3_ep0_complete_data(dwc, event);
921 break;
922
923 case EP0_STATUS_PHASE:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +0530924 dev_vdbg(dwc->dev, "Status Phase");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530925 dwc3_ep0_complete_status(dwc, event);
926 break;
927 default:
928 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
929 }
930}
931
932static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
933 struct dwc3_ep *dep, struct dwc3_request *req)
934{
935 int ret;
936
937 req->direction = !!dep->number;
938
939 if (req->request.length == 0) {
940 ret = dwc3_ep0_start_trans(dwc, dep->number,
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +0530941 dwc->ctrl_req_addr, 0,
942 DWC3_TRBCTL_CONTROL_DATA, 0);
943 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
944 (dep->number == 0)) {
945 u32 transfer_size = 0;
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530946 u32 maxpacket;
947
948 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
949 dep->number);
950 if (ret) {
951 dev_dbg(dwc->dev, "failed to map request\n");
952 return;
953 }
954
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530955 maxpacket = dep->endpoint.maxpacket;
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +0530956 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
957 transfer_size = (req->request.length / maxpacket) *
958 maxpacket;
959 ret = dwc3_ep0_start_trans(dwc, dep->number,
960 req->request.dma,
961 transfer_size,
962 DWC3_TRBCTL_CONTROL_DATA, 1);
963 }
964
965 transfer_size = roundup((req->request.length - transfer_size),
966 maxpacket);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530967
968 dwc->ep0_bounced = true;
969
970 /*
971 * REVISIT in case request length is bigger than
972 * DWC3_EP0_BOUNCE_SIZE we will need two chained
973 * TRBs to handle the transfer.
974 */
975 ret = dwc3_ep0_start_trans(dwc, dep->number,
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +0530976 dwc->ep0_bounce_addr, transfer_size,
977 DWC3_TRBCTL_CONTROL_DATA, 0);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530978 } else {
979 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
980 dep->number);
981 if (ret) {
982 dev_dbg(dwc->dev, "failed to map request\n");
983 return;
984 }
985
986 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +0530987 req->request.length,
988 DWC3_TRBCTL_CONTROL_DATA, 0);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +0530989 }
990
991 WARN_ON(ret < 0);
992}
993
994static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
995{
996 struct dwc3 *dwc = dep->dwc;
997 u32 type;
998
999 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1000 : DWC3_TRBCTL_CONTROL_STATUS2;
1001
1002 return dwc3_ep0_start_trans(dwc, dep->number,
Kishon Vijay Abraham I8d488f32015-02-23 18:40:15 +05301003 dwc->ctrl_req_addr, 0, type, 0);
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301004}
1005
1006static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1007{
1008 if (dwc->resize_fifos) {
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +05301009 dev_dbg(dwc->dev, "Resizing FIFOs");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301010 dwc3_gadget_resize_tx_fifos(dwc);
1011 dwc->resize_fifos = 0;
1012 }
1013
1014 WARN_ON(dwc3_ep0_start_control_status(dep));
1015}
1016
1017static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1018 const struct dwc3_event_depevt *event)
1019{
1020 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1021
1022 __dwc3_ep0_do_control_status(dwc, dep);
1023}
1024
1025static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1026{
1027 struct dwc3_gadget_ep_cmd_params params;
1028 u32 cmd;
1029 int ret;
1030
1031 if (!dep->resource_index)
1032 return;
1033
1034 cmd = DWC3_DEPCMD_ENDTRANSFER;
1035 cmd |= DWC3_DEPCMD_CMDIOC;
1036 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1037 memset(&params, 0, sizeof(params));
1038 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1039 WARN_ON_ONCE(ret);
1040 dep->resource_index = 0;
1041}
1042
1043static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1044 const struct dwc3_event_depevt *event)
1045{
1046 dwc->setup_packet_pending = true;
1047
1048 switch (event->status) {
1049 case DEPEVT_STATUS_CONTROL_DATA:
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +05301050 dev_vdbg(dwc->dev, "Control Data");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301051
1052 /*
1053 * We already have a DATA transfer in the controller's cache,
1054 * if we receive a XferNotReady(DATA) we will ignore it, unless
1055 * it's for the wrong direction.
1056 *
1057 * In that case, we must issue END_TRANSFER command to the Data
1058 * Phase we already have started and issue SetStall on the
1059 * control endpoint.
1060 */
1061 if (dwc->ep0_expect_in != event->endpoint_number) {
1062 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1063
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +05301064 dev_vdbg(dwc->dev, "Wrong direction for Data phase");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301065 dwc3_ep0_end_control_data(dwc, dep);
1066 dwc3_ep0_stall_and_restart(dwc);
1067 return;
1068 }
1069
1070 break;
1071
1072 case DEPEVT_STATUS_CONTROL_STATUS:
1073 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1074 return;
1075
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +05301076 dev_vdbg(dwc->dev, "Control Status");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301077
1078 dwc->ep0state = EP0_STATUS_PHASE;
1079
1080 if (dwc->delayed_status) {
1081 WARN_ON_ONCE(event->endpoint_number != 1);
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +05301082 dev_vdbg(dwc->dev, "Delayed Status");
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301083 return;
1084 }
1085
1086 dwc3_ep0_do_control_status(dwc, event);
1087 }
1088}
1089
1090void dwc3_ep0_interrupt(struct dwc3 *dwc,
1091 const struct dwc3_event_depevt *event)
1092{
1093 u8 epnum = event->endpoint_number;
1094
Kishon Vijay Abraham I9de11152015-02-23 18:39:53 +05301095 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'",
Kishon Vijay Abraham I85d5e702015-02-23 18:39:50 +05301096 dwc3_ep_event_string(event->endpoint_event),
1097 epnum >> 1, (epnum & 1) ? "in" : "out",
1098 dwc3_ep0_state_string(dwc->ep0state));
1099
1100 switch (event->endpoint_event) {
1101 case DWC3_DEPEVT_XFERCOMPLETE:
1102 dwc3_ep0_xfer_complete(dwc, event);
1103 break;
1104
1105 case DWC3_DEPEVT_XFERNOTREADY:
1106 dwc3_ep0_xfernotready(dwc, event);
1107 break;
1108
1109 case DWC3_DEPEVT_XFERINPROGRESS:
1110 case DWC3_DEPEVT_RXTXFIFOEVT:
1111 case DWC3_DEPEVT_STREAMEVT:
1112 case DWC3_DEPEVT_EPCMDCMPLT:
1113 break;
1114 }
1115}