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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0f060c3bf82832331a509f2e5d2442539e7aad09 / . / cpu / mpc85xx / release.S
blob: 7c3e8a1725aac6ebfb8611718bcd292e8331d43b [file] [log] [blame]
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]1#include <config.h>
2#include <mpc85xx.h>
3#include <version.h>
4
5#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
6
7#include <ppc_asm.tmpl>
8#include <ppc_defs.h>
9
10#include <asm/cache.h>
11#include <asm/mmu.h>
12
13/* To boot secondary cpus, we need a place for them to start up.
14 * Normally, they start at 0xfffffffc, but that's usually the
15 * firmware, and we don't want to have to run the firmware again.
16 * Instead, the primary cpu will set the BPTR to point here to
17 * this page. We then set up the core, and head to
18 * start_secondary. Note that this means that the code below
19 * must never exceed 1023 instructions (the branch at the end
20 * would then be the 1024th).
21 */
22 .globl __secondary_start_page
23 .align 12
24__secondary_start_page:
25/* First do some preliminary setup */
26 lis r3, HID0_EMCP@h /* enable machine check */
Kumar Gala0f060c32008-10-23 01:47:38 -0500[diff] [blame^]27#ifndef CONFIG_E500MC
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]28 ori r3,r3,HID0_TBEN@l /* enable Timebase */
Kumar Gala0f060c32008-10-23 01:47:38 -0500[diff] [blame^]29#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]30#ifdef CONFIG_PHYS_64BIT
31 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
32#endif
33 mtspr SPRN_HID0,r3
34
Kumar Gala0f060c32008-10-23 01:47:38 -0500[diff] [blame^]35#ifndef CONFIG_E500MC
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]36 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
37 mtspr SPRN_HID1,r3
Kumar Gala0f060c32008-10-23 01:47:38 -0500[diff] [blame^]38#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]39
40 /* Enable branch prediction */
41 li r3,0x201
42 mtspr SPRN_BUCSR,r3
43
Kumar Galae0ff3d32008-09-08 08:51:29 -0500[diff] [blame]44 /* Ensure TB is 0 */
45 li r3,0
46 mttbl r3
47 mttbu r3
48
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]49 /* Enable/invalidate the I-Cache */
50 mfspr r0,SPRN_L1CSR1
51 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
52 mtspr SPRN_L1CSR1,r0
53 isync
54
55 /* Enable/invalidate the D-Cache */
56 mfspr r0,SPRN_L1CSR0
57 ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
58 msync
59 isync
60 mtspr SPRN_L1CSR0,r0
61 isync
62
63#define toreset(x) (x - __secondary_start_page + 0xfffff000)
64
65 /* get our PIR to figure out our table entry */
66 lis r3,toreset(__spin_table)@h
67 ori r3,r3,toreset(__spin_table)@l
68
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]69 /* r10 has the base address for the entry */
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]70 mfspr r0,SPRN_PIR
Kumar Gala0f060c32008-10-23 01:47:38 -0500[diff] [blame^]71#ifdef CONFIG_E500MC
72 rlwinm r4,r0,27,27,31
73#else
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]74 mr r4,r0
Kumar Gala0f060c32008-10-23 01:47:38 -0500[diff] [blame^]75#endif
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]76 slwi r8,r4,5
77 add r10,r3,r8
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]78
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]79#define EPAPR_MAGIC (0x45504150)
80#define ENTRY_ADDR_UPPER 0
81#define ENTRY_ADDR_LOWER 4
82#define ENTRY_R3_UPPER 8
83#define ENTRY_R3_LOWER 12
84#define ENTRY_RESV 16
85#define ENTRY_PIR 20
86#define ENTRY_R6_UPPER 24
87#define ENTRY_R6_LOWER 28
88#define ENTRY_SIZE 32
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]89
90 /* setup the entry */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]91 li r3,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]92 li r8,1
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]93 stw r0,ENTRY_PIR(r10)
94 stw r3,ENTRY_ADDR_UPPER(r10)
95 stw r8,ENTRY_ADDR_LOWER(r10)
96 stw r3,ENTRY_R3_UPPER(r10)
97 stw r4,ENTRY_R3_LOWER(r10)
98 stw r3,ENTRY_R6_UPPER(r10)
99 stw r3,ENTRY_R6_LOWER(r10)
100
101 /* setup mapping for AS = 1, and jump there */
102 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
103 mtspr SPRN_MAS0,r11
104 lis r11,(MAS1_VALID|MAS1_IPROT)@h
105 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
106 mtspr SPRN_MAS1,r11
107 lis r11,(0xfffff000|MAS2_I)@h
108 ori r11,r11,(0xfffff000|MAS2_I)@l
109 mtspr SPRN_MAS2,r11
110 lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
111 ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
112 mtspr SPRN_MAS3,r11
113 tlbwe
114
115 bl 1f
1161: mflr r11
117 addi r11,r11,28
118 mfmsr r13
119 ori r12,r13,MSR_IS|MSR_DS@l
120
121 mtspr SPRN_SRR0,r11
122 mtspr SPRN_SRR1,r12
123 rfi
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]124
125 /* spin waiting for addr */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]1262:
127 lwz r4,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]128 andi. r11,r4,1
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]129 bne 2b
Kumar Galacf6cc012008-04-28 02:24:04 -0500[diff] [blame]130 isync
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]131
132 /* get the upper bits of the addr */
133 lwz r11,ENTRY_ADDR_UPPER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]134
135 /* setup branch addr */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]136 mtspr SPRN_SRR0,r4
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]137
138 /* mark the entry as released */
139 li r8,3
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]140 stw r8,ENTRY_ADDR_LOWER(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]141
142 /* mask by ~64M to setup our tlb we will jump to */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]143 rlwinm r12,r4,0,0,5
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]144
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]145 /* setup r3, r4, r5, r6, r7, r8, r9 */
146 lwz r3,ENTRY_R3_LOWER(r10)
147 li r4,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]148 li r5,0
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]149 lwz r6,ENTRY_R6_LOWER(r10)
150 lis r7,(64*1024*1024)@h
151 li r8,0
152 li r9,0
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]153
154 /* load up the pir */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]155 lwz r0,ENTRY_PIR(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]156 mtspr SPRN_PIR,r0
157 mfspr r0,SPRN_PIR
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]158 stw r0,ENTRY_PIR(r10)
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]159
160/*
161 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
162 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
163 * second mapping that maps addr 1:1 for 64M, and then we jump to
164 * addr
165 */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]166 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
167 mtspr SPRN_MAS0,r10
168 lis r10,(MAS1_VALID|MAS1_IPROT)@h
169 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
170 mtspr SPRN_MAS1,r10
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]171 /* WIMGE = 0b00000 for now */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]172 mtspr SPRN_MAS2,r12
173 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
174 mtspr SPRN_MAS3,r12
175#ifdef CONFIG_ENABLE_36BIT_PHYS
176 mtspr SPRN_MAS7,r11
177#endif
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]178 tlbwe
179
180/* Now we have another mapping for this page, so we jump to that
181 * mapping
182 */
Kumar Gala79679d82008-03-26 08:34:25 -0500[diff] [blame]183 mtspr SPRN_SRR1,r13
184 rfi
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]185
Kumar Galacf6cc012008-04-28 02:24:04 -0500[diff] [blame]186 .align L1_CACHE_SHIFT
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]187 .globl __spin_table
188__spin_table:
Kumar Gala902ca092008-08-11 11:29:28 -0500[diff] [blame]189 .space CONFIG_NUM_CPUS*ENTRY_SIZE
Kumar Galaec2b74f2008-01-17 16:48:33 -0600[diff] [blame]190
191 /* Fill in the empty space. The actual reset vector is
192 * the last word of the page */
193__secondary_start_code_end:
194 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
195__secondary_reset_vector:
196 b __secondary_start_page