blob: 059cb0fc6e549d6e088374667ca0f9f9a3e4dbdc [file] [log] [blame]
TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
TsiChungLiew2bd806f2007-07-05 23:17:36 -05002 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
TsiChung Liew8e585f02007-06-18 13:50:13 -05003 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
4 *
angelo@sysam.ite27802a2016-04-27 21:51:13 +02005 * Modified to add device model (DM) support
6 * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
TsiChung Liew8e585f02007-06-18 13:50:13 -05009 */
10
11/*
12 * Minimal serial functions needed to use one of the uart ports
13 * as serial console interface.
14 */
15
16#include <common.h>
angelo@sysam.ite27802a2016-04-27 21:51:13 +020017#include <dm.h>
18#include <dm/platform_data/serial_coldfire.h>
Alison Wang39c7a262012-10-18 16:54:38 +000019#include <serial.h>
20#include <linux/compiler.h>
TsiChungLiew2bd806f2007-07-05 23:17:36 -050021#include <asm/immap.h>
22#include <asm/uart.h>
TsiChung Liew8e585f02007-06-18 13:50:13 -050023
24DECLARE_GLOBAL_DATA_PTR;
25
TsiChung Liewfa9da592010-03-09 19:24:43 -060026extern void uart_port_conf(int port);
TsiChungLiew8d1d66a2007-08-05 03:55:21 -050027
angelo@sysam.ite27802a2016-04-27 21:51:13 +020028static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
TsiChung Liew8e585f02007-06-18 13:50:13 -050029{
TsiChung Liew8e585f02007-06-18 13:50:13 -050030 u32 counter;
31
angelo@sysam.ite27802a2016-04-27 21:51:13 +020032 uart_port_conf(port_idx);
TsiChungLiew8d1d66a2007-08-05 03:55:21 -050033
TsiChung Liew8e585f02007-06-18 13:50:13 -050034 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020035 writeb(UART_UCR_RESET_RX, &uart->ucr);
36 writeb(UART_UCR_RESET_TX, &uart->ucr);
37 writeb(UART_UCR_RESET_ERROR, &uart->ucr);
38 writeb(UART_UCR_RESET_MR, &uart->ucr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050039 __asm__("nop");
40
angelo@sysam.ite27802a2016-04-27 21:51:13 +020041 writeb(0, &uart->uimr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050042
43 /* write to CSR: RX/TX baud rate from timers */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020044 writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050045
angelo@sysam.ite27802a2016-04-27 21:51:13 +020046 writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
47 writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050048
49 /* Setting up BaudRate */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020050 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
51 counter = counter / baudrate;
TsiChung Liew8e585f02007-06-18 13:50:13 -050052
53 /* write to CTUR: divide counter upper byte */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020054 writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
TsiChung Liew8e585f02007-06-18 13:50:13 -050055 /* write to CTLR: divide counter lower byte */
angelo@sysam.ite27802a2016-04-27 21:51:13 +020056 writeb((u8)(counter & 0x00ff), &uart->ubg2);
TsiChung Liew8e585f02007-06-18 13:50:13 -050057
angelo@sysam.ite27802a2016-04-27 21:51:13 +020058 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
TsiChung Liew8e585f02007-06-18 13:50:13 -050059
60 return (0);
61}
62
angelo@sysam.ite27802a2016-04-27 21:51:13 +020063static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
64{
65 u32 counter;
66
67 /* Setting up BaudRate */
68 counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
69 counter = counter / baudrate;
70
71 /* write to CTUR: divide counter upper byte */
72 writeb(((counter & 0xff00) >> 8), &uart->ubg1);
73 /* write to CTLR: divide counter lower byte */
74 writeb((counter & 0x00ff), &uart->ubg2);
75
76 writeb(UART_UCR_RESET_RX, &uart->ucr);
77 writeb(UART_UCR_RESET_TX, &uart->ucr);
78
79 writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
80}
81
82#ifndef CONFIG_DM_SERIAL
83
84static int mcf_serial_init(void)
85{
86 uart_t *uart_base;
87 int port_idx;
88
89 uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
90 port_idx = CONFIG_SYS_UART_PORT;
91
92 return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
93}
94
Marek Vasutabaef692012-09-13 16:51:38 +020095static void mcf_serial_putc(const char c)
TsiChung Liew8e585f02007-06-18 13:50:13 -050096{
angelo@sysam.ite27802a2016-04-27 21:51:13 +020097 uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
TsiChung Liew8e585f02007-06-18 13:50:13 -050098
99 if (c == '\n')
100 serial_putc('\r');
101
102 /* Wait for last character to go. */
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200103 while (!(readb(&uart->usr) & UART_USR_TXRDY))
104 ;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500105
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200106 writeb(c, &uart->utb);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500107}
108
Marek Vasutabaef692012-09-13 16:51:38 +0200109static int mcf_serial_getc(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500110{
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200111 uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500112
113 /* Wait for a character to arrive. */
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200114 while (!(readb(&uart->usr) & UART_USR_RXRDY))
115 ;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500116
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200117 return readb(&uart->urb);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500118}
119
Marek Vasutabaef692012-09-13 16:51:38 +0200120static void mcf_serial_setbrg(void)
TsiChung Liew8e585f02007-06-18 13:50:13 -0500121{
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200122 uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500123
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200124 mcf_serial_setbrg_common(uart, gd->baudrate);
125}
TsiChung Liew8e585f02007-06-18 13:50:13 -0500126
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200127static int mcf_serial_tstc(void)
128{
129 uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500130
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200131 return readb(&uart->usr) & UART_USR_RXRDY;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500132}
Marek Vasutabaef692012-09-13 16:51:38 +0200133
Marek Vasutabaef692012-09-13 16:51:38 +0200134static struct serial_device mcf_serial_drv = {
135 .name = "mcf_serial",
136 .start = mcf_serial_init,
137 .stop = NULL,
138 .setbrg = mcf_serial_setbrg,
139 .putc = mcf_serial_putc,
Marek Vasutec3fd682012-10-06 14:07:02 +0000140 .puts = default_serial_puts,
Marek Vasutabaef692012-09-13 16:51:38 +0200141 .getc = mcf_serial_getc,
142 .tstc = mcf_serial_tstc,
143};
144
145void mcf_serial_initialize(void)
146{
147 serial_register(&mcf_serial_drv);
148}
149
150__weak struct serial_device *default_serial_console(void)
151{
152 return &mcf_serial_drv;
153}
angelo@sysam.ite27802a2016-04-27 21:51:13 +0200154
155#endif
156
157#ifdef CONFIG_DM_SERIAL
158
159static int coldfire_serial_probe(struct udevice *dev)
160{
161 struct coldfire_serial_platdata *plat = dev->platdata;
162
163 return mcf_serial_init_common((uart_t *)plat->base,
164 plat->port, plat->baudrate);
165}
166
167static int coldfire_serial_putc(struct udevice *dev, const char ch)
168{
169 struct coldfire_serial_platdata *plat = dev->platdata;
170 uart_t *uart = (uart_t *)plat->base;
171
172 /* Wait for last character to go. */
173 if (!(readb(&uart->usr) & UART_USR_TXRDY))
174 return -EAGAIN;
175
176 writeb(ch, &uart->utb);
177
178 return 0;
179}
180
181static int coldfire_serial_getc(struct udevice *dev)
182{
183 struct coldfire_serial_platdata *plat = dev->platdata;
184 uart_t *uart = (uart_t *)(plat->base);
185
186 /* Wait for a character to arrive. */
187 if (!(readb(&uart->usr) & UART_USR_RXRDY))
188 return -EAGAIN;
189
190 return readb(&uart->urb);
191}
192
193int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
194{
195 struct coldfire_serial_platdata *plat = dev->platdata;
196 uart_t *uart = (uart_t *)(plat->base);
197
198 mcf_serial_setbrg_common(uart, baudrate);
199
200 return 0;
201}
202
203static int coldfire_serial_pending(struct udevice *dev, bool input)
204{
205 struct coldfire_serial_platdata *plat = dev->platdata;
206 uart_t *uart = (uart_t *)(plat->base);
207
208 if (input)
209 return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
210 else
211 return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
212
213 return 0;
214}
215
216static const struct dm_serial_ops coldfire_serial_ops = {
217 .putc = coldfire_serial_putc,
218 .pending = coldfire_serial_pending,
219 .getc = coldfire_serial_getc,
220 .setbrg = coldfire_serial_setbrg,
221};
222
223U_BOOT_DRIVER(serial_coldfire) = {
224 .name = "serial_coldfire",
225 .id = UCLASS_SERIAL,
226 .probe = coldfire_serial_probe,
227 .ops = &coldfire_serial_ops,
228 .flags = DM_FLAG_PRE_RELOC,
229};
230#endif