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wdenkba91e262005-05-30 23:55:42 +00001/*
2 * (C) Copyright 2004
3 * Elmeg Communications Systems GmbH, Juergen Selent (j.selent@elmeg.de)
4 *
5 * Support for the Elmeg VoVPN Gateway Module
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/* define cpu used */
27#define CONFIG_MPC8272 1
28
29/* define busmode: 8260 */
30#undef CONFIG_BUSMODE_60x
31
32/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
33#ifdef CONFIG_CLKIN_66MHz
34#define CONFIG_8260_CLKIN 66666666 /* in Hz */
35#else
36#define CONFIG_8260_CLKIN 100000000 /* in Hz */
37#endif
38
39/* call board_early_init_f */
40#define CONFIG_BOARD_EARLY_INIT_F 1
41
42/* have misc_init_r() function */
43#define CONFIG_MISC_INIT_R 1
44
45/* have reset_phy_r() function */
46#define CONFIG_RESET_PHY_R 1
47
48/* have special reset function */
49#define CONFIG_HAVE_OWN_RESET 1
50
51/* allow serial and ethaddr to be overwritten */
52#define CONFIG_ENV_OVERWRITE
53
54/* watchdog disabled */
55#undef CONFIG_WATCHDOG
56
57/* include support for bzip2 compressed images */
58#undef CONFIG_BZIP2
59
60/* status led */
61#undef CONFIG_STATUS_LED /* XXX jse */
62
63/* vendor parameter protection */
64#define CONFIG_ENV_OVERWRITE
65
66/*
67 * select serial console configuration
68 *
69 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
70 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
71 * for SCC).
72 */
73#define CONFIG_CONS_ON_SMC
74#undef CONFIG_CONS_ON_SCC
75#undef CONFIG_CONS_NONE
76#define CONFIG_CONS_INDEX 1
77
78/* serial port default baudrate */
79#define CONFIG_BAUDRATE 115200
80
81/* echo on for serial download */
82#define CONFIG_LOADS_ECHO 1
83
84/* don't allow baudrate change */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_LOADS_BAUD_CHANGE
wdenkba91e262005-05-30 23:55:42 +000086
87/* supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkba91e262005-05-30 23:55:42 +000089
90/*
91 * select ethernet configuration
92 *
93 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
94 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
95 * for FCC)
96 *
97 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050098 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkba91e262005-05-30 23:55:42 +000099 */
100#undef CONFIG_ETHER_ON_SCC
101#define CONFIG_ETHER_ON_FCC
102#undef CONFIG_ETHER_NONE
103
104#ifdef CONFIG_ETHER_ON_FCC
105
106/* which SCC/FCC channel for ethernet */
107#define CONFIG_ETHER_INDEX 1
108
109/* Marvell Switch SMI base addr */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_PHY_ADDR 0x10
wdenkba91e262005-05-30 23:55:42 +0000111
112/* FCC1 RMII REFCLK is CLK10 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_CMXFCR_VALUE CMXFCR_TF1CS_CLK10
114#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_TF1CS_MSK)
wdenkba91e262005-05-30 23:55:42 +0000115
116/* BDs and buffers on 60x bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_CPMFCR_RAMTYPE 0
wdenkba91e262005-05-30 23:55:42 +0000118
119/* Local Protect, Full duplex, Flowcontrol, RMII */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_LPB|FCC_PSMR_FDE|\
wdenkba91e262005-05-30 23:55:42 +0000121 FCC_PSMR_FCE|FCC_PSMR_RMII)
122
123/* bit-bang MII PHY management */
124#define CONFIG_BITBANGMII
125
126#define MDIO_PORT 1 /* Port B */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200127
128#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
129 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
130#define MDC_DECLARE MDIO_DECLARE
131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */
133#define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */
134#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
135#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
136#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
137#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
138 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
139#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
140 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
wdenkba91e262005-05-30 23:55:42 +0000141#define MIIDELAY udelay(1)
142
143#endif
144
Jon Loeligera5562902007-07-08 15:31:57 -0500145/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500146 * BOOTP options
147 */
148#define CONFIG_BOOTP_BOOTFILESIZE
149#define CONFIG_BOOTP_BOOTPATH
150#define CONFIG_BOOTP_GATEWAY
151#define CONFIG_BOOTP_HOSTNAME
152
153
154/*
Jon Loeligera5562902007-07-08 15:31:57 -0500155 * Command line configuration.
156 */
wdenkba91e262005-05-30 23:55:42 +0000157
Jon Loeligera5562902007-07-08 15:31:57 -0500158#define CONFIG_CMD_BDI
159#define CONFIG_CMD_CONSOLE
160#define CONFIG_CMD_ECHO
Jon Loeligera5562902007-07-08 15:31:57 -0500161#define CONFIG_CMD_FLASH
162#define CONFIG_CMD_IMI
163#define CONFIG_CMD_IMLS
164#define CONFIG_CMD_LOADB
165#define CONFIG_CMD_MEMORY
166#define CONFIG_CMD_MISC
167#define CONFIG_CMD_NET
168#define CONFIG_CMD_PING
169#define CONFIG_CMD_RUN
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200170#define CONFIG_CMD_SAVEENV
171#define CONFIG_CMD_SOURCE
Jon Loeligera5562902007-07-08 15:31:57 -0500172
wdenkba91e262005-05-30 23:55:42 +0000173
174/*
175 * boot options & environment
176 */
177#define CONFIG_BOOTDELAY 3
178#define CONFIG_BOOTCOMMAND "run flash_self"
179#undef CONFIG_BOOTARGS
180#define CONFIG_EXTRA_ENV_SETTINGS \
181"clean_nv=erase fff20000 ffffffff\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100182"update_boss=tftp 100000 PPC/logic157.bin; protect off fff00000 ffffffff; erase fff00000 ffffffff; cp.b 100000 fff00000 ${filesize}; tftp 100000 PPC/bootmon157.bin; cp.b 100000 fff20000 ${filesize}\0" \
183"update_lx=tftp 100000 ${kernel}; erase ${kernel_addr} ffefffff; cp.b 100000 ${kernel_addr} ${filesize}\0" \
184"update_fs=tftp 100000 ${fs}.${fstype}; erase ff840000 ffdfffff; cp.b 100000 ff840000 ${filesize}\0" \
185"update_ub=tftp 100000 ${uboot}; protect off fff00000 fff1ffff; erase fff00000 fff1ffff; cp.b 100000 fff00000 ${filesize}; protect off ff820000 ff83ffff; erase ff820000 ff83ffff\0" \
186"flashargs=setenv bootargs root=${rootdev} rw rootfstype=${fstype}\0" \
187"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
188"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \
189"addmisc=setenv bootargs ${bootargs} console=${console},${baudrate} ethaddr=${ethaddr} panic=1\0" \
190"net_nfs=tftpboot 400000 ${kernel}; run nfsargs addip addmisc; bootm\0" \
191"net_self=tftpboot 400000 ${kernel}; run flashargs addmisc; bootm\0" \
192"flash_self=run flashargs addmisc; bootm ${kernel_addr}\0" \
193"flash_nfs=run nfsargs addip addmisc; bootm ${kernel_addr}\0" \
wdenkba91e262005-05-30 23:55:42 +0000194"fstype=cramfs\0" \
195"rootpath=/root_fs\0" \
196"uboot=PPC/u-boot.bin\0" \
197"kernel=PPC/uImage\0" \
198"kernel_addr=ffe00000\0" \
199"fs=PPC/root_fs\0" \
200"console=ttyS0\0" \
201"netdev=eth0\0" \
202"rootdev=31:3\0" \
203"ethaddr=00:09:4f:01:02:03\0" \
204"ipaddr=10.0.0.201\0" \
205"netmask=255.255.255.0\0" \
206"serverip=10.0.0.136\0" \
207"gatewayip=10.0.0.10\0" \
208"hostname=bastard\0" \
209""
210
211
212/*
213 * miscellaneous configurable options
214 */
215
216/* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_LONGHELP
wdenkba91e262005-05-30 23:55:42 +0000218
219/* monitor command prompt */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_PROMPT "=> "
wdenkba91e262005-05-30 23:55:42 +0000221
222/* console i/o buffer size */
Jon Loeligera5562902007-07-08 15:31:57 -0500223#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_CBSIZE 1024
wdenkba91e262005-05-30 23:55:42 +0000225#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_CBSIZE 256
wdenkba91e262005-05-30 23:55:42 +0000227#endif
228
229/* print buffer size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenkba91e262005-05-30 23:55:42 +0000231
232/* max number of command args */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_MAXARGS 16
wdenkba91e262005-05-30 23:55:42 +0000234
235/* boot argument buffer size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
wdenkba91e262005-05-30 23:55:42 +0000237
238/* memtest works on */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_MEMTEST_START 0x00100000
wdenkba91e262005-05-30 23:55:42 +0000240/* 1 ... 15 MB in DRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_MEMTEST_END 0x00f00000
wdenkba91e262005-05-30 23:55:42 +0000242/* full featured memtest */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_ALT_MEMTEST
wdenkba91e262005-05-30 23:55:42 +0000244
245/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_LOAD_ADDR 0x00100000
wdenkba91e262005-05-30 23:55:42 +0000247
248/* decrementer freq: 1 ms ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_HZ 1000
wdenkba91e262005-05-30 23:55:42 +0000250
251/* configure flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_FLASH_BASE 0xff800000
253#define CONFIG_SYS_MAX_FLASH_BANKS 1
254#define CONFIG_SYS_MAX_FLASH_SECT 64
255#define CONFIG_SYS_FLASH_SIZE 8
256#undef CONFIG_SYS_FLASH_16BIT
257#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
258#define CONFIG_SYS_FLASH_WRITE_TOUT 500
259#define CONFIG_SYS_FLASH_LOCK_TOUT 500
260#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
261#define CONFIG_SYS_FLASH_PROTECTION
wdenkba91e262005-05-30 23:55:42 +0000262
263/* monitor in flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_MONITOR_OFFSET 0x00700000
wdenkba91e262005-05-30 23:55:42 +0000265
266/* environment in flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200267#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00020000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200269#define CONFIG_ENV_SIZE 0x00020000
270#define CONFIG_ENV_SECT_SIZE 0x00020000
wdenkba91e262005-05-30 23:55:42 +0000271
272/*
273 * Initial memory map for linux
274 * For booting Linux, the board info and command line data
275 * have to be in the first 8 MB of memory, since this is
276 * the maximum mapped by the Linux kernel during initialization.
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
wdenkba91e262005-05-30 23:55:42 +0000279
280/* hard reset configuration words */
281#ifdef CONFIG_CLKIN_66MHz
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_HRCW_MASTER 0x04643050
wdenkba91e262005-05-30 23:55:42 +0000283#else
284#error NO HRCW FOR 100MHZ SPECIFIED !!!
285#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_HRCW_SLAVE1 0x00000000
287#define CONFIG_SYS_HRCW_SLAVE2 0x00000000
288#define CONFIG_SYS_HRCW_SLAVE3 0x00000000
289#define CONFIG_SYS_HRCW_SLAVE4 0x00000000
290#define CONFIG_SYS_HRCW_SLAVE5 0x00000000
291#define CONFIG_SYS_HRCW_SLAVE6 0x00000000
292#define CONFIG_SYS_HRCW_SLAVE7 0x00000000
wdenkba91e262005-05-30 23:55:42 +0000293
294/* internal memory mapped register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_IMMR 0xF0000000
wdenkba91e262005-05-30 23:55:42 +0000296
297/* definitions for initial stack pointer and data area (in DPRAM) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
299#define CONFIG_SYS_INIT_RAM_END 0x2000
300#define CONFIG_SYS_GBL_DATA_SIZE 128
301#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
302#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkba91e262005-05-30 23:55:42 +0000303
304/*
305 * Start addresses for the final memory configuration
306 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkba91e262005-05-30 23:55:42 +0000308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_SDRAM_BASE 0x00000000
310#define CONFIG_SYS_SDRAM_SIZE (32*1024*1024)
311#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
312#define CONFIG_SYS_MONITOR_FLASH (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_OFFSET)
313#define CONFIG_SYS_MONITOR_LEN 0x00020000
314#define CONFIG_SYS_MALLOC_LEN 0x00020000
wdenkba91e262005-05-30 23:55:42 +0000315
316/* boot flags */
317#define BOOTFLAG_COLD 0x01 /* normal power-on */
318#define BOOTFLAG_WARM 0x02 /* software reboot */
319
320/* cache configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_CACHELINE_SIZE 32 /* for MPC8260 */
Jon Loeligera5562902007-07-08 15:31:57 -0500322#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of above */
wdenkba91e262005-05-30 23:55:42 +0000324#endif
325
326/*
327 * HIDx - Hardware Implementation-dependent Registers
328 *-----------------------------------------------------------------------
329 * HID0 also contains cache control - initially enable both caches and
330 * invalidate contents, then the final state leaves only the instruction
331 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
332 * but Soft reset does not.
333 *
334 * HID1 has only read-only information - nothing to set.
335 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|\
wdenkba91e262005-05-30 23:55:42 +0000337 HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
339#define CONFIG_SYS_HID2 0
wdenkba91e262005-05-30 23:55:42 +0000340
341/* RMR - reset mode register - turn on checkstop reset enable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_RMR RMR_CSRE
wdenkba91e262005-05-30 23:55:42 +0000343
344/* BCR - bus configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_BCR 0x00000000
wdenkba91e262005-05-30 23:55:42 +0000346
347/* SIUMCR - siu module configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_SIUMCR 0x4905c000
wdenkba91e262005-05-30 23:55:42 +0000349
350/* SYPCR - system protection control */
351#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_SYPCR 0xffffff87
wdenkba91e262005-05-30 23:55:42 +0000353#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_SYPCR 0xffffff83
wdenkba91e262005-05-30 23:55:42 +0000355#endif
356
357/* TMCNTSC - time counter status and control */
358/* clear interrupts XXX jse */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359/*#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR) */
360#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|\
wdenkba91e262005-05-30 23:55:42 +0000361 TMCNTSC_TCF|TMCNTSC_TCE)
362
363/* PISCR - periodic interrupt status and control */
364/* clear interrupts XXX jse */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365/*#define CONFIG_SYS_PISCR (PISCR_PS) */
366#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenkba91e262005-05-30 23:55:42 +0000367
368/* SCCR - system clock control */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_SCCR 0x000001a9
wdenkba91e262005-05-30 23:55:42 +0000370
371/* RCCR - risc controller configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_RCCR 0
wdenkba91e262005-05-30 23:55:42 +0000373
374/*
375 * MEMORY MAP
376 * ----------
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200377 * CS0 - FLASH 8MB/8Bit base=0xff800000 (boot: 0xfe000000, 8x mirrored)
wdenkba91e262005-05-30 23:55:42 +0000378 * CS1 - SDRAM 32MB/64Bit base=0x00000000
379 * CS2 - DSP/SL1 1MB/16Bit base=0xf0100000
380 * CS3 - DSP/SL2 1MB/16Bit base=0xf0200000
381 * CS4 - DSP/SL3 1MB/16Bit base=0xf0300000
382 * CS5 - DSP/SL4 1MB/16Bit base=0xf0400000
383 * CS7 - DPRAM 1KB/8Bit base=0xf0500000, size=32KB (32x mirrored)
384 * x - IMMR 384KB base=0xf0000000
385 */
386/* XXX jse 100MHz TODO */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_BR0_PRELIM 0xff800801
388#define CONFIG_SYS_OR0_PRELIM 0xff801e44
389#define CONFIG_SYS_BR1_PRELIM 0x00000041
390#define CONFIG_SYS_OR1_PRELIM 0xfe002ec0
wdenkba91e262005-05-30 23:55:42 +0000391#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_BR2_PRELIM 0xf0101001
393#define CONFIG_SYS_OR2_PRELIM 0xfff00ef4
394#define CONFIG_SYS_BR3_PRELIM 0xf0201001
395#define CONFIG_SYS_OR3_PRELIM 0xfff00ef4
396#define CONFIG_SYS_BR4_PRELIM 0xf0301001
397#define CONFIG_SYS_OR4_PRELIM 0xfff00ef4
398#define CONFIG_SYS_BR5_PRELIM 0xf0401001
399#define CONFIG_SYS_OR5_PRELIM 0xfff00ef4
wdenkba91e262005-05-30 23:55:42 +0000400#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_BR2_PRELIM 0xf0101081
402#define CONFIG_SYS_OR2_PRELIM 0xfff00104
403#define CONFIG_SYS_BR3_PRELIM 0xf0201081
404#define CONFIG_SYS_OR3_PRELIM 0xfff00104
405#define CONFIG_SYS_BR4_PRELIM 0xf0301081
406#define CONFIG_SYS_OR4_PRELIM 0xfff00104
407#define CONFIG_SYS_BR5_PRELIM 0xf0401081
408#define CONFIG_SYS_OR5_PRELIM 0xfff00104
wdenkba91e262005-05-30 23:55:42 +0000409#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_BR7_PRELIM 0xf0500881
411#define CONFIG_SYS_OR7_PRELIM 0xffff8104
412#define CONFIG_SYS_MPTPR 0x2700
413#define CONFIG_SYS_PSDMR 0x822a2452 /* optimal */
414/*#define CONFIG_SYS_PSDMR 0x822a48a3 */ /* relaxed */
415#define CONFIG_SYS_PSRT 0x1a
wdenkba91e262005-05-30 23:55:42 +0000416
417/* "bad" address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_RESET_ADDRESS 0x40000000
wdenkba91e262005-05-30 23:55:42 +0000419
420#endif /* __CONFIG_H */