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wdenkc6097192002-11-03 00:24:07 +00001/*-----------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21/*----------------------------------------------------------------------------+
22 *
23 * File Name: 405gp_pci.c
24 *
25 * Function: Initialization code for the 405GP PCI Configuration regs.
26 *
27 * Author: Mark Game
28 *
29 * Change Activity-
30 *
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 09-Sep-98 Created MCG
34 * 02-Nov-98 Removed External arbiter selected message JWB
35 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
36 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
37 * from (0 to n) to (1 to n).
38 * 17-May-99 Port to Walnut JWB
39 * 17-Jun-99 Updated for VGA support JWB
40 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
41 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
42 * target latency timer values are not supported).
43 * Should be fixed in pass 2.
44 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
45 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
46 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
47 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
48 * really required after a reset since PMMxMAs are already
Wolfgang Denk53677ef2008-05-20 16:00:29 +020049 * disabled but is a good practice nonetheless. JWB
wdenkc6097192002-11-03 00:24:07 +000050 * 12-Jun-01 stefan.roese@esd-electronics.com
51 * - PCI host/adapter handling reworked
52 * 09-Jul-01 stefan.roese@esd-electronics.com
53 * - PCI host now configures from device 0 (not 1) to max_dev,
54 * (host configures itself)
55 * - On CPCI-405 pci base address and size is generated from
56 * SDRAM and FLASH size (CFG regs not used anymore)
57 * - Some minor changes for CPCI-405-A (adapter version)
58 * 14-Sep-01 stefan.roese@esd-electronics.com
59 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
60 * 28-Sep-01 stefan.roese@esd-electronics.com
61 * - Changed pci master configuration for linux compatibility
62 * (no need for bios_fixup() anymore)
63 * 26-Feb-02 stefan.roese@esd-electronics.com
64 * - Bug fixed in pci configuration (Andrew May)
65 * - Removed pci class code init for CPCI405 board
66 * 15-May-02 stefan.roese@esd-electronics.com
67 * - New vga device handling
68 * 29-May-02 stefan.roese@esd-electronics.com
69 * - PCI class code init added (if defined)
70 *----------------------------------------------------------------------------*/
71
72#include <common.h>
73#include <command.h>
wdenkc6097192002-11-03 00:24:07 +000074#if !defined(CONFIG_440)
Stefan Roese3048bcb2007-10-03 15:01:02 +020075#include <asm/4xx_pci.h>
wdenkc6097192002-11-03 00:24:07 +000076#endif
77#include <asm/processor.h>
78#include <pci.h>
79
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +020080#ifdef CONFIG_PCI
81
Wolfgang Denkd87080b2006-03-31 18:32:53 +020082DECLARE_GLOBAL_DATA_PTR;
83
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +020084/*
85 * Board-specific pci initialization
86 * Platform code can reimplement pci_pre_init() if needed
87 */
88int __pci_pre_init(struct pci_controller *hose)
89{
Matthias Fuchs123f1022009-07-08 13:43:55 +020090#if defined (CONFIG_405EP)
91 /*
92 * Enable the internal PCI arbiter by default.
93 *
94 * On 405EP CPUs the internal arbiter can be controlled
95 * by the I2C strapping EEPROM. If you want to do so
96 * or if you want to disable the arbiter pci_pre_init()
97 * must be reimplemented without enabling the arbiter.
98 * The arbiter is enabled in this place because of
99 * compatibility reasons.
100 */
101 mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN);
102#endif /* CONFIG_405EP */
103
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200104 return 1;
105}
106int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
wdenkc6097192002-11-03 00:24:07 +0000107
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200108#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
wdenkc6097192002-11-03 00:24:07 +0000109
Stefan Roese2076d0a2006-01-18 20:03:15 +0100110#if defined(CONFIG_PMC405)
111ushort pmc405_pci_subsys_deviceid(void);
112#endif
113
wdenkc6097192002-11-03 00:24:07 +0000114/*#define DEBUG*/
115
Matthias Fuchsd0a13642009-07-03 16:06:06 +0200116int __is_pci_host(struct pci_controller *hose)
117{
118#if defined(CONFIG_405GP)
119 if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
120 return 1;
121#elif defined (CONFIG_405EP)
122 if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN)
123 return 1;
124#endif
125 return 0;
126}
127int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
128
wdenkc6097192002-11-03 00:24:07 +0000129/*-----------------------------------------------------------------------------+
130 * pci_init. Initializes the 405GP PCI Configuration regs.
131 *-----------------------------------------------------------------------------*/
132void pci_405gp_init(struct pci_controller *hose)
133{
wdenkc6097192002-11-03 00:24:07 +0000134 int i, reg_num = 0;
135 bd_t *bd = gd->bd;
136
137 unsigned short temp_short;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
stroese5e746fc2004-12-16 18:15:52 +0000139#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
stroesefddae7b2005-04-20 06:52:40 +0000140 char *ptmla_str, *ptmms_str;
Stefan Roese2076d0a2006-01-18 20:03:15 +0100141#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
143 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
wdenkc6097192002-11-03 00:24:07 +0000144#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
145 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
146 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
147 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
148 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
149#else
150 unsigned long pmmla[3] = {0x80000000, 0,0};
151 unsigned long pmmma[3] = {0xC0000001, 0,0};
152 unsigned long pmmpcila[3] = {0x80000000, 0,0};
153 unsigned long pmmpciha[3] = {0x00000000, 0,0};
154#endif
stroese5e746fc2004-12-16 18:15:52 +0000155#ifdef CONFIG_PCI_PNP
156#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
157 char *s;
158#endif
159#endif
wdenkc6097192002-11-03 00:24:07 +0000160
stroesefddae7b2005-04-20 06:52:40 +0000161#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
162 ptmla_str = getenv("ptm1la");
163 ptmms_str = getenv("ptm1ms");
164 if(NULL != ptmla_str && NULL != ptmms_str ) {
165 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
166 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
167 }
168
169 ptmla_str = getenv("ptm2la");
170 ptmms_str = getenv("ptm2ms");
171 if(NULL != ptmla_str && NULL != ptmms_str ) {
172 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
173 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
174 }
175#endif
176
wdenkc6097192002-11-03 00:24:07 +0000177 /*
178 * Register the hose
179 */
180 hose->first_busno = 0;
181 hose->last_busno = 0xff;
182
183 /* ISA/PCI I/O space */
184 pci_set_region(hose->regions + reg_num++,
185 MIN_PCI_PCI_IOADDR,
186 MIN_PLB_PCI_IOADDR,
187 0x10000,
188 PCI_REGION_IO);
189
190 /* PCI I/O space */
191 pci_set_region(hose->regions + reg_num++,
192 0x00800000,
193 0xe8800000,
194 0x03800000,
195 PCI_REGION_IO);
196
197 reg_num = 2;
198
199 /* Memory spaces */
200 for (i=0; i<2; i++)
201 if (ptmms[i] & 1)
202 {
203 if (!i) hose->pci_fb = hose->regions + reg_num;
204
205 pci_set_region(hose->regions + reg_num++,
206 ptmpcila[i], ptmla[i],
207 ~(ptmms[i] & 0xfffff000) + 1,
208 PCI_REGION_MEM |
Kumar Galaff4e66e2009-02-06 09:49:31 -0600209 PCI_REGION_SYS_MEMORY);
wdenkc6097192002-11-03 00:24:07 +0000210 }
211
212 /* PCI memory spaces */
213 for (i=0; i<3; i++)
214 if (pmmma[i] & 1)
215 {
216 pci_set_region(hose->regions + reg_num++,
217 pmmpcila[i], pmmla[i],
218 ~(pmmma[i] & 0xfffff000) + 1,
219 PCI_REGION_MEM);
220 }
221
222 hose->region_count = reg_num;
223
224 pci_setup_indirect(hose,
225 PCICFGADR,
226 PCICFGDATA);
227
228 if (hose->pci_fb)
229 pciauto_region_init(hose->pci_fb);
230
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200231 /* Let board change/modify hose & do initial checks */
232 if (pci_pre_init (hose) == 0) {
233 printf("PCI: Board-specific initialization failed.\n");
234 printf("PCI: Configuration aborted.\n");
235 return;
236 }
237
wdenkc6097192002-11-03 00:24:07 +0000238 pci_register_hose(hose);
239
240 /*--------------------------------------------------------------------------+
241 * 405GP PCI Master configuration.
242 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
243 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
244 * Use byte reversed out routines to handle endianess.
245 *--------------------------------------------------------------------------*/
wdenkf3e0de62003-06-04 15:05:30 +0000246 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
wdenkc6097192002-11-03 00:24:07 +0000247 out32r(PMM0LA, pmmla[0]);
248 out32r(PMM0PCILA, pmmpcila[0]);
249 out32r(PMM0PCIHA, pmmpciha[0]);
250 out32r(PMM0MA, pmmma[0]);
251
252 /*--------------------------------------------------------------------------+
253 * PMM1 is not used. Initialize them to zero.
254 *--------------------------------------------------------------------------*/
wdenkf3e0de62003-06-04 15:05:30 +0000255 out32r(PMM1MA, (pmmma[1]&~0x1));
wdenkc6097192002-11-03 00:24:07 +0000256 out32r(PMM1LA, pmmla[1]);
257 out32r(PMM1PCILA, pmmpcila[1]);
258 out32r(PMM1PCIHA, pmmpciha[1]);
259 out32r(PMM1MA, pmmma[1]);
260
261 /*--------------------------------------------------------------------------+
262 * PMM2 is not used. Initialize them to zero.
263 *--------------------------------------------------------------------------*/
wdenk8bde7f72003-06-27 21:31:46 +0000264 out32r(PMM2MA, (pmmma[2]&~0x1));
wdenkc6097192002-11-03 00:24:07 +0000265 out32r(PMM2LA, pmmla[2]);
266 out32r(PMM2PCILA, pmmpcila[2]);
267 out32r(PMM2PCIHA, pmmpciha[2]);
268 out32r(PMM2MA, pmmma[2]);
269
270 /*--------------------------------------------------------------------------+
271 * 405GP PCI Target configuration. (PTM1)
272 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
273 *--------------------------------------------------------------------------*/
274 out32r(PTM1LA, ptmla[0]); /* insert address */
275 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
wdenk4654af22003-10-22 09:00:28 +0000276 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
wdenkc6097192002-11-03 00:24:07 +0000277
278 /*--------------------------------------------------------------------------+
279 * 405GP PCI Target configuration. (PTM2)
280 *--------------------------------------------------------------------------*/
281 out32r(PTM2LA, ptmla[1]); /* insert address */
wdenk4654af22003-10-22 09:00:28 +0000282 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
283
wdenkc6097192002-11-03 00:24:07 +0000284 if (ptmms[1] == 0)
285 {
286 out32r(PTM2MS, 0x00000001); /* set enable bit */
287 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
288 out32r(PTM2MS, 0x00000000); /* disable */
289 }
290 else
291 {
292 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
293 }
294
295 /*
296 * Insert Subsystem Vendor and Device ID
297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
wdenkc6097192002-11-03 00:24:07 +0000299#ifdef CONFIG_CPCI405
Matthias Fuchsd0a13642009-07-03 16:06:06 +0200300 if (is_pci_host(hose))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
wdenkc6097192002-11-03 00:24:07 +0000302 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
wdenkc6097192002-11-03 00:24:07 +0000304#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
wdenkc6097192002-11-03 00:24:07 +0000306#endif
307
308 /*
309 * Insert Class-code
310 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#ifdef CONFIG_SYS_PCI_CLASSCODE
312 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
313#endif /* CONFIG_SYS_PCI_CLASSCODE */
wdenkc6097192002-11-03 00:24:07 +0000314
315 /*--------------------------------------------------------------------------+
Wolfgang Denk8ed44d92008-10-19 02:35:50 +0200316 * If PCI speed = 66MHz, set 66MHz capable bit.
wdenkc6097192002-11-03 00:24:07 +0000317 *--------------------------------------------------------------------------*/
318 if (bd->bi_pci_busfreq >= 66000000) {
319 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
320 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
321 }
322
323#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
wdenk4654af22003-10-22 09:00:28 +0000324#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
Matthias Fuchsd0a13642009-07-03 16:06:06 +0200325 if (is_pci_host(hose) ||
stroese5e746fc2004-12-16 18:15:52 +0000326 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
wdenkc6097192002-11-03 00:24:07 +0000327#endif
328 {
329 /*--------------------------------------------------------------------------+
330 * Write the 405GP PCI Configuration regs.
331 * Enable 405GP to be a master on the PCI bus (PMM).
332 * Enable 405GP to act as a PCI memory target (PTM).
333 *--------------------------------------------------------------------------*/
334 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
335 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
336 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
337 }
338#endif
339
stroese428c5632003-09-12 08:52:09 +0000340#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
341 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
342#endif
343
wdenkc6097192002-11-03 00:24:07 +0000344 /*
345 * Set HCE bit (Host Configuration Enabled)
346 */
347 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
348 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
349
350#ifdef CONFIG_PCI_PNP
351 /*--------------------------------------------------------------------------+
352 * Scan the PCI bus and configure devices found.
353 *--------------------------------------------------------------------------*/
354#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
Matthias Fuchsd0a13642009-07-03 16:06:06 +0200355 if (is_pci_host(hose) ||
stroese5e746fc2004-12-16 18:15:52 +0000356 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
wdenkc6097192002-11-03 00:24:07 +0000357#endif
358 {
359#ifdef CONFIG_PCI_SCAN_SHOW
360 printf("PCI: Bus Dev VenId DevId Class Int\n");
361#endif
wdenkc6097192002-11-03 00:24:07 +0000362 hose->last_busno = pci_hose_scan(hose);
363 }
364#endif /* CONFIG_PCI_PNP */
365
366}
367
368/*
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100369 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
wdenkc6097192002-11-03 00:24:07 +0000370 * be set as an Adapter.
371 *
372 * I (Andrew May) don't know what we should do here, but I don't want
373 * the auto setup of a PCI device disabling what is done pci_405gp_init
374 * as has happened before.
375 */
376void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
377 struct pci_config_table *entry)
378{
379#ifdef DEBUG
wdenk8bde7f72003-06-27 21:31:46 +0000380 printf("405gp_setup_bridge\n");
wdenkc6097192002-11-03 00:24:07 +0000381#endif
382}
383
384/*
385 *
386 */
387
388void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
389{
390 unsigned char int_line = 0xff;
391
392 /*
393 * Write pci interrupt line register (cpci405 specific)
394 */
395 switch (PCI_DEV(dev) & 0x03)
396 {
397 case 0:
398 int_line = 27 + 2;
399 break;
400 case 1:
401 int_line = 27 + 3;
402 break;
403 case 2:
404 int_line = 27 + 0;
405 break;
406 case 3:
407 int_line = 27 + 1;
408 break;
409 }
410
411 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
412}
413
414void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
415 struct pci_config_table *entry)
416{
417 unsigned int cmdstat = 0;
418
Stefan Roesef3fecfe2006-03-13 09:43:01 +0100419 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000420
421 /* always enable io space on vga boards */
422 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
423 cmdstat |= PCI_COMMAND_IO;
424 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
425}
426
Wolfgang Denk9045f332007-06-08 10:24:58 +0200427#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
wdenkc6097192002-11-03 00:24:07 +0000428
429/*
430 *As is these functs get called out of flash Not a horrible
431 *thing, but something to keep in mind. (no statics?)
432 */
433static struct pci_config_table pci_405gp_config_table[] = {
434/*if VendID is 0 it terminates the table search (ie Walnut)*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
436 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
wdenkc6097192002-11-03 00:24:07 +0000437 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
438#endif
439 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
440 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
441
442 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
443 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
444
445 { }
446};
447
448static struct pci_controller hose = {
449 fixup_irq: pci_405gp_fixup_irq,
450 config_table: pci_405gp_config_table,
451};
452
stroesead10dd92003-02-14 11:21:23 +0000453void pci_init_board(void)
wdenkc6097192002-11-03 00:24:07 +0000454{
455 /*we want the ptrs to RAM not flash (ie don't use init list)*/
456 hose.fixup_irq = pci_405gp_fixup_irq;
457 hose.config_table = pci_405gp_config_table;
458 pci_405gp_init(&hose);
459}
460
461#endif
462
wdenkc6097192002-11-03 00:24:07 +0000463#endif /* CONFIG_405GP */
464
465/*-----------------------------------------------------------------------------+
466 * CONFIG_440
467 *-----------------------------------------------------------------------------*/
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200468#if defined(CONFIG_440)
wdenkc6097192002-11-03 00:24:07 +0000469
470static struct pci_controller ppc440_hose = {0};
471
472
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200473int pci_440_init (struct pci_controller *hose)
wdenkc6097192002-11-03 00:24:07 +0000474{
475 int reg_num = 0;
wdenkc6097192002-11-03 00:24:07 +0000476
Stefan Roese5568e612005-11-22 13:20:42 +0100477#ifndef CONFIG_DISABLE_PISE_TEST
wdenkc6097192002-11-03 00:24:07 +0000478 /*--------------------------------------------------------------------------+
479 * The PCI initialization sequence enable bit must be set ... if not abort
wdenk3c74e322004-02-22 23:46:08 +0000480 * pci setup since updating the bit requires chip reset.
wdenkc6097192002-11-03 00:24:07 +0000481 *--------------------------------------------------------------------------*/
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200482#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese5568e612005-11-22 13:20:42 +0100483 unsigned long strap;
484
wdenk3c74e322004-02-22 23:46:08 +0000485 mfsdr(sdr_sdstp1,strap);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100486 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
wdenk3c74e322004-02-22 23:46:08 +0000487 printf("PCI: SDR0_STRP1[PISE] not set.\n");
488 printf("PCI: Configuration aborted.\n");
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200489 return -1;
wdenk3c74e322004-02-22 23:46:08 +0000490 }
Stefan Roese5568e612005-11-22 13:20:42 +0100491#elif defined(CONFIG_440GP)
492 unsigned long strap;
493
wdenk3c74e322004-02-22 23:46:08 +0000494 strap = mfdcr(cpc0_strp1);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100495 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
wdenk3c74e322004-02-22 23:46:08 +0000496 printf("PCI: CPC0_STRP1[PISE] not set.\n");
497 printf("PCI: Configuration aborted.\n");
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200498 return -1;
wdenk3c74e322004-02-22 23:46:08 +0000499 }
500#endif
Stefan Roese5568e612005-11-22 13:20:42 +0100501#endif /* CONFIG_DISABLE_PISE_TEST */
502
wdenkc6097192002-11-03 00:24:07 +0000503 /*--------------------------------------------------------------------------+
504 * PCI controller init
505 *--------------------------------------------------------------------------*/
506 hose->first_busno = 0;
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200507 hose->last_busno = 0;
wdenkc6097192002-11-03 00:24:07 +0000508
Marian Balakowiczfbb0b552006-07-04 00:55:47 +0200509 /* PCI I/O space */
wdenkc6097192002-11-03 00:24:07 +0000510 pci_set_region(hose->regions + reg_num++,
511 0x00000000,
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100512 PCIX0_IOBASE,
513 0x10000,
514 PCI_REGION_IO);
wdenkc6097192002-11-03 00:24:07 +0000515
Marian Balakowiczfbb0b552006-07-04 00:55:47 +0200516 /* PCI memory space */
wdenkc6097192002-11-03 00:24:07 +0000517 pci_set_region(hose->regions + reg_num++,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518 CONFIG_SYS_PCI_TARGBASE,
519 CONFIG_SYS_PCI_MEMBASE,
520#ifdef CONFIG_SYS_PCI_MEMSIZE
521 CONFIG_SYS_PCI_MEMSIZE,
Stefan Roese899620c2006-08-15 14:22:35 +0200522#else
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100523 0x10000000,
Stefan Roese899620c2006-08-15 14:22:35 +0200524#endif
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100525 PCI_REGION_MEM );
Marian Balakowiczfbb0b552006-07-04 00:55:47 +0200526
527#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
528 defined(CONFIG_PCI_SYS_MEM_SIZE)
529 /* System memory space */
530 pci_set_region(hose->regions + reg_num++,
531 CONFIG_PCI_SYS_MEM_BUS,
532 CONFIG_PCI_SYS_MEM_PHYS,
533 CONFIG_PCI_SYS_MEM_SIZE,
Kumar Galaff4e66e2009-02-06 09:49:31 -0600534 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
Marian Balakowiczfbb0b552006-07-04 00:55:47 +0200535#endif
536
wdenkc6097192002-11-03 00:24:07 +0000537 hose->region_count = reg_num;
538
539 pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
540
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100541 /* Let board change/modify hose & do initial checks */
542 if (pci_pre_init (hose) == 0) {
543 printf("PCI: Board-specific initialization failed.\n");
544 printf("PCI: Configuration aborted.\n");
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200545 return -1;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100546 }
wdenkc6097192002-11-03 00:24:07 +0000547
548 pci_register_hose( hose );
549
550 /*--------------------------------------------------------------------------+
551 * PCI target init
552 *--------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#if defined(CONFIG_SYS_PCI_TARGET_INIT)
wdenkc6097192002-11-03 00:24:07 +0000554 pci_target_init(hose); /* Let board setup pci target */
555#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200556 out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
557 out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100558 out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
wdenkc6097192002-11-03 00:24:07 +0000559#endif
560
Stefan Roese8ac41e32008-03-11 15:05:26 +0100561#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
562 defined(CONFIG_460EX) || defined(CONFIG_460GT)
wdenk3c74e322004-02-22 23:46:08 +0000563 out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
564 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200565#elif defined(PCIX0_BRDGOPT1)
wdenk3c74e322004-02-22 23:46:08 +0000566 out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
567 out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */
568#endif
wdenkc6097192002-11-03 00:24:07 +0000569
570 /*--------------------------------------------------------------------------+
571 * PCI master init: default is one 256MB region for PCI memory:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
wdenkc6097192002-11-03 00:24:07 +0000573 *--------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#if defined(CONFIG_SYS_PCI_MASTER_INIT)
wdenkc6097192002-11-03 00:24:07 +0000575 pci_master_init(hose); /* Let board setup pci master */
576#else
577 out32r( PCIX0_POM0SA, 0 ); /* disable */
578 out32r( PCIX0_POM1SA, 0 ); /* disable */
579 out32r( PCIX0_POM2SA, 0 ); /* disable */
Anatolij Gustschinf8853d12009-03-20 12:45:50 +0100580#if defined(CONFIG_440SPE)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200581 out32r( PCIX0_POM0LAL, 0x10000000 );
582 out32r( PCIX0_POM0LAH, 0x0000000c );
Anatolij Gustschinf8853d12009-03-20 12:45:50 +0100583#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
584 out32r( PCIX0_POM0LAL, 0x20000000 );
585 out32r( PCIX0_POM0LAH, 0x0000000c );
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200586#else
wdenkc6097192002-11-03 00:24:07 +0000587 out32r( PCIX0_POM0LAL, 0x00000000 );
588 out32r( PCIX0_POM0LAH, 0x00000003 );
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200589#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590 out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
wdenkc6097192002-11-03 00:24:07 +0000591 out32r( PCIX0_POM0PCIAH, 0x00000000 );
592 out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100593 out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
wdenkc6097192002-11-03 00:24:07 +0000594#endif
595
596 /*--------------------------------------------------------------------------+
597 * PCI host configuration -- we don't make any assumptions here ... the
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100598 * _board_must_indicate_ what to do -- there's just too many runtime
599 * scenarios in environments like cPCI, PPMC, etc. to make a determination
600 * based on hard-coded values or state of arbiter enable.
wdenkc6097192002-11-03 00:24:07 +0000601 *--------------------------------------------------------------------------*/
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100602 if (is_pci_host(hose)) {
wdenkc6097192002-11-03 00:24:07 +0000603#ifdef CONFIG_PCI_SCAN_SHOW
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100604 printf("PCI: Bus Dev VenId DevId Class Int\n");
wdenkc6097192002-11-03 00:24:07 +0000605#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200606#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
607 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100608 out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200609#endif
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100610 hose->last_busno = pci_hose_scan(hose);
611 }
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200612 return hose->last_busno;
wdenkc6097192002-11-03 00:24:07 +0000613}
614
stroesead10dd92003-02-14 11:21:23 +0000615void pci_init_board(void)
wdenkc6097192002-11-03 00:24:07 +0000616{
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200617 int busno;
618
619 busno = pci_440_init (&ppc440_hose);
Dirk Eibach59d1bda2009-02-03 15:15:21 +0100620#if (defined(CONFIG_440SPE) || \
621 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
622 !defined(CONFIG_PCI_DISABLE_PCIE)
Grzegorz Bernacki7f191392007-09-07 18:20:23 +0200623 pcie_setup_hoses(busno + 1);
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200624#endif
wdenkc6097192002-11-03 00:24:07 +0000625}
626
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200627#endif /* CONFIG_440 */
Stefan Roese1d7b8742007-10-05 17:09:36 +0200628
629#if defined(CONFIG_405EX)
630void pci_init_board(void)
631{
632#ifdef CONFIG_PCI_SCAN_SHOW
633 printf("PCI: Bus Dev VenId DevId Class Int\n");
634#endif
635 pcie_setup_hoses(0);
636}
637#endif /* CONFIG_405EX */
638
Matthias Fuchs5a1c9ff2007-06-24 17:23:41 +0200639#endif /* CONFIG_PCI */