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wdenk5653fc32004-02-08 22:55:38 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2002-2004
wdenk5653fc32004-02-08 22:55:38 +00003 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
wdenk5653fc32004-02-08 22:55:38 +00007 *
wdenkbf9e3b32004-02-12 00:47:09 +00008 * Copyright (C) 2004
9 * Ed Okerson
Stefan Roese260421a2006-11-13 13:55:24 +010010 *
11 * Copyright (C) 2006
12 * Tolunay Orkun <listmember@orkun.us>
wdenkbf9e3b32004-02-12 00:47:09 +000013 *
wdenk5653fc32004-02-08 22:55:38 +000014 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 *
wdenk5653fc32004-02-08 22:55:38 +000032 */
33
34/* The DEBUG define must be before common to enable debugging */
wdenk2d1a5372004-02-23 19:30:57 +000035/* #define DEBUG */
36
wdenk5653fc32004-02-08 22:55:38 +000037#include <common.h>
38#include <asm/processor.h>
Haiying Wang3a197b22007-02-21 16:52:31 +010039#include <asm/io.h>
wdenk4c0d4c32004-06-09 17:34:58 +000040#include <asm/byteorder.h>
wdenk2a8af182005-04-13 10:02:42 +000041#include <environment.h>
wdenkbf9e3b32004-02-12 00:47:09 +000042#ifdef CFG_FLASH_CFI_DRIVER
wdenk028ab6b2004-02-23 23:54:43 +000043
wdenk5653fc32004-02-08 22:55:38 +000044/*
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +010045 * This file implements a Common Flash Interface (CFI) driver for
46 * U-Boot.
47 *
48 * The width of the port and the width of the chips are determined at
49 * initialization. These widths are used to calculate the address for
50 * access CFI data structures.
wdenk5653fc32004-02-08 22:55:38 +000051 *
52 * References
53 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
54 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
55 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
56 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
Stefan Roese260421a2006-11-13 13:55:24 +010057 * AMD CFI Specification, Release 2.0 December 1, 2001
58 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
59 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
wdenk5653fc32004-02-08 22:55:38 +000060 *
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +010061 * Define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
Heiko Schocherd0b6e142007-01-19 18:05:26 +010062 * reading and writing ... (yes there is such a Hardware).
wdenk5653fc32004-02-08 22:55:38 +000063 */
64
wdenkbf9e3b32004-02-12 00:47:09 +000065#ifndef CFG_FLASH_BANKS_LIST
66#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
67#endif
68
wdenk5653fc32004-02-08 22:55:38 +000069#define FLASH_CMD_CFI 0x98
70#define FLASH_CMD_READ_ID 0x90
71#define FLASH_CMD_RESET 0xff
72#define FLASH_CMD_BLOCK_ERASE 0x20
73#define FLASH_CMD_ERASE_CONFIRM 0xD0
74#define FLASH_CMD_WRITE 0x40
75#define FLASH_CMD_PROTECT 0x60
76#define FLASH_CMD_PROTECT_SET 0x01
77#define FLASH_CMD_PROTECT_CLEAR 0xD0
78#define FLASH_CMD_CLEAR_STATUS 0x50
wdenkbf9e3b32004-02-12 00:47:09 +000079#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
80#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
wdenk5653fc32004-02-08 22:55:38 +000081
82#define FLASH_STATUS_DONE 0x80
83#define FLASH_STATUS_ESS 0x40
84#define FLASH_STATUS_ECLBS 0x20
85#define FLASH_STATUS_PSLBS 0x10
86#define FLASH_STATUS_VPENS 0x08
87#define FLASH_STATUS_PSS 0x04
88#define FLASH_STATUS_DPS 0x02
89#define FLASH_STATUS_R 0x01
90#define FLASH_STATUS_PROTECT 0x01
91
92#define AMD_CMD_RESET 0xF0
93#define AMD_CMD_WRITE 0xA0
94#define AMD_CMD_ERASE_START 0x80
95#define AMD_CMD_ERASE_SECTOR 0x30
wdenk855a4962004-03-14 18:23:55 +000096#define AMD_CMD_UNLOCK_START 0xAA
97#define AMD_CMD_UNLOCK_ACK 0x55
Stefan Roese79b4cda2006-02-28 15:29:58 +010098#define AMD_CMD_WRITE_TO_BUFFER 0x25
99#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
wdenk5653fc32004-02-08 22:55:38 +0000100
101#define AMD_STATUS_TOGGLE 0x40
102#define AMD_STATUS_ERROR 0x20
Stefan Roese79b4cda2006-02-28 15:29:58 +0100103
Stefan Roese260421a2006-11-13 13:55:24 +0100104#define FLASH_OFFSET_MANUFACTURER_ID 0x00
105#define FLASH_OFFSET_DEVICE_ID 0x01
106#define FLASH_OFFSET_DEVICE_ID2 0x0E
107#define FLASH_OFFSET_DEVICE_ID3 0x0F
wdenk5653fc32004-02-08 22:55:38 +0000108#define FLASH_OFFSET_CFI 0x55
Wolfgang Denk92eb7292006-12-27 01:26:13 +0100109#define FLASH_OFFSET_CFI_ALT 0x555
wdenk5653fc32004-02-08 22:55:38 +0000110#define FLASH_OFFSET_CFI_RESP 0x10
wdenkbf9e3b32004-02-12 00:47:09 +0000111#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100112/* extended query table primary address */
113#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
wdenk5653fc32004-02-08 22:55:38 +0000114#define FLASH_OFFSET_WTOUT 0x1F
wdenkbf9e3b32004-02-12 00:47:09 +0000115#define FLASH_OFFSET_WBTOUT 0x20
wdenk5653fc32004-02-08 22:55:38 +0000116#define FLASH_OFFSET_ETOUT 0x21
wdenkbf9e3b32004-02-12 00:47:09 +0000117#define FLASH_OFFSET_CETOUT 0x22
wdenk5653fc32004-02-08 22:55:38 +0000118#define FLASH_OFFSET_WMAX_TOUT 0x23
wdenkbf9e3b32004-02-12 00:47:09 +0000119#define FLASH_OFFSET_WBMAX_TOUT 0x24
wdenk5653fc32004-02-08 22:55:38 +0000120#define FLASH_OFFSET_EMAX_TOUT 0x25
wdenkbf9e3b32004-02-12 00:47:09 +0000121#define FLASH_OFFSET_CEMAX_TOUT 0x26
wdenk5653fc32004-02-08 22:55:38 +0000122#define FLASH_OFFSET_SIZE 0x27
wdenkbf9e3b32004-02-12 00:47:09 +0000123#define FLASH_OFFSET_INTERFACE 0x28
124#define FLASH_OFFSET_BUFFER_SIZE 0x2A
wdenk5653fc32004-02-08 22:55:38 +0000125#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
126#define FLASH_OFFSET_ERASE_REGIONS 0x2D
127#define FLASH_OFFSET_PROTECT 0x02
wdenkbf9e3b32004-02-12 00:47:09 +0000128#define FLASH_OFFSET_USER_PROTECTION 0x85
129#define FLASH_OFFSET_INTEL_PROTECTION 0x81
wdenk5653fc32004-02-08 22:55:38 +0000130
Stefan Roese260421a2006-11-13 13:55:24 +0100131#define CFI_CMDSET_NONE 0
132#define CFI_CMDSET_INTEL_EXTENDED 1
133#define CFI_CMDSET_AMD_STANDARD 2
134#define CFI_CMDSET_INTEL_STANDARD 3
135#define CFI_CMDSET_AMD_EXTENDED 4
136#define CFI_CMDSET_MITSU_STANDARD 256
137#define CFI_CMDSET_MITSU_EXTENDED 257
138#define CFI_CMDSET_SST 258
wdenk5653fc32004-02-08 22:55:38 +0000139
wdenkf7d15722004-12-18 22:35:43 +0000140#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
141# undef FLASH_CMD_RESET
Stefan Roese260421a2006-11-13 13:55:24 +0100142# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
wdenkf7d15722004-12-18 22:35:43 +0000143#endif
144
wdenk5653fc32004-02-08 22:55:38 +0000145typedef union {
146 unsigned char c;
147 unsigned short w;
148 unsigned long l;
149 unsigned long long ll;
150} cfiword_t;
151
Stefan Roese260421a2006-11-13 13:55:24 +0100152#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
wdenk5653fc32004-02-08 22:55:38 +0000153
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100154static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
Wolfgang Denk92eb7292006-12-27 01:26:13 +0100155
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200156/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
157#ifdef CFG_MAX_FLASH_BANKS_DETECT
158static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
159flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
160#else
wdenk5653fc32004-02-08 22:55:38 +0000161static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200162flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
163#endif
wdenk5653fc32004-02-08 22:55:38 +0000164
Stefan Roese79b4cda2006-02-28 15:29:58 +0100165/*
166 * Check if chip width is defined. If not, start detecting with 8bit.
167 */
168#ifndef CFG_FLASH_CFI_WIDTH
169#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
170#endif
171
wdenk5653fc32004-02-08 22:55:38 +0000172typedef unsigned long flash_sect_t;
173
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100174static void flash_write8(u8 value, void *addr)
175{
176 __raw_writeb(value, addr);
177}
178
179static void flash_write16(u16 value, void *addr)
180{
181 __raw_writew(value, addr);
182}
183
184static void flash_write32(u32 value, void *addr)
185{
186 __raw_writel(value, addr);
187}
188
189static void flash_write64(u64 value, void *addr)
190{
191 /* No architectures currently implement __raw_writeq() */
192 *(volatile u64 *)addr = value;
193}
194
195static u8 flash_read8(void *addr)
196{
197 return __raw_readb(addr);
198}
199
200static u16 flash_read16(void *addr)
201{
202 return __raw_readw(addr);
203}
204
205static u32 flash_read32(void *addr)
206{
207 return __raw_readl(addr);
208}
209
210static u64 flash_read64(void *addr)
211{
212 /* No architectures currently implement __raw_readq() */
213 return *(volatile u64 *)addr;
214}
215
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200216/*-----------------------------------------------------------------------
217 */
Wolfgang Denk080bdb72005-10-05 01:51:29 +0200218#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200219static flash_info_t *flash_get_info(ulong base)
220{
221 int i;
222 flash_info_t * info = 0;
223
224 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
225 info = & flash_info[i];
226 if (info->size && info->start[0] <= base &&
227 base <= info->start[0] + info->size - 1)
228 break;
229 }
230
231 return i == CFG_MAX_FLASH_BANKS ? 0 : info;
232}
wdenk5653fc32004-02-08 22:55:38 +0000233#endif
234
wdenk5653fc32004-02-08 22:55:38 +0000235/*-----------------------------------------------------------------------
236 * create an address based on the offset and the port width
237 */
Haavard Skinnemoen30557932007-12-13 12:56:29 +0100238static inline uchar *
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100239flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000240{
wdenkbf9e3b32004-02-12 00:47:09 +0000241 return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
wdenk5653fc32004-02-08 22:55:38 +0000242}
wdenkbf9e3b32004-02-12 00:47:09 +0000243
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200244/*-----------------------------------------------------------------------
245 * make a proper sized command based on the port and chip widths
246 */
247static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
248{
249 int i;
250 uchar *cp = (uchar *) cmdbuf;
251
252#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
253 for (i = info->portwidth; i > 0; i--)
254#else
255 for (i = 1; i <= info->portwidth; i++)
256#endif
257 *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
258}
259
wdenkbf9e3b32004-02-12 00:47:09 +0000260#ifdef DEBUG
261/*-----------------------------------------------------------------------
262 * Debug support
263 */
Haavard Skinnemoen30557932007-12-13 12:56:29 +0100264static void print_longlong (char *str, unsigned long long data)
wdenkbf9e3b32004-02-12 00:47:09 +0000265{
266 int i;
267 char *cp;
268
269 cp = (unsigned char *) &data;
270 for (i = 0; i < 8; i++)
271 sprintf (&str[i * 2], "%2.2x", *cp++);
272}
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200273
wdenkbf9e3b32004-02-12 00:47:09 +0000274static void flash_printqry (flash_info_t * info, flash_sect_t sect)
275{
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100276 void *addr;
wdenkbf9e3b32004-02-12 00:47:09 +0000277 int x, y;
278
Wolfgang Denk47340a42005-10-09 00:25:58 +0200279 for (x = 0; x < 0x40; x += 16U / info->portwidth) {
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100280 addr = flash_make_addr (info, sect,
281 x + FLASH_OFFSET_CFI_RESP);
282 debug ("%p : ", addr);
wdenkbf9e3b32004-02-12 00:47:09 +0000283 for (y = 0; y < 16; y++) {
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100284 debug ("%2.2x ", flash_read8(addr + y));
wdenkbf9e3b32004-02-12 00:47:09 +0000285 }
286 debug (" ");
287 for (y = 0; y < 16; y++) {
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100288 unsigned char c = flash_read8(addr + y);
289 if (c >= 0x20 && c <= 0x7e) {
290 debug ("%c", c);
wdenkbf9e3b32004-02-12 00:47:09 +0000291 } else {
292 debug (".");
293 }
294 }
295 debug ("\n");
296 }
297}
wdenkbf9e3b32004-02-12 00:47:09 +0000298#endif
299
300
wdenk5653fc32004-02-08 22:55:38 +0000301/*-----------------------------------------------------------------------
302 * read a character at a port width address
303 */
Haavard Skinnemoen30557932007-12-13 12:56:29 +0100304static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000305{
306 uchar *cp;
wdenkbf9e3b32004-02-12 00:47:09 +0000307
308 cp = flash_make_addr (info, 0, offset);
Heiko Schocherd0b6e142007-01-19 18:05:26 +0100309#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
wdenkbf9e3b32004-02-12 00:47:09 +0000310 return (cp[0]);
311#else
wdenk5653fc32004-02-08 22:55:38 +0000312 return (cp[info->portwidth - 1]);
wdenkbf9e3b32004-02-12 00:47:09 +0000313#endif
wdenk5653fc32004-02-08 22:55:38 +0000314}
315
316/*-----------------------------------------------------------------------
317 * read a short word by swapping for ppc format.
318 */
Haavard Skinnemoen30557932007-12-13 12:56:29 +0100319static ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect,
320 uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000321{
wdenkbf9e3b32004-02-12 00:47:09 +0000322 uchar *addr;
323 ushort retval;
wdenk5653fc32004-02-08 22:55:38 +0000324
wdenkbf9e3b32004-02-12 00:47:09 +0000325#ifdef DEBUG
326 int x;
327#endif
328 addr = flash_make_addr (info, sect, offset);
wdenk5653fc32004-02-08 22:55:38 +0000329
wdenkbf9e3b32004-02-12 00:47:09 +0000330#ifdef DEBUG
331 debug ("ushort addr is at %p info->portwidth = %d\n", addr,
332 info->portwidth);
333 for (x = 0; x < 2 * info->portwidth; x++) {
334 debug ("addr[%x] = 0x%x\n", x, addr[x]);
335 }
336#endif
Heiko Schocherd0b6e142007-01-19 18:05:26 +0100337#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
wdenkbf9e3b32004-02-12 00:47:09 +0000338 retval = ((addr[(info->portwidth)] << 8) | addr[0]);
339#else
340 retval = ((addr[(2 * info->portwidth) - 1] << 8) |
341 addr[info->portwidth - 1]);
342#endif
343
344 debug ("retval = 0x%x\n", retval);
345 return retval;
wdenk5653fc32004-02-08 22:55:38 +0000346}
347
348/*-----------------------------------------------------------------------
Stefan Roese260421a2006-11-13 13:55:24 +0100349 * read a long word by picking the least significant byte of each maximum
wdenk5653fc32004-02-08 22:55:38 +0000350 * port size word. Swap for ppc format.
351 */
Haavard Skinnemoen30557932007-12-13 12:56:29 +0100352static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
353 uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000354{
wdenkbf9e3b32004-02-12 00:47:09 +0000355 uchar *addr;
356 ulong retval;
wdenk5653fc32004-02-08 22:55:38 +0000357
wdenkbf9e3b32004-02-12 00:47:09 +0000358#ifdef DEBUG
359 int x;
360#endif
361 addr = flash_make_addr (info, sect, offset);
362
363#ifdef DEBUG
364 debug ("long addr is at %p info->portwidth = %d\n", addr,
365 info->portwidth);
366 for (x = 0; x < 4 * info->portwidth; x++) {
367 debug ("addr[%x] = 0x%x\n", x, addr[x]);
368 }
369#endif
Heiko Schocherd0b6e142007-01-19 18:05:26 +0100370#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA)
wdenkbf9e3b32004-02-12 00:47:09 +0000371 retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100372 (addr[(2 * info->portwidth)]) |
373 (addr[(3 * info->portwidth)] << 8);
wdenkbf9e3b32004-02-12 00:47:09 +0000374#else
375 retval = (addr[(2 * info->portwidth) - 1] << 24) |
376 (addr[(info->portwidth) - 1] << 16) |
377 (addr[(4 * info->portwidth) - 1] << 8) |
378 addr[(3 * info->portwidth) - 1];
379#endif
380 return retval;
wdenk5653fc32004-02-08 22:55:38 +0000381}
382
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200383/*
384 * Write a proper sized command to the correct address
385 */
386static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
387 uint offset, uchar cmd)
388{
Stefan Roese79b4cda2006-02-28 15:29:58 +0100389
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100390 void *addr;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200391 cfiword_t cword;
392
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100393 addr = flash_make_addr (info, sect, offset);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200394 flash_make_cmd (info, cmd, &cword);
395 switch (info->portwidth) {
396 case FLASH_CFI_8BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100397 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200398 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100399 flash_write8(cword.c, addr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200400 break;
401 case FLASH_CFI_16BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100402 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200403 cmd, cword.w,
404 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100405 flash_write16(cword.w, addr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200406 break;
407 case FLASH_CFI_32BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100408 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200409 cmd, cword.l,
410 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100411 flash_write32(cword.l, addr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200412 break;
413 case FLASH_CFI_64BIT:
414#ifdef DEBUG
415 {
416 char str[20];
417
418 print_longlong (str, cword.ll);
419
420 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100421 addr, cmd, str,
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200422 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
423 }
424#endif
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100425 flash_write64(cword.ll, addr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200426 break;
427 }
428
429 /* Ensure all the instructions are fully finished */
430 sync();
431}
432
433static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
434{
435 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
436 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
437}
438
439/*-----------------------------------------------------------------------
440 */
441static int flash_isequal (flash_info_t * info, flash_sect_t sect,
442 uint offset, uchar cmd)
443{
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100444 void *addr;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200445 cfiword_t cword;
446 int retval;
447
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100448 addr = flash_make_addr (info, sect, offset);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200449 flash_make_cmd (info, cmd, &cword);
450
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100451 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200452 switch (info->portwidth) {
453 case FLASH_CFI_8BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100454 debug ("is= %x %x\n", flash_read8(addr), cword.c);
455 retval = (flash_read8(addr) == cword.c);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200456 break;
457 case FLASH_CFI_16BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100458 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
459 retval = (flash_read16(addr) == cword.w);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200460 break;
461 case FLASH_CFI_32BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100462 debug ("is= %8.8lx %8.8lx\n", flash_read32(addr), cword.l);
463 retval = (flash_read32(addr) == cword.l);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200464 break;
465 case FLASH_CFI_64BIT:
466#ifdef DEBUG
467 {
468 char str1[20];
469 char str2[20];
470
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100471 print_longlong (str1, flash_read64(addr));
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200472 print_longlong (str2, cword.ll);
473 debug ("is= %s %s\n", str1, str2);
474 }
475#endif
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100476 retval = (flash_read64(addr) == cword.ll);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200477 break;
478 default:
479 retval = 0;
480 break;
481 }
482 return retval;
483}
484
485/*-----------------------------------------------------------------------
486 */
487static int flash_isset (flash_info_t * info, flash_sect_t sect,
488 uint offset, uchar cmd)
489{
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100490 void *addr;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200491 cfiword_t cword;
492 int retval;
493
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100494 addr = flash_make_addr (info, sect, offset);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200495 flash_make_cmd (info, cmd, &cword);
496 switch (info->portwidth) {
497 case FLASH_CFI_8BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100498 retval = ((flash_read8(addr) & cword.c) == cword.c);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200499 break;
500 case FLASH_CFI_16BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100501 retval = ((flash_read16(addr) & cword.w) == cword.w);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200502 break;
503 case FLASH_CFI_32BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100504 retval = ((flash_read16(addr) & cword.l) == cword.l);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200505 break;
506 case FLASH_CFI_64BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100507 retval = ((flash_read64(addr) & cword.ll) == cword.ll);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200508 break;
509 default:
510 retval = 0;
511 break;
512 }
513 return retval;
514}
515
516/*-----------------------------------------------------------------------
517 */
518static int flash_toggle (flash_info_t * info, flash_sect_t sect,
519 uint offset, uchar cmd)
520{
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100521 void *addr;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200522 cfiword_t cword;
523 int retval;
524
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100525 addr = flash_make_addr (info, sect, offset);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200526 flash_make_cmd (info, cmd, &cword);
527 switch (info->portwidth) {
528 case FLASH_CFI_8BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100529 retval = ((flash_read8(addr) & cword.c) !=
530 (flash_read8(addr) & cword.c));
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200531 break;
532 case FLASH_CFI_16BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100533 retval = ((flash_read16(addr) & cword.w) !=
534 (flash_read16(addr) & cword.w));
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200535 break;
536 case FLASH_CFI_32BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100537 retval = ((flash_read32(addr) & cword.l) !=
538 (flash_read32(addr) & cword.l));
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200539 break;
540 case FLASH_CFI_64BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100541 retval = ((flash_read64(addr) & cword.ll) !=
542 (flash_read64(addr) & cword.ll));
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200543 break;
544 default:
545 retval = 0;
546 break;
547 }
548 return retval;
549}
550
551/*
552 * flash_is_busy - check to see if the flash is busy
553 *
554 * This routine checks the status of the chip and returns true if the
555 * chip is busy.
556 */
557static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
558{
559 int retval;
560
561 switch (info->vendor) {
562 case CFI_CMDSET_INTEL_STANDARD:
563 case CFI_CMDSET_INTEL_EXTENDED:
564 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
565 break;
566 case CFI_CMDSET_AMD_STANDARD:
567 case CFI_CMDSET_AMD_EXTENDED:
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100568#ifdef CONFIG_FLASH_CFI_LEGACY
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200569 case CFI_CMDSET_AMD_LEGACY:
570#endif
571 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
572 break;
573 default:
574 retval = 0;
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100575 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200576 debug ("flash_is_busy: %d\n", retval);
577 return retval;
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100578}
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200579
580/*-----------------------------------------------------------------------
581 * wait for XSR.7 to be set. Time out with an error if it does not.
582 * This routine does not set the flash to read-array mode.
583 */
584static int flash_status_check (flash_info_t * info, flash_sect_t sector,
585 ulong tout, char *prompt)
586{
587 ulong start;
588
589#if CFG_HZ != 1000
590 tout *= CFG_HZ/1000;
591#endif
592
593 /* Wait for command completion */
594 start = get_timer (0);
595 while (flash_is_busy (info, sector)) {
596 if (get_timer (start) > tout) {
597 printf ("Flash %s timeout at address %lx data %lx\n",
598 prompt, info->start[sector],
599 flash_read_long (info, sector, 0));
600 flash_write_cmd (info, sector, 0, info->cmd_reset);
601 return ERR_TIMOUT;
602 }
603 udelay (1); /* also triggers watchdog */
604 }
605 return ERR_OK;
606}
607
608/*-----------------------------------------------------------------------
609 * Wait for XSR.7 to be set, if it times out print an error, otherwise
610 * do a full status check.
611 *
612 * This routine sets the flash to read-array mode.
613 */
614static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
615 ulong tout, char *prompt)
616{
617 int retcode;
618
619 retcode = flash_status_check (info, sector, tout, prompt);
620 switch (info->vendor) {
621 case CFI_CMDSET_INTEL_EXTENDED:
622 case CFI_CMDSET_INTEL_STANDARD:
623 if ((retcode == ERR_OK)
624 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
625 retcode = ERR_INVAL;
626 printf ("Flash %s error at address %lx\n", prompt,
627 info->start[sector]);
628 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
629 FLASH_STATUS_PSLBS)) {
630 puts ("Command Sequence Error.\n");
631 } else if (flash_isset (info, sector, 0,
632 FLASH_STATUS_ECLBS)) {
633 puts ("Block Erase Error.\n");
634 retcode = ERR_NOT_ERASED;
635 } else if (flash_isset (info, sector, 0,
636 FLASH_STATUS_PSLBS)) {
637 puts ("Locking Error\n");
638 }
639 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
640 puts ("Block locked.\n");
641 retcode = ERR_PROTECTED;
642 }
643 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
644 puts ("Vpp Low Error.\n");
645 }
646 flash_write_cmd (info, sector, 0, info->cmd_reset);
647 break;
648 default:
649 break;
650 }
651 return retcode;
652}
653
654/*-----------------------------------------------------------------------
655 */
656static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
657{
658#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
659 unsigned short w;
660 unsigned int l;
661 unsigned long long ll;
662#endif
663
664 switch (info->portwidth) {
665 case FLASH_CFI_8BIT:
666 cword->c = c;
667 break;
668 case FLASH_CFI_16BIT:
669#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
670 w = c;
671 w <<= 8;
672 cword->w = (cword->w >> 8) | w;
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100673#else
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200674 cword->w = (cword->w << 8) | c;
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100675#endif
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200676 break;
677 case FLASH_CFI_32BIT:
678#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
679 l = c;
680 l <<= 24;
681 cword->l = (cword->l >> 8) | l;
682#else
683 cword->l = (cword->l << 8) | c;
Stefan Roese2662b402006-04-01 13:41:03 +0200684#endif
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200685 break;
686 case FLASH_CFI_64BIT:
687#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA)
688 ll = c;
689 ll <<= 56;
690 cword->ll = (cword->ll >> 8) | ll;
691#else
692 cword->ll = (cword->ll << 8) | c;
693#endif
694 break;
wdenk5653fc32004-02-08 22:55:38 +0000695 }
wdenk5653fc32004-02-08 22:55:38 +0000696}
697
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200698/* loop through the sectors from the highest address when the passed
699 * address is greater or equal to the sector address we have a match
wdenk5653fc32004-02-08 22:55:38 +0000700 */
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200701static flash_sect_t find_sector (flash_info_t * info, ulong addr)
wdenk7680c142005-05-16 15:23:22 +0000702{
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200703 flash_sect_t sector;
wdenk7680c142005-05-16 15:23:22 +0000704
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200705 for (sector = info->sector_count - 1; sector >= 0; sector--) {
706 if (addr >= info->start[sector])
wdenk7680c142005-05-16 15:23:22 +0000707 break;
708 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200709 return sector;
wdenk7680c142005-05-16 15:23:22 +0000710}
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200711
712/*-----------------------------------------------------------------------
713 */
714static int flash_write_cfiword (flash_info_t * info, ulong dest,
715 cfiword_t cword)
716{
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100717 void *ctladdr;
718 void *dstaddr;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200719 int flag;
720
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100721 ctladdr = flash_make_addr (info, 0, 0);
722 dstaddr = (uchar *)dest;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200723
724 /* Check if Flash is (sufficiently) erased */
725 switch (info->portwidth) {
726 case FLASH_CFI_8BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100727 flag = ((flash_read8(dstaddr) & cword.c) == cword.c);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200728 break;
729 case FLASH_CFI_16BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100730 flag = ((flash_read16(dstaddr) & cword.w) == cword.w);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200731 break;
732 case FLASH_CFI_32BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100733 flag = ((flash_read32(dstaddr) & cword.l) == cword.l);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200734 break;
735 case FLASH_CFI_64BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100736 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200737 break;
738 default:
739 return 2;
740 }
741 if (!flag)
742 return 2;
743
744 /* Disable interrupts which might cause a timeout here */
745 flag = disable_interrupts ();
746
747 switch (info->vendor) {
748 case CFI_CMDSET_INTEL_EXTENDED:
749 case CFI_CMDSET_INTEL_STANDARD:
750 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
751 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
752 break;
753 case CFI_CMDSET_AMD_EXTENDED:
754 case CFI_CMDSET_AMD_STANDARD:
755#ifdef CONFIG_FLASH_CFI_LEGACY
756 case CFI_CMDSET_AMD_LEGACY:
Wolfgang Denk080bdb72005-10-05 01:51:29 +0200757#endif
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200758 flash_unlock_seq (info, 0);
759 flash_write_cmd (info, 0, info->addr_unlock1, AMD_CMD_WRITE);
760 break;
761 }
762
763 switch (info->portwidth) {
764 case FLASH_CFI_8BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100765 flash_write8(cword.c, dstaddr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200766 break;
767 case FLASH_CFI_16BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100768 flash_write16(cword.w, dstaddr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200769 break;
770 case FLASH_CFI_32BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100771 flash_write32(cword.l, dstaddr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200772 break;
773 case FLASH_CFI_64BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100774 flash_write64(cword.ll, dstaddr);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200775 break;
776 }
777
778 /* re-enable interrupts if necessary */
779 if (flag)
780 enable_interrupts ();
781
782 return flash_full_status_check (info, find_sector (info, dest),
783 info->write_tout, "write");
784}
785
786#ifdef CFG_FLASH_USE_BUFFER_WRITE
787
788static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
789 int len)
790{
791 flash_sect_t sector;
792 int cnt;
793 int retcode;
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100794 void *src = cp;
795 void *dst = (void *)dest;
796
797 sector = find_sector (info, dest);
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200798
799 switch (info->vendor) {
800 case CFI_CMDSET_INTEL_STANDARD:
801 case CFI_CMDSET_INTEL_EXTENDED:
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200802 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
803 flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
804 retcode = flash_status_check (info, sector,
805 info->buffer_write_tout,
806 "write to buffer");
807 if (retcode == ERR_OK) {
808 /* reduce the number of loops by the width of
809 * the port */
810 switch (info->portwidth) {
811 case FLASH_CFI_8BIT:
812 cnt = len;
813 break;
814 case FLASH_CFI_16BIT:
815 cnt = len >> 1;
816 break;
817 case FLASH_CFI_32BIT:
818 cnt = len >> 2;
819 break;
820 case FLASH_CFI_64BIT:
821 cnt = len >> 3;
822 break;
823 default:
824 return ERR_INVAL;
825 break;
826 }
827 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
828 while (cnt-- > 0) {
829 switch (info->portwidth) {
830 case FLASH_CFI_8BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100831 flash_write8(flash_read8(src), dst);
832 src += 1, dst += 1;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200833 break;
834 case FLASH_CFI_16BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100835 flash_write16(flash_read16(src), dst);
836 src += 2, dst += 2;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200837 break;
838 case FLASH_CFI_32BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100839 flash_write32(flash_read32(src), dst);
840 src += 4, dst += 4;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200841 break;
842 case FLASH_CFI_64BIT:
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100843 flash_write64(flash_read64(src), dst);
844 src += 8, dst += 8;
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200845 break;
846 default:
847 return ERR_INVAL;
848 break;
849 }
850 }
851 flash_write_cmd (info, sector, 0,
852 FLASH_CMD_WRITE_BUFFER_CONFIRM);
853 retcode = flash_full_status_check (
854 info, sector, info->buffer_write_tout,
855 "buffer write");
856 }
857 return retcode;
858
859 case CFI_CMDSET_AMD_STANDARD:
860 case CFI_CMDSET_AMD_EXTENDED:
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200861 flash_unlock_seq(info,0);
862 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_TO_BUFFER);
863
864 switch (info->portwidth) {
865 case FLASH_CFI_8BIT:
866 cnt = len;
867 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100868 while (cnt-- > 0) {
869 flash_write8(flash_read8(src), dst);
870 src += 1, dst += 1;
871 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200872 break;
873 case FLASH_CFI_16BIT:
874 cnt = len >> 1;
875 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100876 while (cnt-- > 0) {
877 flash_write16(flash_read16(src), dst);
878 src += 2, dst += 2;
879 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200880 break;
881 case FLASH_CFI_32BIT:
882 cnt = len >> 2;
883 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100884 while (cnt-- > 0) {
885 flash_write32(flash_read32(src), dst);
886 src += 4, dst += 4;
887 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200888 break;
889 case FLASH_CFI_64BIT:
890 cnt = len >> 3;
891 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
Haavard Skinnemoencdbaefb2007-12-13 12:56:32 +0100892 while (cnt-- > 0) {
893 flash_write64(flash_read64(src), dst);
894 src += 8, dst += 8;
895 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +0200896 break;
897 default:
898 return ERR_INVAL;
899 }
900
901 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
902 retcode = flash_full_status_check (info, sector,
903 info->buffer_write_tout,
904 "buffer write");
905 return retcode;
906
907 default:
908 debug ("Unknown Command Set\n");
909 return ERR_INVAL;
910 }
911}
912#endif /* CFG_FLASH_USE_BUFFER_WRITE */
913
wdenk7680c142005-05-16 15:23:22 +0000914
915/*-----------------------------------------------------------------------
916 */
wdenkbf9e3b32004-02-12 00:47:09 +0000917int flash_erase (flash_info_t * info, int s_first, int s_last)
wdenk5653fc32004-02-08 22:55:38 +0000918{
919 int rcode = 0;
920 int prot;
921 flash_sect_t sect;
922
wdenkbf9e3b32004-02-12 00:47:09 +0000923 if (info->flash_id != FLASH_MAN_CFI) {
wdenk4b9206e2004-03-23 22:14:11 +0000924 puts ("Can't erase unknown flash type - aborted\n");
wdenk5653fc32004-02-08 22:55:38 +0000925 return 1;
926 }
927 if ((s_first < 0) || (s_first > s_last)) {
wdenk4b9206e2004-03-23 22:14:11 +0000928 puts ("- no sectors to erase\n");
wdenk5653fc32004-02-08 22:55:38 +0000929 return 1;
930 }
931
932 prot = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000933 for (sect = s_first; sect <= s_last; ++sect) {
wdenk5653fc32004-02-08 22:55:38 +0000934 if (info->protect[sect]) {
935 prot++;
936 }
937 }
938 if (prot) {
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100939 printf ("- Warning: %d protected sectors will not be erased!\n",
940 prot);
wdenk5653fc32004-02-08 22:55:38 +0000941 } else {
wdenk4b9206e2004-03-23 22:14:11 +0000942 putc ('\n');
wdenk5653fc32004-02-08 22:55:38 +0000943 }
944
945
wdenkbf9e3b32004-02-12 00:47:09 +0000946 for (sect = s_first; sect <= s_last; sect++) {
wdenk5653fc32004-02-08 22:55:38 +0000947 if (info->protect[sect] == 0) { /* not protected */
wdenkbf9e3b32004-02-12 00:47:09 +0000948 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +0000949 case CFI_CMDSET_INTEL_STANDARD:
950 case CFI_CMDSET_INTEL_EXTENDED:
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100951 flash_write_cmd (info, sect, 0,
952 FLASH_CMD_CLEAR_STATUS);
953 flash_write_cmd (info, sect, 0,
954 FLASH_CMD_BLOCK_ERASE);
955 flash_write_cmd (info, sect, 0,
956 FLASH_CMD_ERASE_CONFIRM);
wdenk5653fc32004-02-08 22:55:38 +0000957 break;
958 case CFI_CMDSET_AMD_STANDARD:
959 case CFI_CMDSET_AMD_EXTENDED:
wdenkbf9e3b32004-02-12 00:47:09 +0000960 flash_unlock_seq (info, sect);
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100961 flash_write_cmd (info, sect,
962 info->addr_unlock1,
963 AMD_CMD_ERASE_START);
wdenkbf9e3b32004-02-12 00:47:09 +0000964 flash_unlock_seq (info, sect);
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100965 flash_write_cmd (info, sect, 0,
966 AMD_CMD_ERASE_SECTOR);
wdenk5653fc32004-02-08 22:55:38 +0000967 break;
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100968#ifdef CONFIG_FLASH_CFI_LEGACY
969 case CFI_CMDSET_AMD_LEGACY:
970 flash_unlock_seq (info, 0);
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100971 flash_write_cmd (info, 0, info->addr_unlock1,
972 AMD_CMD_ERASE_START);
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100973 flash_unlock_seq (info, 0);
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +0100974 flash_write_cmd (info, sect, 0,
975 AMD_CMD_ERASE_SECTOR);
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100976 break;
977#endif
wdenk5653fc32004-02-08 22:55:38 +0000978 default:
wdenkbf9e3b32004-02-12 00:47:09 +0000979 debug ("Unkown flash vendor %d\n",
980 info->vendor);
wdenk5653fc32004-02-08 22:55:38 +0000981 break;
982 }
983
wdenkbf9e3b32004-02-12 00:47:09 +0000984 if (flash_full_status_check
985 (info, sect, info->erase_blk_tout, "erase")) {
wdenk5653fc32004-02-08 22:55:38 +0000986 rcode = 1;
987 } else
wdenk4b9206e2004-03-23 22:14:11 +0000988 putc ('.');
wdenk5653fc32004-02-08 22:55:38 +0000989 }
990 }
wdenk4b9206e2004-03-23 22:14:11 +0000991 puts (" done\n");
wdenk5653fc32004-02-08 22:55:38 +0000992 return rcode;
993}
994
995/*-----------------------------------------------------------------------
996 */
wdenkbf9e3b32004-02-12 00:47:09 +0000997void flash_print_info (flash_info_t * info)
wdenk5653fc32004-02-08 22:55:38 +0000998{
999 int i;
1000
1001 if (info->flash_id != FLASH_MAN_CFI) {
wdenk4b9206e2004-03-23 22:14:11 +00001002 puts ("missing or unknown FLASH type\n");
wdenk5653fc32004-02-08 22:55:38 +00001003 return;
1004 }
1005
Michael Schwingen81b20cc2007-12-07 23:35:02 +01001006 printf ("%s FLASH (%d x %d)",
1007 info->name,
wdenkbf9e3b32004-02-12 00:47:09 +00001008 (info->portwidth << 3), (info->chipwidth << 3));
Michael Schwingen81b20cc2007-12-07 23:35:02 +01001009 if (info->size < 1024*1024)
1010 printf (" Size: %ld kB in %d Sectors\n",
1011 info->size >> 10, info->sector_count);
1012 else
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001013 printf (" Size: %ld MB in %d Sectors\n",
1014 info->size >> 20, info->sector_count);
Stefan Roese260421a2006-11-13 13:55:24 +01001015 printf (" ");
1016 switch (info->vendor) {
1017 case CFI_CMDSET_INTEL_STANDARD:
1018 printf ("Intel Standard");
1019 break;
1020 case CFI_CMDSET_INTEL_EXTENDED:
1021 printf ("Intel Extended");
1022 break;
1023 case CFI_CMDSET_AMD_STANDARD:
1024 printf ("AMD Standard");
1025 break;
1026 case CFI_CMDSET_AMD_EXTENDED:
1027 printf ("AMD Extended");
1028 break;
Michael Schwingen81b20cc2007-12-07 23:35:02 +01001029#ifdef CONFIG_FLASH_CFI_LEGACY
1030 case CFI_CMDSET_AMD_LEGACY:
1031 printf ("AMD Legacy");
1032 break;
1033#endif
Stefan Roese260421a2006-11-13 13:55:24 +01001034 default:
1035 printf ("Unknown (%d)", info->vendor);
1036 break;
1037 }
1038 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X",
1039 info->manufacturer_id, info->device_id);
1040 if (info->device_id == 0x7E) {
1041 printf("%04X", info->device_id2);
1042 }
1043 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
wdenk028ab6b2004-02-23 23:54:43 +00001044 info->erase_blk_tout,
Stefan Roese260421a2006-11-13 13:55:24 +01001045 info->write_tout);
1046 if (info->buffer_size > 1) {
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001047 printf (" Buffer write timeout: %ld ms, "
1048 "buffer size: %d bytes\n",
wdenk028ab6b2004-02-23 23:54:43 +00001049 info->buffer_write_tout,
1050 info->buffer_size);
Stefan Roese260421a2006-11-13 13:55:24 +01001051 }
wdenk5653fc32004-02-08 22:55:38 +00001052
Stefan Roese260421a2006-11-13 13:55:24 +01001053 puts ("\n Sector Start Addresses:");
wdenkbf9e3b32004-02-12 00:47:09 +00001054 for (i = 0; i < info->sector_count; ++i) {
Stefan Roese260421a2006-11-13 13:55:24 +01001055 if ((i % 5) == 0)
1056 printf ("\n");
wdenk5653fc32004-02-08 22:55:38 +00001057#ifdef CFG_FLASH_EMPTY_INFO
1058 int k;
1059 int size;
1060 int erased;
1061 volatile unsigned long *flash;
1062
1063 /*
1064 * Check if whole sector is erased
1065 */
wdenkbf9e3b32004-02-12 00:47:09 +00001066 if (i != (info->sector_count - 1))
1067 size = info->start[i + 1] - info->start[i];
wdenk5653fc32004-02-08 22:55:38 +00001068 else
wdenkbf9e3b32004-02-12 00:47:09 +00001069 size = info->start[0] + info->size - info->start[i];
wdenk5653fc32004-02-08 22:55:38 +00001070 erased = 1;
wdenkbf9e3b32004-02-12 00:47:09 +00001071 flash = (volatile unsigned long *) info->start[i];
1072 size = size >> 2; /* divide by 4 for longword access */
1073 for (k = 0; k < size; k++) {
1074 if (*flash++ != 0xffffffff) {
1075 erased = 0;
1076 break;
1077 }
1078 }
wdenk5653fc32004-02-08 22:55:38 +00001079
wdenk5653fc32004-02-08 22:55:38 +00001080 /* print empty and read-only info */
Stefan Roese260421a2006-11-13 13:55:24 +01001081 printf (" %08lX %c %s ",
wdenk5653fc32004-02-08 22:55:38 +00001082 info->start[i],
Stefan Roese260421a2006-11-13 13:55:24 +01001083 erased ? 'E' : ' ',
1084 info->protect[i] ? "RO" : " ");
Wolfgang Denkb63de2c2005-09-25 00:23:05 +02001085#else /* ! CFG_FLASH_EMPTY_INFO */
Stefan Roese260421a2006-11-13 13:55:24 +01001086 printf (" %08lX %s ",
1087 info->start[i],
1088 info->protect[i] ? "RO" : " ");
wdenk5653fc32004-02-08 22:55:38 +00001089#endif
1090 }
wdenk4b9206e2004-03-23 22:14:11 +00001091 putc ('\n');
wdenk5653fc32004-02-08 22:55:38 +00001092 return;
1093}
1094
1095/*-----------------------------------------------------------------------
1096 * Copy memory to flash, returns:
1097 * 0 - OK
1098 * 1 - write timeout
1099 * 2 - Flash not erased
1100 */
wdenkbf9e3b32004-02-12 00:47:09 +00001101int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
wdenk5653fc32004-02-08 22:55:38 +00001102{
1103 ulong wp;
1104 ulong cp;
1105 int aln;
1106 cfiword_t cword;
1107 int i, rc;
1108
wdenkbf9e3b32004-02-12 00:47:09 +00001109#ifdef CFG_FLASH_USE_BUFFER_WRITE
1110 int buffered_size;
1111#endif
wdenkbf9e3b32004-02-12 00:47:09 +00001112 /* get lower aligned address */
wdenk5653fc32004-02-08 22:55:38 +00001113 /* get lower aligned address */
1114 wp = (addr & ~(info->portwidth - 1));
1115
1116 /* handle unaligned start */
wdenkbf9e3b32004-02-12 00:47:09 +00001117 if ((aln = addr - wp) != 0) {
wdenk5653fc32004-02-08 22:55:38 +00001118 cword.l = 0;
1119 cp = wp;
wdenkbf9e3b32004-02-12 00:47:09 +00001120 for (i = 0; i < aln; ++i, ++cp)
1121 flash_add_byte (info, &cword, (*(uchar *) cp));
wdenk5653fc32004-02-08 22:55:38 +00001122
wdenkbf9e3b32004-02-12 00:47:09 +00001123 for (; (i < info->portwidth) && (cnt > 0); i++) {
1124 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +00001125 cnt--;
1126 cp++;
1127 }
wdenkbf9e3b32004-02-12 00:47:09 +00001128 for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
1129 flash_add_byte (info, &cword, (*(uchar *) cp));
1130 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
wdenk5653fc32004-02-08 22:55:38 +00001131 return rc;
1132 wp = cp;
1133 }
1134
wdenkbf9e3b32004-02-12 00:47:09 +00001135 /* handle the aligned part */
wdenk5653fc32004-02-08 22:55:38 +00001136#ifdef CFG_FLASH_USE_BUFFER_WRITE
wdenkbf9e3b32004-02-12 00:47:09 +00001137 buffered_size = (info->portwidth / info->chipwidth);
1138 buffered_size *= info->buffer_size;
1139 while (cnt >= info->portwidth) {
Stefan Roese79b4cda2006-02-28 15:29:58 +01001140 /* prohibit buffer write when buffer_size is 1 */
1141 if (info->buffer_size == 1) {
1142 cword.l = 0;
1143 for (i = 0; i < info->portwidth; i++)
1144 flash_add_byte (info, &cword, *src++);
1145 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1146 return rc;
1147 wp += info->portwidth;
1148 cnt -= info->portwidth;
1149 continue;
1150 }
1151
1152 /* write buffer until next buffered_size aligned boundary */
1153 i = buffered_size - (wp % buffered_size);
1154 if (i > cnt)
1155 i = cnt;
wdenkbf9e3b32004-02-12 00:47:09 +00001156 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
wdenk5653fc32004-02-08 22:55:38 +00001157 return rc;
Wolfgang Denk8d4ba3d2005-08-12 22:35:59 +02001158 i -= i & (info->portwidth - 1);
wdenk5653fc32004-02-08 22:55:38 +00001159 wp += i;
1160 src += i;
wdenkbf9e3b32004-02-12 00:47:09 +00001161 cnt -= i;
wdenk5653fc32004-02-08 22:55:38 +00001162 }
1163#else
wdenkbf9e3b32004-02-12 00:47:09 +00001164 while (cnt >= info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001165 cword.l = 0;
wdenkbf9e3b32004-02-12 00:47:09 +00001166 for (i = 0; i < info->portwidth; i++) {
1167 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +00001168 }
wdenkbf9e3b32004-02-12 00:47:09 +00001169 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
wdenk5653fc32004-02-08 22:55:38 +00001170 return rc;
1171 wp += info->portwidth;
1172 cnt -= info->portwidth;
1173 }
1174#endif /* CFG_FLASH_USE_BUFFER_WRITE */
1175 if (cnt == 0) {
1176 return (0);
1177 }
1178
1179 /*
1180 * handle unaligned tail bytes
1181 */
1182 cword.l = 0;
wdenkbf9e3b32004-02-12 00:47:09 +00001183 for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
1184 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +00001185 --cnt;
1186 }
wdenkbf9e3b32004-02-12 00:47:09 +00001187 for (; i < info->portwidth; ++i, ++cp) {
1188 flash_add_byte (info, &cword, (*(uchar *) cp));
wdenk5653fc32004-02-08 22:55:38 +00001189 }
1190
wdenkbf9e3b32004-02-12 00:47:09 +00001191 return flash_write_cfiword (info, wp, cword);
wdenk5653fc32004-02-08 22:55:38 +00001192}
1193
1194/*-----------------------------------------------------------------------
1195 */
1196#ifdef CFG_FLASH_PROTECTION
1197
wdenkbf9e3b32004-02-12 00:47:09 +00001198int flash_real_protect (flash_info_t * info, long sector, int prot)
wdenk5653fc32004-02-08 22:55:38 +00001199{
1200 int retcode = 0;
1201
wdenkbf9e3b32004-02-12 00:47:09 +00001202 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1203 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1204 if (prot)
1205 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
wdenk5653fc32004-02-08 22:55:38 +00001206 else
wdenkbf9e3b32004-02-12 00:47:09 +00001207 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
wdenk5653fc32004-02-08 22:55:38 +00001208
wdenkbf9e3b32004-02-12 00:47:09 +00001209 if ((retcode =
1210 flash_full_status_check (info, sector, info->erase_blk_tout,
1211 prot ? "protect" : "unprotect")) == 0) {
wdenk5653fc32004-02-08 22:55:38 +00001212
1213 info->protect[sector] = prot;
Stefan Roese2662b402006-04-01 13:41:03 +02001214
1215 /*
1216 * On some of Intel's flash chips (marked via legacy_unlock)
1217 * unprotect unprotects all locking.
1218 */
1219 if ((prot == 0) && (info->legacy_unlock)) {
wdenk5653fc32004-02-08 22:55:38 +00001220 flash_sect_t i;
wdenkbf9e3b32004-02-12 00:47:09 +00001221
1222 for (i = 0; i < info->sector_count; i++) {
1223 if (info->protect[i])
1224 flash_real_protect (info, i, 1);
wdenk5653fc32004-02-08 22:55:38 +00001225 }
1226 }
1227 }
wdenk5653fc32004-02-08 22:55:38 +00001228 return retcode;
wdenkbf9e3b32004-02-12 00:47:09 +00001229}
1230
wdenk5653fc32004-02-08 22:55:38 +00001231/*-----------------------------------------------------------------------
1232 * flash_read_user_serial - read the OneTimeProgramming cells
1233 */
wdenkbf9e3b32004-02-12 00:47:09 +00001234void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
1235 int len)
wdenk5653fc32004-02-08 22:55:38 +00001236{
wdenkbf9e3b32004-02-12 00:47:09 +00001237 uchar *src;
1238 uchar *dst;
wdenk5653fc32004-02-08 22:55:38 +00001239
1240 dst = buffer;
wdenkbf9e3b32004-02-12 00:47:09 +00001241 src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
1242 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1243 memcpy (dst, src + offset, len);
Wolfgang Denkdb421e62005-09-25 16:41:22 +02001244 flash_write_cmd (info, 0, 0, info->cmd_reset);
wdenk5653fc32004-02-08 22:55:38 +00001245}
wdenkbf9e3b32004-02-12 00:47:09 +00001246
wdenk5653fc32004-02-08 22:55:38 +00001247/*
1248 * flash_read_factory_serial - read the device Id from the protection area
1249 */
wdenkbf9e3b32004-02-12 00:47:09 +00001250void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
1251 int len)
wdenk5653fc32004-02-08 22:55:38 +00001252{
wdenkbf9e3b32004-02-12 00:47:09 +00001253 uchar *src;
wdenkcd37d9e2004-02-10 00:03:41 +00001254
wdenkbf9e3b32004-02-12 00:47:09 +00001255 src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
1256 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1257 memcpy (buffer, src + offset, len);
Wolfgang Denkdb421e62005-09-25 16:41:22 +02001258 flash_write_cmd (info, 0, 0, info->cmd_reset);
wdenk5653fc32004-02-08 22:55:38 +00001259}
1260
1261#endif /* CFG_FLASH_PROTECTION */
1262
wdenk5653fc32004-02-08 22:55:38 +00001263
1264/*-----------------------------------------------------------------------
Stefan Roese260421a2006-11-13 13:55:24 +01001265 * read jedec ids from device and set corresponding fields in info struct
1266 *
1267 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1268 *
1269*/
1270static void flash_read_jedec_ids (flash_info_t * info)
1271{
1272 info->manufacturer_id = 0;
1273 info->device_id = 0;
1274 info->device_id2 = 0;
1275
1276 switch (info->vendor) {
1277 case CFI_CMDSET_INTEL_STANDARD:
1278 case CFI_CMDSET_INTEL_EXTENDED:
1279 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1280 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1281 udelay(1000); /* some flash are slow to respond */
1282 info->manufacturer_id = flash_read_uchar (info,
1283 FLASH_OFFSET_MANUFACTURER_ID);
1284 info->device_id = flash_read_uchar (info,
1285 FLASH_OFFSET_DEVICE_ID);
1286 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1287 break;
1288 case CFI_CMDSET_AMD_STANDARD:
1289 case CFI_CMDSET_AMD_EXTENDED:
1290 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1291 flash_unlock_seq(info, 0);
Michael Schwingen81b20cc2007-12-07 23:35:02 +01001292 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
Stefan Roese260421a2006-11-13 13:55:24 +01001293 udelay(1000); /* some flash are slow to respond */
1294 info->manufacturer_id = flash_read_uchar (info,
1295 FLASH_OFFSET_MANUFACTURER_ID);
1296 info->device_id = flash_read_uchar (info,
1297 FLASH_OFFSET_DEVICE_ID);
1298 if (info->device_id == 0x7E) {
1299 /* AMD 3-byte (expanded) device ids */
1300 info->device_id2 = flash_read_uchar (info,
1301 FLASH_OFFSET_DEVICE_ID2);
1302 info->device_id2 <<= 8;
1303 info->device_id2 |= flash_read_uchar (info,
1304 FLASH_OFFSET_DEVICE_ID3);
1305 }
1306 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1307 break;
1308 default:
1309 break;
1310 }
1311}
1312
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001313#ifdef CONFIG_FLASH_CFI_LEGACY
1314/*-----------------------------------------------------------------------
1315 * Call board code to request info about non-CFI flash.
1316 * board_flash_get_legacy needs to fill in at least:
1317 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
1318 */
1319static int flash_detect_legacy(ulong base, int banknum)
1320{
1321 flash_info_t *info = &flash_info[banknum];
1322
1323 if (board_flash_get_legacy(base, banknum, info)) {
1324 /* board code may have filled info completely. If not, we
1325 use JEDEC ID probing. */
1326 if (!info->vendor) {
1327 int modes[] = {
1328 CFI_CMDSET_AMD_STANDARD,
1329 CFI_CMDSET_INTEL_STANDARD
1330 };
1331 int i;
1332
1333 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
1334 info->vendor = modes[i];
1335 info->start[0] = base;
1336 if (info->portwidth == FLASH_CFI_8BIT
1337 && info->interface == FLASH_CFI_X8X16) {
1338 info->addr_unlock1 = 0x2AAA;
1339 info->addr_unlock2 = 0x5555;
1340 } else {
1341 info->addr_unlock1 = 0x5555;
1342 info->addr_unlock2 = 0x2AAA;
1343 }
1344 flash_read_jedec_ids(info);
1345 debug("JEDEC PROBE: ID %x %x %x\n",
1346 info->manufacturer_id,
1347 info->device_id,
1348 info->device_id2);
1349 if (jedec_flash_match(info, base))
1350 break;
1351 }
1352 }
1353
1354 switch(info->vendor) {
1355 case CFI_CMDSET_INTEL_STANDARD:
1356 case CFI_CMDSET_INTEL_EXTENDED:
1357 info->cmd_reset = FLASH_CMD_RESET;
1358 break;
1359 case CFI_CMDSET_AMD_STANDARD:
1360 case CFI_CMDSET_AMD_EXTENDED:
1361 case CFI_CMDSET_AMD_LEGACY:
1362 info->cmd_reset = AMD_CMD_RESET;
1363 break;
1364 }
1365 info->flash_id = FLASH_MAN_CFI;
1366 return 1;
1367 }
1368 return 0; /* use CFI */
1369}
1370#else
1371static inline int flash_detect_legacy(ulong base, int banknum)
1372{
1373 return 0; /* use CFI */
1374}
1375#endif
1376
Stefan Roese260421a2006-11-13 13:55:24 +01001377/*-----------------------------------------------------------------------
wdenk5653fc32004-02-08 22:55:38 +00001378 * detect if flash is compatible with the Common Flash Interface (CFI)
1379 * http://www.jedec.org/download/search/jesd68.pdf
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001380 */
1381static int __flash_detect_cfi (flash_info_t * info)
wdenk5653fc32004-02-08 22:55:38 +00001382{
Wolfgang Denk92eb7292006-12-27 01:26:13 +01001383 int cfi_offset;
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001384
1385 flash_write_cmd (info, 0, 0, info->cmd_reset);
1386 for (cfi_offset=0;
1387 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);
1388 cfi_offset++) {
1389 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
1390 FLASH_CMD_CFI);
1391 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
1392 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
1393 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
1394 info->interface = flash_read_ushort (info, 0,
1395 FLASH_OFFSET_INTERFACE);
1396 info->cfi_offset = flash_offset_cfi[cfi_offset];
1397 debug ("device interface is %d\n",
1398 info->interface);
1399 debug ("found port %d chip %d ",
1400 info->portwidth, info->chipwidth);
1401 debug ("port %d bits chip %d bits\n",
1402 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1403 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1404
1405 /* calculate command offsets as in the Linux driver */
1406 info->addr_unlock1 = 0x555;
1407 info->addr_unlock2 = 0x2aa;
1408
1409 /*
1410 * modify the unlock address if we are
1411 * in compatibility mode
1412 */
1413 if ( /* x8/x16 in x8 mode */
1414 ((info->chipwidth == FLASH_CFI_BY8) &&
1415 (info->interface == FLASH_CFI_X8X16)) ||
1416 /* x16/x32 in x16 mode */
1417 ((info->chipwidth == FLASH_CFI_BY16) &&
1418 (info->interface == FLASH_CFI_X16X32)))
1419 {
1420 info->addr_unlock1 = 0xaaa;
1421 info->addr_unlock2 = 0x555;
1422 }
1423
1424 info->name = "CFI conformant";
1425 return 1;
1426 }
1427 }
1428
1429 return 0;
1430}
1431
1432static int flash_detect_cfi (flash_info_t * info)
1433{
wdenkbf9e3b32004-02-12 00:47:09 +00001434 debug ("flash detect cfi\n");
wdenk5653fc32004-02-08 22:55:38 +00001435
Stefan Roese79b4cda2006-02-28 15:29:58 +01001436 for (info->portwidth = CFG_FLASH_CFI_WIDTH;
wdenkbf9e3b32004-02-12 00:47:09 +00001437 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1438 for (info->chipwidth = FLASH_CFI_BY8;
1439 info->chipwidth <= info->portwidth;
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001440 info->chipwidth <<= 1)
1441 if (__flash_detect_cfi(info))
1442 return 1;
wdenk5653fc32004-02-08 22:55:38 +00001443 }
wdenkbf9e3b32004-02-12 00:47:09 +00001444 debug ("not found\n");
wdenk5653fc32004-02-08 22:55:38 +00001445 return 0;
1446}
wdenkbf9e3b32004-02-12 00:47:09 +00001447
wdenk5653fc32004-02-08 22:55:38 +00001448/*
1449 * The following code cannot be run from FLASH!
1450 *
1451 */
Marian Balakowicze6f2e902005-10-11 19:09:42 +02001452ulong flash_get_size (ulong base, int banknum)
wdenk5653fc32004-02-08 22:55:38 +00001453{
wdenkbf9e3b32004-02-12 00:47:09 +00001454 flash_info_t *info = &flash_info[banknum];
wdenk5653fc32004-02-08 22:55:38 +00001455 int i, j;
1456 flash_sect_t sect_cnt;
1457 unsigned long sector;
1458 unsigned long tmp;
1459 int size_ratio;
1460 uchar num_erase_regions;
wdenkbf9e3b32004-02-12 00:47:09 +00001461 int erase_region_size;
1462 int erase_region_count;
Stefan Roese260421a2006-11-13 13:55:24 +01001463 int geometry_reversed = 0;
1464
1465 info->ext_addr = 0;
1466 info->cfi_version = 0;
Stefan Roese2662b402006-04-01 13:41:03 +02001467#ifdef CFG_FLASH_PROTECTION
Stefan Roese2662b402006-04-01 13:41:03 +02001468 info->legacy_unlock = 0;
1469#endif
wdenk5653fc32004-02-08 22:55:38 +00001470
1471 info->start[0] = base;
1472
wdenkbf9e3b32004-02-12 00:47:09 +00001473 if (flash_detect_cfi (info)) {
Stefan Roese260421a2006-11-13 13:55:24 +01001474 info->vendor = flash_read_ushort (info, 0,
1475 FLASH_OFFSET_PRIMARY_VENDOR);
1476 flash_read_jedec_ids (info);
Stefano Babicd784fdb2006-12-12 00:22:42 +01001477 flash_write_cmd (info, 0, info->cfi_offset, FLASH_CMD_CFI);
Stefan Roese260421a2006-11-13 13:55:24 +01001478 num_erase_regions = flash_read_uchar (info,
1479 FLASH_OFFSET_NUM_ERASE_REGIONS);
1480 info->ext_addr = flash_read_ushort (info, 0,
1481 FLASH_OFFSET_EXT_QUERY_T_P_ADDR);
1482 if (info->ext_addr) {
1483 info->cfi_version = (ushort) flash_read_uchar (info,
1484 info->ext_addr + 3) << 8;
1485 info->cfi_version |= (ushort) flash_read_uchar (info,
1486 info->ext_addr + 4);
1487 }
wdenkbf9e3b32004-02-12 00:47:09 +00001488#ifdef DEBUG
1489 flash_printqry (info, 0);
1490#endif
1491 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +00001492 case CFI_CMDSET_INTEL_STANDARD:
1493 case CFI_CMDSET_INTEL_EXTENDED:
1494 default:
1495 info->cmd_reset = FLASH_CMD_RESET;
Stefan Roese2662b402006-04-01 13:41:03 +02001496#ifdef CFG_FLASH_PROTECTION
1497 /* read legacy lock/unlock bit from intel flash */
Stefan Roese260421a2006-11-13 13:55:24 +01001498 if (info->ext_addr) {
1499 info->legacy_unlock = flash_read_uchar (info,
1500 info->ext_addr + 5) & 0x08;
1501 }
Stefan Roese2662b402006-04-01 13:41:03 +02001502#endif
wdenk5653fc32004-02-08 22:55:38 +00001503 break;
1504 case CFI_CMDSET_AMD_STANDARD:
1505 case CFI_CMDSET_AMD_EXTENDED:
1506 info->cmd_reset = AMD_CMD_RESET;
Stefan Roese260421a2006-11-13 13:55:24 +01001507 /* check if flash geometry needs reversal */
1508 if (num_erase_regions <= 1)
1509 break;
1510 /* reverse geometry if top boot part */
1511 if (info->cfi_version < 0x3131) {
1512 /* CFI < 1.1, try to guess from device id */
1513 if ((info->device_id & 0x80) != 0) {
1514 geometry_reversed = 1;
1515 }
1516 break;
1517 }
1518 /* CFI >= 1.1, deduct from top/bottom flag */
1519 /* note: ext_addr is valid since cfi_version > 0 */
1520 if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1521 geometry_reversed = 1;
1522 }
wdenk5653fc32004-02-08 22:55:38 +00001523 break;
1524 }
wdenkcd37d9e2004-02-10 00:03:41 +00001525
wdenkbf9e3b32004-02-12 00:47:09 +00001526 debug ("manufacturer is %d\n", info->vendor);
Stefan Roese260421a2006-11-13 13:55:24 +01001527 debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
1528 debug ("device id is 0x%x\n", info->device_id);
1529 debug ("device id2 is 0x%x\n", info->device_id2);
1530 debug ("cfi version is 0x%04x\n", info->cfi_version);
1531
wdenk5653fc32004-02-08 22:55:38 +00001532 size_ratio = info->portwidth / info->chipwidth;
wdenkbf9e3b32004-02-12 00:47:09 +00001533 /* if the chip is x8/x16 reduce the ratio by half */
1534 if ((info->interface == FLASH_CFI_X8X16)
1535 && (info->chipwidth == FLASH_CFI_BY8)) {
1536 size_ratio >>= 1;
1537 }
wdenkbf9e3b32004-02-12 00:47:09 +00001538 debug ("size_ratio %d port %d bits chip %d bits\n",
1539 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1540 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1541 debug ("found %d erase regions\n", num_erase_regions);
wdenk5653fc32004-02-08 22:55:38 +00001542 sect_cnt = 0;
1543 sector = base;
wdenkbf9e3b32004-02-12 00:47:09 +00001544 for (i = 0; i < num_erase_regions; i++) {
1545 if (i > NUM_ERASE_REGIONS) {
wdenk028ab6b2004-02-23 23:54:43 +00001546 printf ("%d erase regions found, only %d used\n",
1547 num_erase_regions, NUM_ERASE_REGIONS);
wdenk5653fc32004-02-08 22:55:38 +00001548 break;
1549 }
Stefan Roese260421a2006-11-13 13:55:24 +01001550 if (geometry_reversed)
1551 tmp = flash_read_long (info, 0,
1552 FLASH_OFFSET_ERASE_REGIONS +
1553 (num_erase_regions - 1 - i) * 4);
1554 else
1555 tmp = flash_read_long (info, 0,
wdenkbf9e3b32004-02-12 00:47:09 +00001556 FLASH_OFFSET_ERASE_REGIONS +
1557 i * 4);
1558 erase_region_size =
1559 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
wdenk5653fc32004-02-08 22:55:38 +00001560 tmp >>= 16;
wdenkbf9e3b32004-02-12 00:47:09 +00001561 erase_region_count = (tmp & 0xffff) + 1;
wdenk4c0d4c32004-06-09 17:34:58 +00001562 debug ("erase_region_count = %d erase_region_size = %d\n",
wdenk028ab6b2004-02-23 23:54:43 +00001563 erase_region_count, erase_region_size);
wdenkbf9e3b32004-02-12 00:47:09 +00001564 for (j = 0; j < erase_region_count; j++) {
Michael Schwingen81b20cc2007-12-07 23:35:02 +01001565 if (sect_cnt >= CFG_MAX_FLASH_SECT) {
1566 printf("ERROR: too many flash sectors\n");
1567 break;
1568 }
wdenk5653fc32004-02-08 22:55:38 +00001569 info->start[sect_cnt] = sector;
1570 sector += (erase_region_size * size_ratio);
wdenka1191902005-01-09 17:12:27 +00001571
1572 /*
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001573 * Only read protection status from
1574 * supported devices (intel...)
wdenka1191902005-01-09 17:12:27 +00001575 */
1576 switch (info->vendor) {
1577 case CFI_CMDSET_INTEL_EXTENDED:
1578 case CFI_CMDSET_INTEL_STANDARD:
1579 info->protect[sect_cnt] =
1580 flash_isset (info, sect_cnt,
1581 FLASH_OFFSET_PROTECT,
1582 FLASH_STATUS_PROTECT);
1583 break;
1584 default:
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001585 /* default: not protected */
1586 info->protect[sect_cnt] = 0;
wdenka1191902005-01-09 17:12:27 +00001587 }
1588
wdenk5653fc32004-02-08 22:55:38 +00001589 sect_cnt++;
1590 }
1591 }
1592
1593 info->sector_count = sect_cnt;
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001594 info->size = 1 << flash_read_uchar (info, FLASH_OFFSET_SIZE);
wdenk5653fc32004-02-08 22:55:38 +00001595 /* multiply the size by the number of chips */
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001596 info->size *= size_ratio;
1597 info->buffer_size = 1 << flash_read_ushort (info, 0,
1598 FLASH_OFFSET_BUFFER_SIZE);
wdenkbf9e3b32004-02-12 00:47:09 +00001599 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001600 info->erase_blk_tout = tmp *
1601 (1 << flash_read_uchar (
1602 info, FLASH_OFFSET_EMAX_TOUT));
Stefan Roese2662b402006-04-01 13:41:03 +02001603 tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) *
1604 (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT));
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001605 /* round up when converting to ms */
1606 info->buffer_write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0);
Stefan Roese79b4cda2006-02-28 15:29:58 +01001607 tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) *
1608 (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT));
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001609 /* round up when converting to ms */
1610 info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0);
wdenk5653fc32004-02-08 22:55:38 +00001611 info->flash_id = FLASH_MAN_CFI;
Haavard Skinnemoen7e5b9b42007-12-13 12:56:28 +01001612 if ((info->interface == FLASH_CFI_X8X16) &&
1613 (info->chipwidth == FLASH_CFI_BY8)) {
1614 /* XXX - Need to test on x8/x16 in parallel. */
1615 info->portwidth >>= 1;
wdenk855a4962004-03-14 18:23:55 +00001616 }
wdenk5653fc32004-02-08 22:55:38 +00001617 }
1618
Wolfgang Denkdb421e62005-09-25 16:41:22 +02001619 flash_write_cmd (info, 0, 0, info->cmd_reset);
wdenkbf9e3b32004-02-12 00:47:09 +00001620 return (info->size);
wdenk5653fc32004-02-08 22:55:38 +00001621}
1622
wdenk5653fc32004-02-08 22:55:38 +00001623/*-----------------------------------------------------------------------
1624 */
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001625unsigned long flash_init (void)
wdenk5653fc32004-02-08 22:55:38 +00001626{
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001627 unsigned long size = 0;
1628 int i;
wdenk5653fc32004-02-08 22:55:38 +00001629
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001630#ifdef CFG_FLASH_PROTECTION
1631 char *s = getenv("unlock");
Michael Schwingen81b20cc2007-12-07 23:35:02 +01001632#endif
wdenk5653fc32004-02-08 22:55:38 +00001633
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001634 /* Init: no FLASHes known */
1635 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
1636 flash_info[i].flash_id = FLASH_UNKNOWN;
wdenk5653fc32004-02-08 22:55:38 +00001637
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001638 if (!flash_detect_legacy (bank_base[i], i))
1639 flash_get_size (bank_base[i], i);
1640 size += flash_info[i].size;
1641 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
1642#ifndef CFG_FLASH_QUIET_TEST
1643 printf ("## Unknown FLASH on Bank %d "
1644 "- Size = 0x%08lx = %ld MB\n",
1645 i+1, flash_info[i].size,
1646 flash_info[i].size << 20);
1647#endif /* CFG_FLASH_QUIET_TEST */
wdenk5653fc32004-02-08 22:55:38 +00001648 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001649#ifdef CFG_FLASH_PROTECTION
1650 else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
1651 /*
1652 * Only the U-Boot image and it's environment
1653 * is protected, all other sectors are
1654 * unprotected (unlocked) if flash hardware
1655 * protection is used (CFG_FLASH_PROTECTION)
1656 * and the environment variable "unlock" is
1657 * set to "yes".
1658 */
1659 if (flash_info[i].legacy_unlock) {
1660 int k;
Stefan Roese79b4cda2006-02-28 15:29:58 +01001661
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001662 /*
1663 * Disable legacy_unlock temporarily,
1664 * since flash_real_protect would
1665 * relock all other sectors again
1666 * otherwise.
1667 */
1668 flash_info[i].legacy_unlock = 0;
Stefan Roese79b4cda2006-02-28 15:29:58 +01001669
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001670 /*
1671 * Legacy unlocking (e.g. Intel J3) ->
1672 * unlock only one sector. This will
1673 * unlock all sectors.
1674 */
1675 flash_real_protect (&flash_info[i], 0, 0);
Stefan Roese79b4cda2006-02-28 15:29:58 +01001676
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001677 flash_info[i].legacy_unlock = 1;
1678
1679 /*
1680 * Manually mark other sectors as
1681 * unlocked (unprotected)
1682 */
1683 for (k = 1; k < flash_info[i].sector_count; k++)
1684 flash_info[i].protect[k] = 0;
1685 } else {
1686 /*
1687 * No legancy unlocking -> unlock all sectors
1688 */
1689 flash_protect (FLAG_PROTECT_CLEAR,
1690 flash_info[i].start[0],
1691 flash_info[i].start[0]
1692 + flash_info[i].size - 1,
1693 &flash_info[i]);
1694 }
Stefan Roese79b4cda2006-02-28 15:29:58 +01001695 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001696#endif /* CFG_FLASH_PROTECTION */
wdenk5653fc32004-02-08 22:55:38 +00001697 }
Haavard Skinnemoenbe60a902007-10-06 18:55:36 +02001698
1699 /* Monitor protection ON by default */
1700#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
1701 flash_protect (FLAG_PROTECT_SET,
1702 CFG_MONITOR_BASE,
1703 CFG_MONITOR_BASE + monitor_flash_len - 1,
1704 flash_get_info(CFG_MONITOR_BASE));
1705#endif
1706
1707 /* Environment protection ON by default */
1708#ifdef CFG_ENV_IS_IN_FLASH
1709 flash_protect (FLAG_PROTECT_SET,
1710 CFG_ENV_ADDR,
1711 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
1712 flash_get_info(CFG_ENV_ADDR));
1713#endif
1714
1715 /* Redundant environment protection ON by default */
1716#ifdef CFG_ENV_ADDR_REDUND
1717 flash_protect (FLAG_PROTECT_SET,
1718 CFG_ENV_ADDR_REDUND,
1719 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
1720 flash_get_info(CFG_ENV_ADDR_REDUND));
1721#endif
1722 return (size);
wdenk5653fc32004-02-08 22:55:38 +00001723}
Heiko Schocherca43ba12007-01-11 15:44:44 +01001724
wdenk5653fc32004-02-08 22:55:38 +00001725#endif /* CFG_FLASH_CFI */