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wdenk5653fc32004-02-08 22:55:38 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2002-2004
wdenk5653fc32004-02-08 22:55:38 +00003 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
7 * Modified to work with AMD flashes
8 *
wdenkbf9e3b32004-02-12 00:47:09 +00009 * Copyright (C) 2004
10 * Ed Okerson
11 * Modified to work with little-endian systems.
12 *
wdenk5653fc32004-02-08 22:55:38 +000013 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 *
31 * History
32 * 01/20/2004 - combined variants of original driver.
wdenkbf9e3b32004-02-12 00:47:09 +000033 * 01/22/2004 - Write performance enhancements for parallel chips (Tolunay)
34 * 01/23/2004 - Support for x8/x16 chips (Rune Raknerud)
35 * 01/27/2004 - Little endian support Ed Okerson
wdenk5653fc32004-02-08 22:55:38 +000036 *
37 * Tested Architectures
wdenkbf9e3b32004-02-12 00:47:09 +000038 * Port Width Chip Width # of banks Flash Chip Board
wdenk2d1a5372004-02-23 19:30:57 +000039 * 32 16 1 28F128J3 seranoa/eagle
40 * 64 16 1 28F128J3 seranoa/falcon
wdenkcd37d9e2004-02-10 00:03:41 +000041 *
wdenk5653fc32004-02-08 22:55:38 +000042 */
43
44/* The DEBUG define must be before common to enable debugging */
wdenk2d1a5372004-02-23 19:30:57 +000045/* #define DEBUG */
46
wdenk5653fc32004-02-08 22:55:38 +000047#include <common.h>
48#include <asm/processor.h>
wdenk4c0d4c32004-06-09 17:34:58 +000049#include <asm/byteorder.h>
wdenk2a8af182005-04-13 10:02:42 +000050#include <environment.h>
wdenkbf9e3b32004-02-12 00:47:09 +000051#ifdef CFG_FLASH_CFI_DRIVER
wdenk028ab6b2004-02-23 23:54:43 +000052
wdenk5653fc32004-02-08 22:55:38 +000053/*
54 * This file implements a Common Flash Interface (CFI) driver for U-Boot.
55 * The width of the port and the width of the chips are determined at initialization.
56 * These widths are used to calculate the address for access CFI data structures.
57 * It has been tested on an Intel Strataflash implementation and AMD 29F016D.
58 *
59 * References
60 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
61 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
62 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
63 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
64 *
65 * TODO
66 *
67 * Use Primary Extended Query table (PRI) and Alternate Algorithm Query
68 * Table (ALT) to determine if protection is available
69 *
70 * Add support for other command sets Use the PRI and ALT to determine command set
71 * Verify erase and program timeouts.
72 */
73
wdenkbf9e3b32004-02-12 00:47:09 +000074#ifndef CFG_FLASH_BANKS_LIST
75#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
76#endif
77
wdenk5653fc32004-02-08 22:55:38 +000078#define FLASH_CMD_CFI 0x98
79#define FLASH_CMD_READ_ID 0x90
80#define FLASH_CMD_RESET 0xff
81#define FLASH_CMD_BLOCK_ERASE 0x20
82#define FLASH_CMD_ERASE_CONFIRM 0xD0
83#define FLASH_CMD_WRITE 0x40
84#define FLASH_CMD_PROTECT 0x60
85#define FLASH_CMD_PROTECT_SET 0x01
86#define FLASH_CMD_PROTECT_CLEAR 0xD0
87#define FLASH_CMD_CLEAR_STATUS 0x50
wdenkbf9e3b32004-02-12 00:47:09 +000088#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
89#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
wdenk5653fc32004-02-08 22:55:38 +000090
91#define FLASH_STATUS_DONE 0x80
92#define FLASH_STATUS_ESS 0x40
93#define FLASH_STATUS_ECLBS 0x20
94#define FLASH_STATUS_PSLBS 0x10
95#define FLASH_STATUS_VPENS 0x08
96#define FLASH_STATUS_PSS 0x04
97#define FLASH_STATUS_DPS 0x02
98#define FLASH_STATUS_R 0x01
99#define FLASH_STATUS_PROTECT 0x01
100
101#define AMD_CMD_RESET 0xF0
102#define AMD_CMD_WRITE 0xA0
103#define AMD_CMD_ERASE_START 0x80
104#define AMD_CMD_ERASE_SECTOR 0x30
wdenk855a4962004-03-14 18:23:55 +0000105#define AMD_CMD_UNLOCK_START 0xAA
106#define AMD_CMD_UNLOCK_ACK 0x55
wdenk5653fc32004-02-08 22:55:38 +0000107
108#define AMD_STATUS_TOGGLE 0x40
109#define AMD_STATUS_ERROR 0x20
wdenk855a4962004-03-14 18:23:55 +0000110#define AMD_ADDR_ERASE_START 0x555
111#define AMD_ADDR_START 0x555
112#define AMD_ADDR_ACK 0x2AA
wdenk5653fc32004-02-08 22:55:38 +0000113
114#define FLASH_OFFSET_CFI 0x55
115#define FLASH_OFFSET_CFI_RESP 0x10
wdenkbf9e3b32004-02-12 00:47:09 +0000116#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
wdenk5653fc32004-02-08 22:55:38 +0000117#define FLASH_OFFSET_WTOUT 0x1F
wdenkbf9e3b32004-02-12 00:47:09 +0000118#define FLASH_OFFSET_WBTOUT 0x20
wdenk5653fc32004-02-08 22:55:38 +0000119#define FLASH_OFFSET_ETOUT 0x21
wdenkbf9e3b32004-02-12 00:47:09 +0000120#define FLASH_OFFSET_CETOUT 0x22
wdenk5653fc32004-02-08 22:55:38 +0000121#define FLASH_OFFSET_WMAX_TOUT 0x23
wdenkbf9e3b32004-02-12 00:47:09 +0000122#define FLASH_OFFSET_WBMAX_TOUT 0x24
wdenk5653fc32004-02-08 22:55:38 +0000123#define FLASH_OFFSET_EMAX_TOUT 0x25
wdenkbf9e3b32004-02-12 00:47:09 +0000124#define FLASH_OFFSET_CEMAX_TOUT 0x26
wdenk5653fc32004-02-08 22:55:38 +0000125#define FLASH_OFFSET_SIZE 0x27
wdenkbf9e3b32004-02-12 00:47:09 +0000126#define FLASH_OFFSET_INTERFACE 0x28
127#define FLASH_OFFSET_BUFFER_SIZE 0x2A
wdenk5653fc32004-02-08 22:55:38 +0000128#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
129#define FLASH_OFFSET_ERASE_REGIONS 0x2D
130#define FLASH_OFFSET_PROTECT 0x02
wdenkbf9e3b32004-02-12 00:47:09 +0000131#define FLASH_OFFSET_USER_PROTECTION 0x85
132#define FLASH_OFFSET_INTEL_PROTECTION 0x81
wdenk5653fc32004-02-08 22:55:38 +0000133
134
135#define FLASH_MAN_CFI 0x01000000
136
wdenkbf9e3b32004-02-12 00:47:09 +0000137#define CFI_CMDSET_NONE 0
wdenk5653fc32004-02-08 22:55:38 +0000138#define CFI_CMDSET_INTEL_EXTENDED 1
wdenkbf9e3b32004-02-12 00:47:09 +0000139#define CFI_CMDSET_AMD_STANDARD 2
wdenk5653fc32004-02-08 22:55:38 +0000140#define CFI_CMDSET_INTEL_STANDARD 3
wdenkbf9e3b32004-02-12 00:47:09 +0000141#define CFI_CMDSET_AMD_EXTENDED 4
wdenk5653fc32004-02-08 22:55:38 +0000142#define CFI_CMDSET_MITSU_STANDARD 256
143#define CFI_CMDSET_MITSU_EXTENDED 257
wdenkbf9e3b32004-02-12 00:47:09 +0000144#define CFI_CMDSET_SST 258
wdenk5653fc32004-02-08 22:55:38 +0000145
146
wdenkf7d15722004-12-18 22:35:43 +0000147#ifdef CFG_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
148# undef FLASH_CMD_RESET
149# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
150#endif
151
152
wdenk5653fc32004-02-08 22:55:38 +0000153typedef union {
154 unsigned char c;
155 unsigned short w;
156 unsigned long l;
157 unsigned long long ll;
158} cfiword_t;
159
160typedef union {
wdenkbf9e3b32004-02-12 00:47:09 +0000161 volatile unsigned char *cp;
wdenk5653fc32004-02-08 22:55:38 +0000162 volatile unsigned short *wp;
wdenkbf9e3b32004-02-12 00:47:09 +0000163 volatile unsigned long *lp;
wdenk5653fc32004-02-08 22:55:38 +0000164 volatile unsigned long long *llp;
165} cfiptr_t;
166
167#define NUM_ERASE_REGIONS 4
168
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200169/* use CFG_MAX_FLASH_BANKS_DETECT if defined */
170#ifdef CFG_MAX_FLASH_BANKS_DETECT
171static ulong bank_base[CFG_MAX_FLASH_BANKS_DETECT] = CFG_FLASH_BANKS_LIST;
172flash_info_t flash_info[CFG_MAX_FLASH_BANKS_DETECT]; /* FLASH chips info */
173#else
wdenk5653fc32004-02-08 22:55:38 +0000174static ulong bank_base[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200175flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* FLASH chips info */
176#endif
wdenk5653fc32004-02-08 22:55:38 +0000177
wdenk5653fc32004-02-08 22:55:38 +0000178
179/*-----------------------------------------------------------------------
180 * Functions
181 */
182
183typedef unsigned long flash_sect_t;
184
wdenkbf9e3b32004-02-12 00:47:09 +0000185static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
186static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
wdenk028ab6b2004-02-23 23:54:43 +0000187static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
wdenkbf9e3b32004-02-12 00:47:09 +0000188static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect);
wdenk028ab6b2004-02-23 23:54:43 +0000189static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
190static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
191static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd);
wdenkbf9e3b32004-02-12 00:47:09 +0000192static int flash_detect_cfi (flash_info_t * info);
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200193ulong flash_get_size (ulong base, int banknum);
wdenk028ab6b2004-02-23 23:54:43 +0000194static int flash_write_cfiword (flash_info_t * info, ulong dest, cfiword_t cword);
wdenkbf9e3b32004-02-12 00:47:09 +0000195static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
196 ulong tout, char *prompt);
Wolfgang Denk080bdb72005-10-05 01:51:29 +0200197#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
wdenk7680c142005-05-16 15:23:22 +0000198static flash_info_t *flash_get_info(ulong base);
Wolfgang Denk080bdb72005-10-05 01:51:29 +0200199#endif
wdenk5653fc32004-02-08 22:55:38 +0000200#ifdef CFG_FLASH_USE_BUFFER_WRITE
wdenk028ab6b2004-02-23 23:54:43 +0000201static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, int len);
wdenk5653fc32004-02-08 22:55:38 +0000202#endif
203
wdenk5653fc32004-02-08 22:55:38 +0000204/*-----------------------------------------------------------------------
205 * create an address based on the offset and the port width
206 */
wdenk028ab6b2004-02-23 23:54:43 +0000207inline uchar *flash_make_addr (flash_info_t * info, flash_sect_t sect, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000208{
wdenkbf9e3b32004-02-12 00:47:09 +0000209 return ((uchar *) (info->start[sect] + (offset * info->portwidth)));
wdenk5653fc32004-02-08 22:55:38 +0000210}
wdenkbf9e3b32004-02-12 00:47:09 +0000211
212#ifdef DEBUG
213/*-----------------------------------------------------------------------
214 * Debug support
215 */
216void print_longlong (char *str, unsigned long long data)
217{
218 int i;
219 char *cp;
220
221 cp = (unsigned char *) &data;
222 for (i = 0; i < 8; i++)
223 sprintf (&str[i * 2], "%2.2x", *cp++);
224}
225static void flash_printqry (flash_info_t * info, flash_sect_t sect)
226{
227 cfiptr_t cptr;
228 int x, y;
229
Wolfgang Denk47340a42005-10-09 00:25:58 +0200230 for (x = 0; x < 0x40; x += 16U / info->portwidth) {
wdenkbf9e3b32004-02-12 00:47:09 +0000231 cptr.cp =
232 flash_make_addr (info, sect,
233 x + FLASH_OFFSET_CFI_RESP);
234 debug ("%p : ", cptr.cp);
235 for (y = 0; y < 16; y++) {
236 debug ("%2.2x ", cptr.cp[y]);
237 }
238 debug (" ");
239 for (y = 0; y < 16; y++) {
240 if (cptr.cp[y] >= 0x20 && cptr.cp[y] <= 0x7e) {
241 debug ("%c", cptr.cp[y]);
242 } else {
243 debug (".");
244 }
245 }
246 debug ("\n");
247 }
248}
wdenkbf9e3b32004-02-12 00:47:09 +0000249#endif
250
251
wdenk5653fc32004-02-08 22:55:38 +0000252/*-----------------------------------------------------------------------
253 * read a character at a port width address
254 */
wdenkbf9e3b32004-02-12 00:47:09 +0000255inline uchar flash_read_uchar (flash_info_t * info, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000256{
257 uchar *cp;
wdenkbf9e3b32004-02-12 00:47:09 +0000258
259 cp = flash_make_addr (info, 0, offset);
260#if defined(__LITTLE_ENDIAN)
261 return (cp[0]);
262#else
wdenk5653fc32004-02-08 22:55:38 +0000263 return (cp[info->portwidth - 1]);
wdenkbf9e3b32004-02-12 00:47:09 +0000264#endif
wdenk5653fc32004-02-08 22:55:38 +0000265}
266
267/*-----------------------------------------------------------------------
268 * read a short word by swapping for ppc format.
269 */
wdenkbf9e3b32004-02-12 00:47:09 +0000270ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000271{
wdenkbf9e3b32004-02-12 00:47:09 +0000272 uchar *addr;
273 ushort retval;
wdenk5653fc32004-02-08 22:55:38 +0000274
wdenkbf9e3b32004-02-12 00:47:09 +0000275#ifdef DEBUG
276 int x;
277#endif
278 addr = flash_make_addr (info, sect, offset);
wdenk5653fc32004-02-08 22:55:38 +0000279
wdenkbf9e3b32004-02-12 00:47:09 +0000280#ifdef DEBUG
281 debug ("ushort addr is at %p info->portwidth = %d\n", addr,
282 info->portwidth);
283 for (x = 0; x < 2 * info->portwidth; x++) {
284 debug ("addr[%x] = 0x%x\n", x, addr[x]);
285 }
286#endif
287#if defined(__LITTLE_ENDIAN)
288 retval = ((addr[(info->portwidth)] << 8) | addr[0]);
289#else
290 retval = ((addr[(2 * info->portwidth) - 1] << 8) |
291 addr[info->portwidth - 1]);
292#endif
293
294 debug ("retval = 0x%x\n", retval);
295 return retval;
wdenk5653fc32004-02-08 22:55:38 +0000296}
297
298/*-----------------------------------------------------------------------
299 * read a long word by picking the least significant byte of each maiximum
300 * port size word. Swap for ppc format.
301 */
wdenkbf9e3b32004-02-12 00:47:09 +0000302ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset)
wdenk5653fc32004-02-08 22:55:38 +0000303{
wdenkbf9e3b32004-02-12 00:47:09 +0000304 uchar *addr;
305 ulong retval;
wdenk5653fc32004-02-08 22:55:38 +0000306
wdenkbf9e3b32004-02-12 00:47:09 +0000307#ifdef DEBUG
308 int x;
309#endif
310 addr = flash_make_addr (info, sect, offset);
311
312#ifdef DEBUG
313 debug ("long addr is at %p info->portwidth = %d\n", addr,
314 info->portwidth);
315 for (x = 0; x < 4 * info->portwidth; x++) {
316 debug ("addr[%x] = 0x%x\n", x, addr[x]);
317 }
318#endif
319#if defined(__LITTLE_ENDIAN)
320 retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) |
wdenk028ab6b2004-02-23 23:54:43 +0000321 (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8);
wdenkbf9e3b32004-02-12 00:47:09 +0000322#else
323 retval = (addr[(2 * info->portwidth) - 1] << 24) |
324 (addr[(info->portwidth) - 1] << 16) |
325 (addr[(4 * info->portwidth) - 1] << 8) |
326 addr[(3 * info->portwidth) - 1];
327#endif
328 return retval;
wdenk5653fc32004-02-08 22:55:38 +0000329}
330
331/*-----------------------------------------------------------------------
332 */
333unsigned long flash_init (void)
334{
335 unsigned long size = 0;
336 int i;
337
338 /* Init: no FLASHes known */
wdenkbf9e3b32004-02-12 00:47:09 +0000339 for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
wdenk5653fc32004-02-08 22:55:38 +0000340 flash_info[i].flash_id = FLASH_UNKNOWN;
wdenkbf9e3b32004-02-12 00:47:09 +0000341 size += flash_info[i].size = flash_get_size (bank_base[i], i);
wdenk5653fc32004-02-08 22:55:38 +0000342 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
wdenk028ab6b2004-02-23 23:54:43 +0000343 printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
344 i, flash_info[i].size, flash_info[i].size << 20);
wdenk5653fc32004-02-08 22:55:38 +0000345 }
346 }
347
348 /* Monitor protection ON by default */
349#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
wdenkbf9e3b32004-02-12 00:47:09 +0000350 flash_protect (FLAG_PROTECT_SET,
351 CFG_MONITOR_BASE,
wdenk7680c142005-05-16 15:23:22 +0000352 CFG_MONITOR_BASE + monitor_flash_len - 1,
353 flash_get_info(CFG_MONITOR_BASE));
wdenk5653fc32004-02-08 22:55:38 +0000354#endif
355
wdenk656658d2004-10-10 22:16:06 +0000356 /* Environment protection ON by default */
357#ifdef CFG_ENV_IS_IN_FLASH
358 flash_protect (FLAG_PROTECT_SET,
359 CFG_ENV_ADDR,
360 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
wdenk7680c142005-05-16 15:23:22 +0000361 flash_get_info(CFG_ENV_ADDR));
wdenk656658d2004-10-10 22:16:06 +0000362#endif
363
364 /* Redundant environment protection ON by default */
365#ifdef CFG_ENV_ADDR_REDUND
366 flash_protect (FLAG_PROTECT_SET,
367 CFG_ENV_ADDR_REDUND,
368 CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
wdenk7680c142005-05-16 15:23:22 +0000369 flash_get_info(CFG_ENV_ADDR_REDUND));
wdenk656658d2004-10-10 22:16:06 +0000370#endif
wdenk5653fc32004-02-08 22:55:38 +0000371 return (size);
372}
373
374/*-----------------------------------------------------------------------
375 */
Wolfgang Denk080bdb72005-10-05 01:51:29 +0200376#if defined(CFG_ENV_IS_IN_FLASH) || defined(CFG_ENV_ADDR_REDUND) || (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
wdenk7680c142005-05-16 15:23:22 +0000377static flash_info_t *flash_get_info(ulong base)
378{
379 int i;
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200380 flash_info_t * info = 0;
wdenk7680c142005-05-16 15:23:22 +0000381
382 for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
383 info = & flash_info[i];
384 if (info->size && info->start[0] <= base &&
385 base <= info->start[0] + info->size - 1)
386 break;
387 }
388
389 return i == CFG_MAX_FLASH_BANKS ? 0 : info;
390}
Wolfgang Denk080bdb72005-10-05 01:51:29 +0200391#endif
wdenk7680c142005-05-16 15:23:22 +0000392
393/*-----------------------------------------------------------------------
394 */
wdenkbf9e3b32004-02-12 00:47:09 +0000395int flash_erase (flash_info_t * info, int s_first, int s_last)
wdenk5653fc32004-02-08 22:55:38 +0000396{
397 int rcode = 0;
398 int prot;
399 flash_sect_t sect;
400
wdenkbf9e3b32004-02-12 00:47:09 +0000401 if (info->flash_id != FLASH_MAN_CFI) {
wdenk4b9206e2004-03-23 22:14:11 +0000402 puts ("Can't erase unknown flash type - aborted\n");
wdenk5653fc32004-02-08 22:55:38 +0000403 return 1;
404 }
405 if ((s_first < 0) || (s_first > s_last)) {
wdenk4b9206e2004-03-23 22:14:11 +0000406 puts ("- no sectors to erase\n");
wdenk5653fc32004-02-08 22:55:38 +0000407 return 1;
408 }
409
410 prot = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000411 for (sect = s_first; sect <= s_last; ++sect) {
wdenk5653fc32004-02-08 22:55:38 +0000412 if (info->protect[sect]) {
413 prot++;
414 }
415 }
416 if (prot) {
wdenkbf9e3b32004-02-12 00:47:09 +0000417 printf ("- Warning: %d protected sectors will not be erased!\n", prot);
wdenk5653fc32004-02-08 22:55:38 +0000418 } else {
wdenk4b9206e2004-03-23 22:14:11 +0000419 putc ('\n');
wdenk5653fc32004-02-08 22:55:38 +0000420 }
421
422
wdenkbf9e3b32004-02-12 00:47:09 +0000423 for (sect = s_first; sect <= s_last; sect++) {
wdenk5653fc32004-02-08 22:55:38 +0000424 if (info->protect[sect] == 0) { /* not protected */
wdenkbf9e3b32004-02-12 00:47:09 +0000425 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +0000426 case CFI_CMDSET_INTEL_STANDARD:
427 case CFI_CMDSET_INTEL_EXTENDED:
wdenk028ab6b2004-02-23 23:54:43 +0000428 flash_write_cmd (info, sect, 0, FLASH_CMD_CLEAR_STATUS);
429 flash_write_cmd (info, sect, 0, FLASH_CMD_BLOCK_ERASE);
430 flash_write_cmd (info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
wdenk5653fc32004-02-08 22:55:38 +0000431 break;
432 case CFI_CMDSET_AMD_STANDARD:
433 case CFI_CMDSET_AMD_EXTENDED:
wdenkbf9e3b32004-02-12 00:47:09 +0000434 flash_unlock_seq (info, sect);
wdenk855a4962004-03-14 18:23:55 +0000435 flash_write_cmd (info, sect, AMD_ADDR_ERASE_START,
436 AMD_CMD_ERASE_START);
wdenkbf9e3b32004-02-12 00:47:09 +0000437 flash_unlock_seq (info, sect);
wdenk028ab6b2004-02-23 23:54:43 +0000438 flash_write_cmd (info, sect, 0, AMD_CMD_ERASE_SECTOR);
wdenk5653fc32004-02-08 22:55:38 +0000439 break;
440 default:
wdenkbf9e3b32004-02-12 00:47:09 +0000441 debug ("Unkown flash vendor %d\n",
442 info->vendor);
wdenk5653fc32004-02-08 22:55:38 +0000443 break;
444 }
445
wdenkbf9e3b32004-02-12 00:47:09 +0000446 if (flash_full_status_check
447 (info, sect, info->erase_blk_tout, "erase")) {
wdenk5653fc32004-02-08 22:55:38 +0000448 rcode = 1;
449 } else
wdenk4b9206e2004-03-23 22:14:11 +0000450 putc ('.');
wdenk5653fc32004-02-08 22:55:38 +0000451 }
452 }
wdenk4b9206e2004-03-23 22:14:11 +0000453 puts (" done\n");
wdenk5653fc32004-02-08 22:55:38 +0000454 return rcode;
455}
456
457/*-----------------------------------------------------------------------
458 */
wdenkbf9e3b32004-02-12 00:47:09 +0000459void flash_print_info (flash_info_t * info)
wdenk5653fc32004-02-08 22:55:38 +0000460{
461 int i;
462
463 if (info->flash_id != FLASH_MAN_CFI) {
wdenk4b9206e2004-03-23 22:14:11 +0000464 puts ("missing or unknown FLASH type\n");
wdenk5653fc32004-02-08 22:55:38 +0000465 return;
466 }
467
wdenkbf9e3b32004-02-12 00:47:09 +0000468 printf ("CFI conformant FLASH (%d x %d)",
469 (info->portwidth << 3), (info->chipwidth << 3));
wdenk5653fc32004-02-08 22:55:38 +0000470 printf (" Size: %ld MB in %d Sectors\n",
471 info->size >> 20, info->sector_count);
wdenk028ab6b2004-02-23 23:54:43 +0000472 printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
473 info->erase_blk_tout,
474 info->write_tout,
475 info->buffer_write_tout,
476 info->buffer_size);
wdenk5653fc32004-02-08 22:55:38 +0000477
wdenk4b9206e2004-03-23 22:14:11 +0000478 puts (" Sector Start Addresses:");
wdenkbf9e3b32004-02-12 00:47:09 +0000479 for (i = 0; i < info->sector_count; ++i) {
wdenk5653fc32004-02-08 22:55:38 +0000480#ifdef CFG_FLASH_EMPTY_INFO
481 int k;
482 int size;
483 int erased;
484 volatile unsigned long *flash;
485
486 /*
487 * Check if whole sector is erased
488 */
wdenkbf9e3b32004-02-12 00:47:09 +0000489 if (i != (info->sector_count - 1))
490 size = info->start[i + 1] - info->start[i];
wdenk5653fc32004-02-08 22:55:38 +0000491 else
wdenkbf9e3b32004-02-12 00:47:09 +0000492 size = info->start[0] + info->size - info->start[i];
wdenk5653fc32004-02-08 22:55:38 +0000493 erased = 1;
wdenkbf9e3b32004-02-12 00:47:09 +0000494 flash = (volatile unsigned long *) info->start[i];
495 size = size >> 2; /* divide by 4 for longword access */
496 for (k = 0; k < size; k++) {
497 if (*flash++ != 0xffffffff) {
498 erased = 0;
499 break;
500 }
501 }
wdenk5653fc32004-02-08 22:55:38 +0000502
503 if ((i % 5) == 0)
504 printf ("\n");
505 /* print empty and read-only info */
506 printf (" %08lX%s%s",
507 info->start[i],
508 erased ? " E" : " ",
509 info->protect[i] ? "RO " : " ");
Wolfgang Denkb63de2c2005-09-25 00:23:05 +0200510#else /* ! CFG_FLASH_EMPTY_INFO */
wdenk5653fc32004-02-08 22:55:38 +0000511 if ((i % 5) == 0)
512 printf ("\n ");
513 printf (" %08lX%s",
Wolfgang Denkb63de2c2005-09-25 00:23:05 +0200514 info->start[i], info->protect[i] ? " (RO)" : " ");
wdenk5653fc32004-02-08 22:55:38 +0000515#endif
516 }
wdenk4b9206e2004-03-23 22:14:11 +0000517 putc ('\n');
wdenk5653fc32004-02-08 22:55:38 +0000518 return;
519}
520
521/*-----------------------------------------------------------------------
522 * Copy memory to flash, returns:
523 * 0 - OK
524 * 1 - write timeout
525 * 2 - Flash not erased
526 */
wdenkbf9e3b32004-02-12 00:47:09 +0000527int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
wdenk5653fc32004-02-08 22:55:38 +0000528{
529 ulong wp;
530 ulong cp;
531 int aln;
532 cfiword_t cword;
533 int i, rc;
534
wdenkbf9e3b32004-02-12 00:47:09 +0000535#ifdef CFG_FLASH_USE_BUFFER_WRITE
536 int buffered_size;
537#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000538 /* get lower aligned address */
wdenk5653fc32004-02-08 22:55:38 +0000539 /* get lower aligned address */
540 wp = (addr & ~(info->portwidth - 1));
541
542 /* handle unaligned start */
wdenkbf9e3b32004-02-12 00:47:09 +0000543 if ((aln = addr - wp) != 0) {
wdenk5653fc32004-02-08 22:55:38 +0000544 cword.l = 0;
545 cp = wp;
wdenkbf9e3b32004-02-12 00:47:09 +0000546 for (i = 0; i < aln; ++i, ++cp)
547 flash_add_byte (info, &cword, (*(uchar *) cp));
wdenk5653fc32004-02-08 22:55:38 +0000548
wdenkbf9e3b32004-02-12 00:47:09 +0000549 for (; (i < info->portwidth) && (cnt > 0); i++) {
550 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +0000551 cnt--;
552 cp++;
553 }
wdenkbf9e3b32004-02-12 00:47:09 +0000554 for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
555 flash_add_byte (info, &cword, (*(uchar *) cp));
556 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
wdenk5653fc32004-02-08 22:55:38 +0000557 return rc;
558 wp = cp;
559 }
560
wdenkbf9e3b32004-02-12 00:47:09 +0000561 /* handle the aligned part */
wdenk5653fc32004-02-08 22:55:38 +0000562#ifdef CFG_FLASH_USE_BUFFER_WRITE
wdenkbf9e3b32004-02-12 00:47:09 +0000563 buffered_size = (info->portwidth / info->chipwidth);
564 buffered_size *= info->buffer_size;
565 while (cnt >= info->portwidth) {
566 i = buffered_size > cnt ? cnt : buffered_size;
567 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
wdenk5653fc32004-02-08 22:55:38 +0000568 return rc;
Wolfgang Denk8d4ba3d2005-08-12 22:35:59 +0200569 i -= i & (info->portwidth - 1);
wdenk5653fc32004-02-08 22:55:38 +0000570 wp += i;
571 src += i;
wdenkbf9e3b32004-02-12 00:47:09 +0000572 cnt -= i;
wdenk5653fc32004-02-08 22:55:38 +0000573 }
574#else
wdenkbf9e3b32004-02-12 00:47:09 +0000575 while (cnt >= info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000576 cword.l = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000577 for (i = 0; i < info->portwidth; i++) {
578 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +0000579 }
wdenkbf9e3b32004-02-12 00:47:09 +0000580 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
wdenk5653fc32004-02-08 22:55:38 +0000581 return rc;
582 wp += info->portwidth;
583 cnt -= info->portwidth;
584 }
585#endif /* CFG_FLASH_USE_BUFFER_WRITE */
586 if (cnt == 0) {
587 return (0);
588 }
589
590 /*
591 * handle unaligned tail bytes
592 */
593 cword.l = 0;
wdenkbf9e3b32004-02-12 00:47:09 +0000594 for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
595 flash_add_byte (info, &cword, *src++);
wdenk5653fc32004-02-08 22:55:38 +0000596 --cnt;
597 }
wdenkbf9e3b32004-02-12 00:47:09 +0000598 for (; i < info->portwidth; ++i, ++cp) {
599 flash_add_byte (info, &cword, (*(uchar *) cp));
wdenk5653fc32004-02-08 22:55:38 +0000600 }
601
wdenkbf9e3b32004-02-12 00:47:09 +0000602 return flash_write_cfiword (info, wp, cword);
wdenk5653fc32004-02-08 22:55:38 +0000603}
604
605/*-----------------------------------------------------------------------
606 */
607#ifdef CFG_FLASH_PROTECTION
608
wdenkbf9e3b32004-02-12 00:47:09 +0000609int flash_real_protect (flash_info_t * info, long sector, int prot)
wdenk5653fc32004-02-08 22:55:38 +0000610{
611 int retcode = 0;
612
wdenkbf9e3b32004-02-12 00:47:09 +0000613 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
614 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
615 if (prot)
616 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
wdenk5653fc32004-02-08 22:55:38 +0000617 else
wdenkbf9e3b32004-02-12 00:47:09 +0000618 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
wdenk5653fc32004-02-08 22:55:38 +0000619
wdenkbf9e3b32004-02-12 00:47:09 +0000620 if ((retcode =
621 flash_full_status_check (info, sector, info->erase_blk_tout,
622 prot ? "protect" : "unprotect")) == 0) {
wdenk5653fc32004-02-08 22:55:38 +0000623
624 info->protect[sector] = prot;
625 /* Intel's unprotect unprotects all locking */
wdenkbf9e3b32004-02-12 00:47:09 +0000626 if (prot == 0) {
wdenk5653fc32004-02-08 22:55:38 +0000627 flash_sect_t i;
wdenkbf9e3b32004-02-12 00:47:09 +0000628
629 for (i = 0; i < info->sector_count; i++) {
630 if (info->protect[i])
631 flash_real_protect (info, i, 1);
wdenk5653fc32004-02-08 22:55:38 +0000632 }
633 }
634 }
wdenk5653fc32004-02-08 22:55:38 +0000635 return retcode;
wdenkbf9e3b32004-02-12 00:47:09 +0000636}
637
wdenk5653fc32004-02-08 22:55:38 +0000638/*-----------------------------------------------------------------------
639 * flash_read_user_serial - read the OneTimeProgramming cells
640 */
wdenkbf9e3b32004-02-12 00:47:09 +0000641void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
642 int len)
wdenk5653fc32004-02-08 22:55:38 +0000643{
wdenkbf9e3b32004-02-12 00:47:09 +0000644 uchar *src;
645 uchar *dst;
wdenk5653fc32004-02-08 22:55:38 +0000646
647 dst = buffer;
wdenkbf9e3b32004-02-12 00:47:09 +0000648 src = flash_make_addr (info, 0, FLASH_OFFSET_USER_PROTECTION);
649 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
650 memcpy (dst, src + offset, len);
Wolfgang Denkdb421e62005-09-25 16:41:22 +0200651 flash_write_cmd (info, 0, 0, info->cmd_reset);
wdenk5653fc32004-02-08 22:55:38 +0000652}
wdenkbf9e3b32004-02-12 00:47:09 +0000653
wdenk5653fc32004-02-08 22:55:38 +0000654/*
655 * flash_read_factory_serial - read the device Id from the protection area
656 */
wdenkbf9e3b32004-02-12 00:47:09 +0000657void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
658 int len)
wdenk5653fc32004-02-08 22:55:38 +0000659{
wdenkbf9e3b32004-02-12 00:47:09 +0000660 uchar *src;
wdenkcd37d9e2004-02-10 00:03:41 +0000661
wdenkbf9e3b32004-02-12 00:47:09 +0000662 src = flash_make_addr (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
663 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
664 memcpy (buffer, src + offset, len);
Wolfgang Denkdb421e62005-09-25 16:41:22 +0200665 flash_write_cmd (info, 0, 0, info->cmd_reset);
wdenk5653fc32004-02-08 22:55:38 +0000666}
667
668#endif /* CFG_FLASH_PROTECTION */
669
wdenkbf9e3b32004-02-12 00:47:09 +0000670/*
671 * flash_is_busy - check to see if the flash is busy
672 * This routine checks the status of the chip and returns true if the chip is busy
673 */
674static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
wdenk5653fc32004-02-08 22:55:38 +0000675{
676 int retval;
wdenkbf9e3b32004-02-12 00:47:09 +0000677
678 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +0000679 case CFI_CMDSET_INTEL_STANDARD:
680 case CFI_CMDSET_INTEL_EXTENDED:
wdenkbf9e3b32004-02-12 00:47:09 +0000681 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
wdenk5653fc32004-02-08 22:55:38 +0000682 break;
683 case CFI_CMDSET_AMD_STANDARD:
684 case CFI_CMDSET_AMD_EXTENDED:
wdenkbf9e3b32004-02-12 00:47:09 +0000685 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
wdenk5653fc32004-02-08 22:55:38 +0000686 break;
687 default:
688 retval = 0;
689 }
wdenkbf9e3b32004-02-12 00:47:09 +0000690 debug ("flash_is_busy: %d\n", retval);
wdenk5653fc32004-02-08 22:55:38 +0000691 return retval;
692}
wdenkbf9e3b32004-02-12 00:47:09 +0000693
wdenk5653fc32004-02-08 22:55:38 +0000694/*-----------------------------------------------------------------------
695 * wait for XSR.7 to be set. Time out with an error if it does not.
696 * This routine does not set the flash to read-array mode.
697 */
wdenkbf9e3b32004-02-12 00:47:09 +0000698static int flash_status_check (flash_info_t * info, flash_sect_t sector,
699 ulong tout, char *prompt)
wdenk5653fc32004-02-08 22:55:38 +0000700{
701 ulong start;
702
703 /* Wait for command completion */
704 start = get_timer (0);
wdenkbf9e3b32004-02-12 00:47:09 +0000705 while (flash_is_busy (info, sector)) {
706 if (get_timer (start) > info->erase_blk_tout * CFG_HZ) {
707 printf ("Flash %s timeout at address %lx data %lx\n",
708 prompt, info->start[sector],
709 flash_read_long (info, sector, 0));
710 flash_write_cmd (info, sector, 0, info->cmd_reset);
wdenk5653fc32004-02-08 22:55:38 +0000711 return ERR_TIMOUT;
712 }
713 }
714 return ERR_OK;
715}
wdenkbf9e3b32004-02-12 00:47:09 +0000716
wdenk5653fc32004-02-08 22:55:38 +0000717/*-----------------------------------------------------------------------
718 * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
719 * This routine sets the flash to read-array mode.
720 */
wdenkbf9e3b32004-02-12 00:47:09 +0000721static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
722 ulong tout, char *prompt)
wdenk5653fc32004-02-08 22:55:38 +0000723{
724 int retcode;
wdenkbf9e3b32004-02-12 00:47:09 +0000725
726 retcode = flash_status_check (info, sector, tout, prompt);
727 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +0000728 case CFI_CMDSET_INTEL_EXTENDED:
729 case CFI_CMDSET_INTEL_STANDARD:
wdenkbf9e3b32004-02-12 00:47:09 +0000730 if ((retcode != ERR_OK)
731 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
wdenk5653fc32004-02-08 22:55:38 +0000732 retcode = ERR_INVAL;
wdenkbf9e3b32004-02-12 00:47:09 +0000733 printf ("Flash %s error at address %lx\n", prompt,
734 info->start[sector]);
wdenk028ab6b2004-02-23 23:54:43 +0000735 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
wdenk4b9206e2004-03-23 22:14:11 +0000736 puts ("Command Sequence Error.\n");
wdenk028ab6b2004-02-23 23:54:43 +0000737 } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
wdenk4b9206e2004-03-23 22:14:11 +0000738 puts ("Block Erase Error.\n");
wdenk5653fc32004-02-08 22:55:38 +0000739 retcode = ERR_NOT_ERASED;
wdenk028ab6b2004-02-23 23:54:43 +0000740 } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
wdenk4b9206e2004-03-23 22:14:11 +0000741 puts ("Locking Error\n");
wdenk5653fc32004-02-08 22:55:38 +0000742 }
wdenkbf9e3b32004-02-12 00:47:09 +0000743 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
wdenk4b9206e2004-03-23 22:14:11 +0000744 puts ("Block locked.\n");
wdenkbf9e3b32004-02-12 00:47:09 +0000745 retcode = ERR_PROTECTED;
746 }
747 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
wdenk4b9206e2004-03-23 22:14:11 +0000748 puts ("Vpp Low Error.\n");
wdenk5653fc32004-02-08 22:55:38 +0000749 }
Wolfgang Denkdb421e62005-09-25 16:41:22 +0200750 flash_write_cmd (info, sector, 0, info->cmd_reset);
wdenk5653fc32004-02-08 22:55:38 +0000751 break;
752 default:
753 break;
754 }
755 return retcode;
756}
wdenkbf9e3b32004-02-12 00:47:09 +0000757
wdenk5653fc32004-02-08 22:55:38 +0000758/*-----------------------------------------------------------------------
759 */
wdenkbf9e3b32004-02-12 00:47:09 +0000760static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
wdenk5653fc32004-02-08 22:55:38 +0000761{
wdenk4d13cba2004-03-14 14:09:05 +0000762#if defined(__LITTLE_ENDIAN)
763 unsigned short w;
764 unsigned int l;
765 unsigned long long ll;
766#endif
767
wdenkbf9e3b32004-02-12 00:47:09 +0000768 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000769 case FLASH_CFI_8BIT:
770 cword->c = c;
771 break;
772 case FLASH_CFI_16BIT:
wdenk4d13cba2004-03-14 14:09:05 +0000773#if defined(__LITTLE_ENDIAN)
774 w = c;
775 w <<= 8;
776 cword->w = (cword->w >> 8) | w;
777#else
wdenk5653fc32004-02-08 22:55:38 +0000778 cword->w = (cword->w << 8) | c;
wdenk4d13cba2004-03-14 14:09:05 +0000779#endif
wdenk5653fc32004-02-08 22:55:38 +0000780 break;
781 case FLASH_CFI_32BIT:
wdenk4d13cba2004-03-14 14:09:05 +0000782#if defined(__LITTLE_ENDIAN)
783 l = c;
784 l <<= 24;
785 cword->l = (cword->l >> 8) | l;
786#else
wdenk5653fc32004-02-08 22:55:38 +0000787 cword->l = (cword->l << 8) | c;
wdenk4d13cba2004-03-14 14:09:05 +0000788#endif
wdenk5653fc32004-02-08 22:55:38 +0000789 break;
790 case FLASH_CFI_64BIT:
wdenk4d13cba2004-03-14 14:09:05 +0000791#if defined(__LITTLE_ENDIAN)
792 ll = c;
793 ll <<= 56;
794 cword->ll = (cword->ll >> 8) | ll;
795#else
wdenk5653fc32004-02-08 22:55:38 +0000796 cword->ll = (cword->ll << 8) | c;
wdenk4d13cba2004-03-14 14:09:05 +0000797#endif
wdenk5653fc32004-02-08 22:55:38 +0000798 break;
799 }
800}
801
802
803/*-----------------------------------------------------------------------
804 * make a proper sized command based on the port and chip widths
805 */
wdenkbf9e3b32004-02-12 00:47:09 +0000806static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
wdenk5653fc32004-02-08 22:55:38 +0000807{
808 int i;
wdenkbf9e3b32004-02-12 00:47:09 +0000809 uchar *cp = (uchar *) cmdbuf;
810
wdenkbf9e3b32004-02-12 00:47:09 +0000811#if defined(__LITTLE_ENDIAN)
Wolfgang Denkdafbe372005-09-24 23:32:48 +0200812 for (i = info->portwidth; i > 0; i--)
813#else
814 for (i = 1; i <= info->portwidth; i++)
wdenkbf9e3b32004-02-12 00:47:09 +0000815#endif
Wolfgang Denk47340a42005-10-09 00:25:58 +0200816 *cp++ = (i & (info->chipwidth - 1)) ? '\0' : cmd;
wdenk5653fc32004-02-08 22:55:38 +0000817}
818
819/*
820 * Write a proper sized command to the correct address
821 */
wdenk028ab6b2004-02-23 23:54:43 +0000822static void flash_write_cmd (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
wdenk5653fc32004-02-08 22:55:38 +0000823{
824
825 volatile cfiptr_t addr;
826 cfiword_t cword;
wdenkbf9e3b32004-02-12 00:47:09 +0000827
828 addr.cp = flash_make_addr (info, sect, offset);
829 flash_make_cmd (info, cmd, &cword);
830 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000831 case FLASH_CFI_8BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000832 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr.cp, cmd,
833 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
wdenk5653fc32004-02-08 22:55:38 +0000834 *addr.cp = cword.c;
835 break;
836 case FLASH_CFI_16BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000837 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr.wp,
838 cmd, cword.w,
wdenk5653fc32004-02-08 22:55:38 +0000839 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
840 *addr.wp = cword.w;
841 break;
842 case FLASH_CFI_32BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000843 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr.lp,
844 cmd, cword.l,
wdenk5653fc32004-02-08 22:55:38 +0000845 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
846 *addr.lp = cword.l;
847 break;
848 case FLASH_CFI_64BIT:
849#ifdef DEBUG
wdenkbf9e3b32004-02-12 00:47:09 +0000850 {
wdenk5653fc32004-02-08 22:55:38 +0000851 char str[20];
wdenkcd37d9e2004-02-10 00:03:41 +0000852
wdenkbf9e3b32004-02-12 00:47:09 +0000853 print_longlong (str, cword.ll);
854
855 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
856 addr.llp, cmd, str,
wdenk5653fc32004-02-08 22:55:38 +0000857 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
858 }
859#endif
860 *addr.llp = cword.ll;
861 break;
862 }
863}
864
wdenkbf9e3b32004-02-12 00:47:09 +0000865static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
wdenk5653fc32004-02-08 22:55:38 +0000866{
wdenk855a4962004-03-14 18:23:55 +0000867 flash_write_cmd (info, sect, AMD_ADDR_START, AMD_CMD_UNLOCK_START);
868 flash_write_cmd (info, sect, AMD_ADDR_ACK, AMD_CMD_UNLOCK_ACK);
wdenk5653fc32004-02-08 22:55:38 +0000869}
wdenkbf9e3b32004-02-12 00:47:09 +0000870
wdenk5653fc32004-02-08 22:55:38 +0000871/*-----------------------------------------------------------------------
872 */
wdenk028ab6b2004-02-23 23:54:43 +0000873static int flash_isequal (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
wdenk5653fc32004-02-08 22:55:38 +0000874{
875 cfiptr_t cptr;
876 cfiword_t cword;
877 int retval;
wdenk5653fc32004-02-08 22:55:38 +0000878
wdenkbf9e3b32004-02-12 00:47:09 +0000879 cptr.cp = flash_make_addr (info, sect, offset);
880 flash_make_cmd (info, cmd, &cword);
881
882 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, cptr.cp);
883 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000884 case FLASH_CFI_8BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000885 debug ("is= %x %x\n", cptr.cp[0], cword.c);
wdenk5653fc32004-02-08 22:55:38 +0000886 retval = (cptr.cp[0] == cword.c);
887 break;
888 case FLASH_CFI_16BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000889 debug ("is= %4.4x %4.4x\n", cptr.wp[0], cword.w);
wdenk5653fc32004-02-08 22:55:38 +0000890 retval = (cptr.wp[0] == cword.w);
891 break;
892 case FLASH_CFI_32BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000893 debug ("is= %8.8lx %8.8lx\n", cptr.lp[0], cword.l);
wdenk5653fc32004-02-08 22:55:38 +0000894 retval = (cptr.lp[0] == cword.l);
895 break;
896 case FLASH_CFI_64BIT:
wdenkcd37d9e2004-02-10 00:03:41 +0000897#ifdef DEBUG
wdenkbf9e3b32004-02-12 00:47:09 +0000898 {
wdenk5653fc32004-02-08 22:55:38 +0000899 char str1[20];
900 char str2[20];
wdenkbf9e3b32004-02-12 00:47:09 +0000901
902 print_longlong (str1, cptr.llp[0]);
903 print_longlong (str2, cword.ll);
904 debug ("is= %s %s\n", str1, str2);
wdenk5653fc32004-02-08 22:55:38 +0000905 }
906#endif
907 retval = (cptr.llp[0] == cword.ll);
908 break;
909 default:
910 retval = 0;
911 break;
912 }
913 return retval;
914}
wdenkbf9e3b32004-02-12 00:47:09 +0000915
wdenk5653fc32004-02-08 22:55:38 +0000916/*-----------------------------------------------------------------------
917 */
wdenk028ab6b2004-02-23 23:54:43 +0000918static int flash_isset (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
wdenk5653fc32004-02-08 22:55:38 +0000919{
920 cfiptr_t cptr;
921 cfiword_t cword;
922 int retval;
wdenkbf9e3b32004-02-12 00:47:09 +0000923
924 cptr.cp = flash_make_addr (info, sect, offset);
925 flash_make_cmd (info, cmd, &cword);
926 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000927 case FLASH_CFI_8BIT:
928 retval = ((cptr.cp[0] & cword.c) == cword.c);
929 break;
930 case FLASH_CFI_16BIT:
931 retval = ((cptr.wp[0] & cword.w) == cword.w);
932 break;
933 case FLASH_CFI_32BIT:
934 retval = ((cptr.lp[0] & cword.l) == cword.l);
935 break;
936 case FLASH_CFI_64BIT:
937 retval = ((cptr.llp[0] & cword.ll) == cword.ll);
wdenkbf9e3b32004-02-12 00:47:09 +0000938 break;
wdenk5653fc32004-02-08 22:55:38 +0000939 default:
940 retval = 0;
941 break;
942 }
943 return retval;
944}
945
946/*-----------------------------------------------------------------------
947 */
wdenk028ab6b2004-02-23 23:54:43 +0000948static int flash_toggle (flash_info_t * info, flash_sect_t sect, uint offset, uchar cmd)
wdenk5653fc32004-02-08 22:55:38 +0000949{
950 cfiptr_t cptr;
951 cfiword_t cword;
952 int retval;
wdenkbf9e3b32004-02-12 00:47:09 +0000953
954 cptr.cp = flash_make_addr (info, sect, offset);
955 flash_make_cmd (info, cmd, &cword);
956 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +0000957 case FLASH_CFI_8BIT:
958 retval = ((cptr.cp[0] & cword.c) != (cptr.cp[0] & cword.c));
959 break;
960 case FLASH_CFI_16BIT:
961 retval = ((cptr.wp[0] & cword.w) != (cptr.wp[0] & cword.w));
962 break;
963 case FLASH_CFI_32BIT:
964 retval = ((cptr.lp[0] & cword.l) != (cptr.lp[0] & cword.l));
965 break;
966 case FLASH_CFI_64BIT:
wdenkbf9e3b32004-02-12 00:47:09 +0000967 retval = ((cptr.llp[0] & cword.ll) !=
968 (cptr.llp[0] & cword.ll));
wdenk5653fc32004-02-08 22:55:38 +0000969 break;
970 default:
971 retval = 0;
972 break;
973 }
974 return retval;
975}
976
977/*-----------------------------------------------------------------------
978 * detect if flash is compatible with the Common Flash Interface (CFI)
979 * http://www.jedec.org/download/search/jesd68.pdf
980 *
981*/
wdenkbf9e3b32004-02-12 00:47:09 +0000982static int flash_detect_cfi (flash_info_t * info)
wdenk5653fc32004-02-08 22:55:38 +0000983{
wdenkbf9e3b32004-02-12 00:47:09 +0000984 debug ("flash detect cfi\n");
wdenk5653fc32004-02-08 22:55:38 +0000985
wdenkbf9e3b32004-02-12 00:47:09 +0000986 for (info->portwidth = FLASH_CFI_8BIT;
987 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
988 for (info->chipwidth = FLASH_CFI_BY8;
989 info->chipwidth <= info->portwidth;
990 info->chipwidth <<= 1) {
Wolfgang Denkdb421e62005-09-25 16:41:22 +0200991 flash_write_cmd (info, 0, 0, info->cmd_reset);
wdenk028ab6b2004-02-23 23:54:43 +0000992 flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
993 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
994 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
995 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
996 info->interface = flash_read_ushort (info, 0, FLASH_OFFSET_INTERFACE);
wdenkbf9e3b32004-02-12 00:47:09 +0000997 debug ("device interface is %d\n",
998 info->interface);
999 debug ("found port %d chip %d ",
1000 info->portwidth, info->chipwidth);
1001 debug ("port %d bits chip %d bits\n",
wdenk028ab6b2004-02-23 23:54:43 +00001002 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1003 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
wdenk5653fc32004-02-08 22:55:38 +00001004 return 1;
1005 }
1006 }
1007 }
wdenkbf9e3b32004-02-12 00:47:09 +00001008 debug ("not found\n");
wdenk5653fc32004-02-08 22:55:38 +00001009 return 0;
1010}
wdenkbf9e3b32004-02-12 00:47:09 +00001011
wdenk5653fc32004-02-08 22:55:38 +00001012/*
1013 * The following code cannot be run from FLASH!
1014 *
1015 */
Marian Balakowicze6f2e902005-10-11 19:09:42 +02001016ulong flash_get_size (ulong base, int banknum)
wdenk5653fc32004-02-08 22:55:38 +00001017{
wdenkbf9e3b32004-02-12 00:47:09 +00001018 flash_info_t *info = &flash_info[banknum];
wdenk5653fc32004-02-08 22:55:38 +00001019 int i, j;
1020 flash_sect_t sect_cnt;
1021 unsigned long sector;
1022 unsigned long tmp;
1023 int size_ratio;
1024 uchar num_erase_regions;
wdenkbf9e3b32004-02-12 00:47:09 +00001025 int erase_region_size;
1026 int erase_region_count;
wdenk5653fc32004-02-08 22:55:38 +00001027
1028 info->start[0] = base;
1029
wdenkbf9e3b32004-02-12 00:47:09 +00001030 if (flash_detect_cfi (info)) {
wdenk028ab6b2004-02-23 23:54:43 +00001031 info->vendor = flash_read_ushort (info, 0, FLASH_OFFSET_PRIMARY_VENDOR);
wdenkbf9e3b32004-02-12 00:47:09 +00001032#ifdef DEBUG
1033 flash_printqry (info, 0);
1034#endif
1035 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +00001036 case CFI_CMDSET_INTEL_STANDARD:
1037 case CFI_CMDSET_INTEL_EXTENDED:
1038 default:
1039 info->cmd_reset = FLASH_CMD_RESET;
1040 break;
1041 case CFI_CMDSET_AMD_STANDARD:
1042 case CFI_CMDSET_AMD_EXTENDED:
1043 info->cmd_reset = AMD_CMD_RESET;
1044 break;
1045 }
wdenkcd37d9e2004-02-10 00:03:41 +00001046
wdenkbf9e3b32004-02-12 00:47:09 +00001047 debug ("manufacturer is %d\n", info->vendor);
wdenk5653fc32004-02-08 22:55:38 +00001048 size_ratio = info->portwidth / info->chipwidth;
wdenkbf9e3b32004-02-12 00:47:09 +00001049 /* if the chip is x8/x16 reduce the ratio by half */
1050 if ((info->interface == FLASH_CFI_X8X16)
1051 && (info->chipwidth == FLASH_CFI_BY8)) {
1052 size_ratio >>= 1;
1053 }
wdenk028ab6b2004-02-23 23:54:43 +00001054 num_erase_regions = flash_read_uchar (info, FLASH_OFFSET_NUM_ERASE_REGIONS);
wdenkbf9e3b32004-02-12 00:47:09 +00001055 debug ("size_ratio %d port %d bits chip %d bits\n",
1056 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1057 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1058 debug ("found %d erase regions\n", num_erase_regions);
wdenk5653fc32004-02-08 22:55:38 +00001059 sect_cnt = 0;
1060 sector = base;
wdenkbf9e3b32004-02-12 00:47:09 +00001061 for (i = 0; i < num_erase_regions; i++) {
1062 if (i > NUM_ERASE_REGIONS) {
wdenk028ab6b2004-02-23 23:54:43 +00001063 printf ("%d erase regions found, only %d used\n",
1064 num_erase_regions, NUM_ERASE_REGIONS);
wdenk5653fc32004-02-08 22:55:38 +00001065 break;
1066 }
wdenkbf9e3b32004-02-12 00:47:09 +00001067 tmp = flash_read_long (info, 0,
1068 FLASH_OFFSET_ERASE_REGIONS +
1069 i * 4);
1070 erase_region_size =
1071 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
wdenk5653fc32004-02-08 22:55:38 +00001072 tmp >>= 16;
wdenkbf9e3b32004-02-12 00:47:09 +00001073 erase_region_count = (tmp & 0xffff) + 1;
wdenk4c0d4c32004-06-09 17:34:58 +00001074 debug ("erase_region_count = %d erase_region_size = %d\n",
wdenk028ab6b2004-02-23 23:54:43 +00001075 erase_region_count, erase_region_size);
wdenkbf9e3b32004-02-12 00:47:09 +00001076 for (j = 0; j < erase_region_count; j++) {
wdenk5653fc32004-02-08 22:55:38 +00001077 info->start[sect_cnt] = sector;
1078 sector += (erase_region_size * size_ratio);
wdenka1191902005-01-09 17:12:27 +00001079
1080 /*
1081 * Only read protection status from supported devices (intel...)
1082 */
1083 switch (info->vendor) {
1084 case CFI_CMDSET_INTEL_EXTENDED:
1085 case CFI_CMDSET_INTEL_STANDARD:
1086 info->protect[sect_cnt] =
1087 flash_isset (info, sect_cnt,
1088 FLASH_OFFSET_PROTECT,
1089 FLASH_STATUS_PROTECT);
1090 break;
1091 default:
1092 info->protect[sect_cnt] = 0; /* default: not protected */
1093 }
1094
wdenk5653fc32004-02-08 22:55:38 +00001095 sect_cnt++;
1096 }
1097 }
1098
1099 info->sector_count = sect_cnt;
1100 /* multiply the size by the number of chips */
wdenk028ab6b2004-02-23 23:54:43 +00001101 info->size = (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) * size_ratio;
1102 info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE));
wdenkbf9e3b32004-02-12 00:47:09 +00001103 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
wdenk028ab6b2004-02-23 23:54:43 +00001104 info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
wdenkbf9e3b32004-02-12 00:47:09 +00001105 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
wdenk028ab6b2004-02-23 23:54:43 +00001106 info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
wdenkbf9e3b32004-02-12 00:47:09 +00001107 tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
wdenk028ab6b2004-02-23 23:54:43 +00001108 info->write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT))) / 1000;
wdenk5653fc32004-02-08 22:55:38 +00001109 info->flash_id = FLASH_MAN_CFI;
wdenk855a4962004-03-14 18:23:55 +00001110 if ((info->interface == FLASH_CFI_X8X16) && (info->chipwidth == FLASH_CFI_BY8)) {
1111 info->portwidth >>= 1; /* XXX - Need to test on x8/x16 in parallel. */
1112 }
wdenk5653fc32004-02-08 22:55:38 +00001113 }
1114
Wolfgang Denkdb421e62005-09-25 16:41:22 +02001115 flash_write_cmd (info, 0, 0, info->cmd_reset);
wdenkbf9e3b32004-02-12 00:47:09 +00001116 return (info->size);
wdenk5653fc32004-02-08 22:55:38 +00001117}
1118
1119
1120/*-----------------------------------------------------------------------
1121 */
wdenkbf9e3b32004-02-12 00:47:09 +00001122static int flash_write_cfiword (flash_info_t * info, ulong dest,
1123 cfiword_t cword)
wdenk5653fc32004-02-08 22:55:38 +00001124{
1125
1126 cfiptr_t ctladdr;
1127 cfiptr_t cptr;
1128 int flag;
1129
wdenkbf9e3b32004-02-12 00:47:09 +00001130 ctladdr.cp = flash_make_addr (info, 0, 0);
1131 cptr.cp = (uchar *) dest;
wdenk5653fc32004-02-08 22:55:38 +00001132
1133
1134 /* Check if Flash is (sufficiently) erased */
wdenkbf9e3b32004-02-12 00:47:09 +00001135 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001136 case FLASH_CFI_8BIT:
1137 flag = ((cptr.cp[0] & cword.c) == cword.c);
1138 break;
1139 case FLASH_CFI_16BIT:
1140 flag = ((cptr.wp[0] & cword.w) == cword.w);
1141 break;
1142 case FLASH_CFI_32BIT:
wdenkbf9e3b32004-02-12 00:47:09 +00001143 flag = ((cptr.lp[0] & cword.l) == cword.l);
wdenk5653fc32004-02-08 22:55:38 +00001144 break;
1145 case FLASH_CFI_64BIT:
wdenke1599e82004-10-10 23:27:33 +00001146 flag = ((cptr.llp[0] & cword.ll) == cword.ll);
wdenk5653fc32004-02-08 22:55:38 +00001147 break;
1148 default:
1149 return 2;
1150 }
wdenkbf9e3b32004-02-12 00:47:09 +00001151 if (!flag)
wdenk5653fc32004-02-08 22:55:38 +00001152 return 2;
1153
1154 /* Disable interrupts which might cause a timeout here */
wdenkbf9e3b32004-02-12 00:47:09 +00001155 flag = disable_interrupts ();
wdenk5653fc32004-02-08 22:55:38 +00001156
wdenkbf9e3b32004-02-12 00:47:09 +00001157 switch (info->vendor) {
wdenk5653fc32004-02-08 22:55:38 +00001158 case CFI_CMDSET_INTEL_EXTENDED:
1159 case CFI_CMDSET_INTEL_STANDARD:
wdenkbf9e3b32004-02-12 00:47:09 +00001160 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
1161 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
wdenk5653fc32004-02-08 22:55:38 +00001162 break;
1163 case CFI_CMDSET_AMD_EXTENDED:
1164 case CFI_CMDSET_AMD_STANDARD:
wdenkbf9e3b32004-02-12 00:47:09 +00001165 flash_unlock_seq (info, 0);
wdenk855a4962004-03-14 18:23:55 +00001166 flash_write_cmd (info, 0, AMD_ADDR_START, AMD_CMD_WRITE);
wdenk5653fc32004-02-08 22:55:38 +00001167 break;
1168 }
1169
wdenkbf9e3b32004-02-12 00:47:09 +00001170 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001171 case FLASH_CFI_8BIT:
1172 cptr.cp[0] = cword.c;
1173 break;
1174 case FLASH_CFI_16BIT:
1175 cptr.wp[0] = cword.w;
1176 break;
1177 case FLASH_CFI_32BIT:
1178 cptr.lp[0] = cword.l;
1179 break;
1180 case FLASH_CFI_64BIT:
1181 cptr.llp[0] = cword.ll;
1182 break;
1183 }
1184
1185 /* re-enable interrupts if necessary */
wdenkbf9e3b32004-02-12 00:47:09 +00001186 if (flag)
1187 enable_interrupts ();
wdenk5653fc32004-02-08 22:55:38 +00001188
wdenkbf9e3b32004-02-12 00:47:09 +00001189 return flash_full_status_check (info, 0, info->write_tout, "write");
wdenk5653fc32004-02-08 22:55:38 +00001190}
1191
1192#ifdef CFG_FLASH_USE_BUFFER_WRITE
1193
1194/* loop through the sectors from the highest address
1195 * when the passed address is greater or equal to the sector address
1196 * we have a match
1197 */
wdenkbf9e3b32004-02-12 00:47:09 +00001198static flash_sect_t find_sector (flash_info_t * info, ulong addr)
wdenk5653fc32004-02-08 22:55:38 +00001199{
1200 flash_sect_t sector;
wdenkbf9e3b32004-02-12 00:47:09 +00001201
1202 for (sector = info->sector_count - 1; sector >= 0; sector--) {
1203 if (addr >= info->start[sector])
wdenk5653fc32004-02-08 22:55:38 +00001204 break;
1205 }
1206 return sector;
1207}
1208
wdenkbf9e3b32004-02-12 00:47:09 +00001209static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
1210 int len)
wdenk5653fc32004-02-08 22:55:38 +00001211{
1212 flash_sect_t sector;
1213 int cnt;
1214 int retcode;
1215 volatile cfiptr_t src;
1216 volatile cfiptr_t dst;
wdenk855a4962004-03-14 18:23:55 +00001217 /* buffered writes in the AMD chip set is not supported yet */
1218 if((info->vendor == CFI_CMDSET_AMD_STANDARD) ||
1219 (info->vendor == CFI_CMDSET_AMD_EXTENDED))
1220 return ERR_INVAL;
wdenk5653fc32004-02-08 22:55:38 +00001221
1222 src.cp = cp;
wdenkbf9e3b32004-02-12 00:47:09 +00001223 dst.cp = (uchar *) dest;
1224 sector = find_sector (info, dest);
1225 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1226 flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
1227 if ((retcode =
1228 flash_status_check (info, sector, info->buffer_write_tout,
1229 "write to buffer")) == ERR_OK) {
1230 /* reduce the number of loops by the width of the port */
1231 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001232 case FLASH_CFI_8BIT:
1233 cnt = len;
1234 break;
1235 case FLASH_CFI_16BIT:
1236 cnt = len >> 1;
1237 break;
1238 case FLASH_CFI_32BIT:
1239 cnt = len >> 2;
1240 break;
1241 case FLASH_CFI_64BIT:
1242 cnt = len >> 3;
1243 break;
1244 default:
1245 return ERR_INVAL;
1246 break;
1247 }
wdenkbf9e3b32004-02-12 00:47:09 +00001248 flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
1249 while (cnt-- > 0) {
1250 switch (info->portwidth) {
wdenk5653fc32004-02-08 22:55:38 +00001251 case FLASH_CFI_8BIT:
1252 *dst.cp++ = *src.cp++;
1253 break;
1254 case FLASH_CFI_16BIT:
1255 *dst.wp++ = *src.wp++;
1256 break;
1257 case FLASH_CFI_32BIT:
1258 *dst.lp++ = *src.lp++;
1259 break;
1260 case FLASH_CFI_64BIT:
1261 *dst.llp++ = *src.llp++;
1262 break;
1263 default:
1264 return ERR_INVAL;
1265 break;
1266 }
1267 }
wdenkbf9e3b32004-02-12 00:47:09 +00001268 flash_write_cmd (info, sector, 0,
1269 FLASH_CMD_WRITE_BUFFER_CONFIRM);
1270 retcode =
1271 flash_full_status_check (info, sector,
1272 info->buffer_write_tout,
1273 "buffer write");
wdenk5653fc32004-02-08 22:55:38 +00001274 }
wdenkbf9e3b32004-02-12 00:47:09 +00001275 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
wdenk5653fc32004-02-08 22:55:38 +00001276 return retcode;
1277}
wdenkcce625e2004-09-28 19:00:19 +00001278#endif /* CFG_FLASH_USE_BUFFER_WRITE */
wdenk5653fc32004-02-08 22:55:38 +00001279#endif /* CFG_FLASH_CFI */