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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
39#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
40
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
42
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050044#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroesea20b27a2004-12-16 18:05:42 +000045
46#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
47
48#define CONFIG_BAUDRATE 9600
49#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
50
51#undef CONFIG_BOOTARGS
52#undef CONFIG_BOOTCOMMAND
53
54#define CONFIG_PREBOOT /* enable preboot variable */
55
56#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +000058
Ben Warren96e21f82008-10-27 23:50:15 -070059#define CONFIG_PPC4xx_EMAC
stroesea20b27a2004-12-16 18:05:42 +000060#define CONFIG_MII 1 /* MII PHY management */
61#define CONFIG_PHY_ADDR 0 /* PHY address */
62#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Matthias Fuchs6f35c532007-06-24 17:41:21 +020063#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
64
65#define CONFIG_NET_MULTI 1
66#undef CONFIG_HAS_ETH1
stroesea20b27a2004-12-16 18:05:42 +000067
68#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
69
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050070/*
71 * BOOTP options
72 */
73#define CONFIG_BOOTP_SUBNETMASK
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76#define CONFIG_BOOTP_BOOTPATH
77#define CONFIG_BOOTP_DNS
78#define CONFIG_BOOTP_DNS2
79#define CONFIG_BOOTP_SEND_HOSTNAME
stroesea20b27a2004-12-16 18:05:42 +000080
stroesea20b27a2004-12-16 18:05:42 +000081
Jon Loeliger49cf7e82007-07-05 19:52:35 -050082/*
83 * Command line configuration.
84 */
85#include <config_cmd_default.h>
86
87#define CONFIG_CMD_DHCP
88#define CONFIG_CMD_PCI
89#define CONFIG_CMD_IRQ
90#define CONFIG_CMD_IDE
91#define CONFIG_CMD_FAT
92#define CONFIG_CMD_ELF
93#define CONFIG_CMD_DATE
Jon Loeliger49cf7e82007-07-05 19:52:35 -050094#define CONFIG_CMD_I2C
95#define CONFIG_CMD_MII
96#define CONFIG_CMD_PING
97#define CONFIG_CMD_BSP
98#define CONFIG_CMD_EEPROM
99
stroesea20b27a2004-12-16 18:05:42 +0000100#define CONFIG_MAC_PARTITION
101#define CONFIG_DOS_PARTITION
102
103#define CONFIG_SUPPORT_VFAT
104
105#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
106
stroesea20b27a2004-12-16 18:05:42 +0000107#undef CONFIG_WATCHDOG /* watchdog disabled */
108
109#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
110
111/*
112 * Miscellaneous configurable options
113 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LONGHELP /* undef to save memory */
115#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroesea20b27a2004-12-16 18:05:42 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
118#ifdef CONFIG_SYS_HUSH_PARSER
119#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroesea20b27a2004-12-16 18:05:42 +0000120#endif
121
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500122#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000124#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000126#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
128#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
129#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000130
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea20b27a2004-12-16 18:05:42 +0000134
135#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
138#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000139
Stefan Roese550650d2010-09-20 16:05:31 +0200140#define CONFIG_CONS_INDEX 1 /* Use UART0 */
141#define CONFIG_SYS_NS16550
142#define CONFIG_SYS_NS16550_SERIAL
143#define CONFIG_SYS_NS16550_REG_SIZE 1
144#define CONFIG_SYS_NS16550_CLK get_serial_clock()
145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000148
149/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea20b27a2004-12-16 18:05:42 +0000151 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
152 57600, 115200, 230400, 460800, 921600 }
153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
155#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesea20b27a2004-12-16 18:05:42 +0000158
159#define CONFIG_LOOPW 1 /* enable loopw command */
160
161#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
162
163/* Only interrupt boot if special string is typed */
Stefan Roesef2302d42008-08-06 14:05:38 +0200164#define CONFIG_AUTOBOOT_KEYED 1
165#define CONFIG_AUTOBOOT_PROMPT \
166 "Autobooting in %d seconds\n", bootdelay
stroesea20b27a2004-12-16 18:05:42 +0000167#undef CONFIG_AUTOBOOT_DELAY_STR
168#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */
169#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
170
171#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000174
175/*-----------------------------------------------------------------------
176 * PCI stuff
177 *-----------------------------------------------------------------------
178 */
179#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
180#define PCI_HOST_FORCE 1 /* configure as pci host */
181#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
182
183#define CONFIG_PCI /* include pci support */
184#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
185#define CONFIG_PCI_PNP /* do pci plug-and-play */
186 /* resource configuration */
187
188#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
189
190#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
191
192#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
195#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
196#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
197#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
198#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
199#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
200#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
201#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
202#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
203#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroesea20b27a2004-12-16 18:05:42 +0000204
Matthias Fuchs82379b52009-09-07 17:00:41 +0200205#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
206
stroesea20b27a2004-12-16 18:05:42 +0000207/*-----------------------------------------------------------------------
208 * IDE/ATA stuff
209 *-----------------------------------------------------------------------
210 */
211#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
212#undef CONFIG_IDE_LED /* no led for ide supported */
213#define CONFIG_IDE_RESET 1 /* reset for ide supported */
214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
216#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
stroesea20b27a2004-12-16 18:05:42 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
219#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroesea20b27a2004-12-16 18:05:42 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
222#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
223#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesea20b27a2004-12-16 18:05:42 +0000224
225/*-----------------------------------------------------------------------
226 * Start addresses for the final memory configuration
227 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_SDRAM_BASE 0x00000000
231#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
232#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
233#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
234#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
stroesea20b27a2004-12-16 18:05:42 +0000235
236/*
237 * For booting Linux, the board info and command line data
238 * have to be in the first 8 MB of memory, since this is
239 * the maximum mapped by the Linux kernel during initialization.
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000242/*-----------------------------------------------------------------------
243 * FLASH organization
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
246#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea20b27a2004-12-16 18:05:42 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
249#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
252#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
253#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea20b27a2004-12-16 18:05:42 +0000254/*
255 * The following defines are added for buggy IOP480 byte interface.
256 * All other boards should use the standard values (CPCI405 etc.)
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
259#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
260#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea20b27a2004-12-16 18:05:42 +0000261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000263
stroesea20b27a2004-12-16 18:05:42 +0000264#if 0 /* Use NVRAM for environment variables */
265/*-----------------------------------------------------------------------
266 * NVRAM organization
267 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200268#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200269#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
270#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
stroesea20b27a2004-12-16 18:05:42 +0000272
273#else /* Use EEPROM for environment variables */
274
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200275#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200276#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
277#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000278 /* total size of a CAT24WC16 is 2048 bytes */
279#endif
280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
282#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
283#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
stroesea20b27a2004-12-16 18:05:42 +0000284
285/*-----------------------------------------------------------------------
286 * I2C EEPROM (CAT24WC16) for environment
287 */
288#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200289#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
291#define CONFIG_SYS_I2C_SLAVE 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
294#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000295/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
297#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000298 /* 16 byte page write mode using*/
299 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000301
stroesea20b27a2004-12-16 18:05:42 +0000302/*
303 * Init Memory Controller:
304 *
305 * BR0/1 and OR0/1 (FLASH)
306 */
307
308#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
309#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
310
311/*-----------------------------------------------------------------------
312 * External Bus Controller (EBC) Setup
313 */
314
315/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_EBC_PB0AP 0x92015480
317#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000318
319/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_EBC_PB1AP 0x92015480
321#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000322
323/* Memory Bank 2 (CAN0, 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
325#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
326#define CONFIG_SYS_LED_ADDR 0xF0000380
stroesea20b27a2004-12-16 18:05:42 +0000327
328/* Memory Bank 3 (CompactFlash IDE) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
330#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000331
332/* Memory Bank 4 (NVRAM/RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333/*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */
334#define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */
335#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000336
337/* Memory Bank 5 (optional Quart) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
339#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000340
341/* Memory Bank 6 (FPGA internal) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
343#define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
344#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
stroesea20b27a2004-12-16 18:05:42 +0000345
346/*-----------------------------------------------------------------------
347 * FPGA stuff
348 */
349/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_FPGA_MODE 0x00
351#define CONFIG_SYS_FPGA_STATUS 0x02
352#define CONFIG_SYS_FPGA_TS 0x04
353#define CONFIG_SYS_FPGA_TS_LOW 0x06
354#define CONFIG_SYS_FPGA_TS_CAP0 0x10
355#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
356#define CONFIG_SYS_FPGA_TS_CAP1 0x14
357#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
358#define CONFIG_SYS_FPGA_TS_CAP2 0x18
359#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
360#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
361#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
stroesea20b27a2004-12-16 18:05:42 +0000362
363/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
365#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
366#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */
367#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
368#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
369#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
stroesea20b27a2004-12-16 18:05:42 +0000370
371/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
373#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
374#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
375#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
376#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
stroesea20b27a2004-12-16 18:05:42 +0000377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
379#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */
stroesea20b27a2004-12-16 18:05:42 +0000380
381/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
383#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
384#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
385#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
386#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000387
388/*-----------------------------------------------------------------------
389 * Definitions for initial stack pointer and data area (in data cache)
390 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
stroesea20b27a2004-12-16 18:05:42 +0000392
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200394#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200395#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000397
stroesea20b27a2004-12-16 18:05:42 +0000398#endif /* __CONFIG_H */