blob: 7bf9fc76c2168a5b301d76aa71c5807fa22528e4 [file] [log] [blame]
Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
Paul Gortmaker2738bc82009-09-20 20:36:06 -04002 * Copyright 2007,2009 Wind River Systems <www.windriver.com>
Joe Hamman9e3ed392007-12-13 06:45:14 -06003 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * sbc8548 board configuration file
Paul Gortmaker2738bc82009-09-20 20:36:06 -040027 * Please refer to doc/README.sbc8548 for more info.
Joe Hamman9e3ed392007-12-13 06:45:14 -060028 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
Paul Gortmaker2738bc82009-09-20 20:36:06 -040032/*
33 * Top level Makefile configuration choices
34 */
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020035#ifdef CONFIG_PCI
Paul Gortmaker2738bc82009-09-20 20:36:06 -040036#define CONFIG_PCI1
37#endif
38
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020039#ifdef CONFIG_66
Paul Gortmaker2738bc82009-09-20 20:36:06 -040040#define CONFIG_SYS_CLK_DIV 1
41#endif
42
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020043#ifdef CONFIG_33
Paul Gortmaker2738bc82009-09-20 20:36:06 -040044#define CONFIG_SYS_CLK_DIV 2
45#endif
46
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020047#ifdef CONFIG_PCIE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040048#define CONFIG_PCIE1
49#endif
50
51/*
52 * High Level Configuration Options
53 */
Joe Hamman9e3ed392007-12-13 06:45:14 -060054#define CONFIG_BOOKE 1 /* BOOKE */
55#define CONFIG_E500 1 /* BOOKE e500 family */
56#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
57#define CONFIG_MPC8548 1 /* MPC8548 specific */
58#define CONFIG_SBC8548 1 /* SBC8548 board specific */
59
Wolfgang Denk2ae18242010-10-06 09:05:45 +020060#ifndef CONFIG_SYS_TEXT_BASE
61#define CONFIG_SYS_TEXT_BASE 0xfffa0000
62#endif
63
Joe Hamman9e3ed392007-12-13 06:45:14 -060064#undef CONFIG_RIO
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040065
66#ifdef CONFIG_PCI
67#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
68#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
69#endif
70#ifdef CONFIG_PCIE1
71#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
72#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -060073
74#define CONFIG_TSEC_ENET /* tsec ethernet support */
75#define CONFIG_ENV_OVERWRITE
Joe Hamman9e3ed392007-12-13 06:45:14 -060076
Joe Hamman9e3ed392007-12-13 06:45:14 -060077#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
78
Kumar Galae2b159d2008-01-16 09:05:27 -060079#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060080
Paul Gortmaker2738bc82009-09-20 20:36:06 -040081/*
82 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
83 */
84#ifndef CONFIG_SYS_CLK_DIV
85#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
86#endif
87#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -060088
89/*
90 * These can be toggled for performance analysis, otherwise use default.
91 */
92#define CONFIG_L2_CACHE /* toggle L2 cache */
93#define CONFIG_BTB /* toggle branch predition */
Joe Hamman9e3ed392007-12-13 06:45:14 -060094
95/*
96 * Only possible on E500 Version 2 or newer cores.
97 */
98#define CONFIG_ENABLE_36BIT_PHYS 1
99
100#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
103#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
104#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600105
106/*
107 * Base addresses -- Note these are effective addresses where the
108 * actual resources get mapped (not physical addresses)
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
111#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
112#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
113#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600114
Kumar Gala33b90792008-08-26 23:15:28 -0500115/* DDR Setup */
116#define CONFIG_FSL_DDR2
117#undef CONFIG_FSL_DDR_INTERACTIVE
118#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
119#undef CONFIG_DDR_SPD
120#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600121
Kumar Gala33b90792008-08-26 23:15:28 -0500122#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
123#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
126#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala33b90792008-08-26 23:15:28 -0500127#define CONFIG_VERY_BIG_RAM
128
129#define CONFIG_NUM_DDR_CONTROLLERS 1
130#define CONFIG_DIMM_SLOTS_PER_CTLR 1
131#define CONFIG_CHIP_SELECTS_PER_CTRL 2
132
133/* I2C addresses of SPD EEPROMs */
134#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600135
136/*
137 * Make sure required options are set
138 */
139#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600141#endif
142
143#undef CONFIG_CLOCKS_IN_MHZ
144
145/*
146 * FLASH on the Local Bus
147 * Two banks, one 8MB the other 64MB, using the CFI driver.
148 * Boot from BR0/OR0 bank at 0xff80_0000
149 * Alternate BR6/OR6 bank at 0xfb80_0000
150 *
151 * BR0:
152 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
153 * Port Size = 8 bits = BRx[19:20] = 01
154 * Use GPCM = BRx[24:26] = 000
155 * Valid = BRx[31] = 1
156 *
157 * 0 4 8 12 16 20 24 28
158 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0
159 *
160 * BR6:
161 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
162 * Port Size = 32 bits = BRx[19:20] = 11
163 * Use GPCM = BRx[24:26] = 000
164 * Valid = BRx[31] = 1
165 *
166 * 0 4 8 12 16 20 24 28
167 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6
168 *
169 * OR0:
170 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
171 * XAM = OR0[17:18] = 11
172 * CSNT = OR0[20] = 1
173 * ACS = half cycle delay = OR0[21:22] = 11
174 * SCY = 6 = OR0[24:27] = 0110
175 * TRLX = use relaxed timing = OR0[29] = 1
176 * EAD = use external address latch delay = OR0[31] = 1
177 *
178 * 0 4 8 12 16 20 24 28
179 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0
180 *
181 * OR6:
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400182 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600183 * XAM = OR6[17:18] = 11
184 * CSNT = OR6[20] = 1
185 * ACS = half cycle delay = OR6[21:22] = 11
186 * SCY = 6 = OR6[24:27] = 0110
187 * TRLX = use relaxed timing = OR6[29] = 1
188 * EAD = use external address latch delay = OR6[31] = 1
189 *
190 * 0 4 8 12 16 20 24 28
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400191 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6
Joe Hamman9e3ed392007-12-13 06:45:14 -0600192 */
193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400195#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_BR0_PRELIM 0xff800801
199#define CONFIG_SYS_BR6_PRELIM 0xfb801801
Joe Hamman9e3ed392007-12-13 06:45:14 -0600200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_OR0_PRELIM 0xff806e65
202#define CONFIG_SYS_OR6_PRELIM 0xf8006e65
Joe Hamman9e3ed392007-12-13 06:45:14 -0600203
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400204#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
205 CONFIG_SYS_ALT_FLASH}
206#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
207#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#undef CONFIG_SYS_FLASH_CHECKSUM
209#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
210#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600211
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200212#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600213
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200214#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_FLASH_CFI
216#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600217
218/* CS5 = Local bus peripherals controlled by the EPLD */
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_BR5_PRELIM 0xf8000801
221#define CONFIG_SYS_OR5_PRELIM 0xff006e65
222#define CONFIG_SYS_EPLD_BASE 0xf8000000
223#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
224#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
225#define CONFIG_SYS_BD_REV 0xf8300000
226#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600227
228/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400229 * SDRAM on the Local Bus (CS3 and CS4)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600230 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400232#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600233
234/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400235 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600237 *
238 * For BR3, need:
239 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
240 * port-size = 32-bits = BR2[19:20] = 11
241 * no parity checking = BR2[21:22] = 00
242 * SDRAM for MSEL = BR2[24:26] = 011
243 * Valid = BR[31] = 1
244 *
245 * 0 4 8 12 16 20 24 28
246 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
247 *
248 */
249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_BR3_PRELIM 0xf0001861
Joe Hamman9e3ed392007-12-13 06:45:14 -0600251
252/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400253 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600254 *
255 * For OR3, need:
256 * 64MB mask for AM, OR3[0:7] = 1111 1100
257 * XAM, OR3[17:18] = 11
258 * 10 columns OR3[19-21] = 011
259 * 12 rows OR3[23-25] = 011
260 * EAD set for extra time OR[31] = 0
261 *
262 * 0 4 8 12 16 20 24 28
263 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
264 */
265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600267
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400268/*
269 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
270 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
271 *
272 * For BR4, need:
273 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
274 * port-size = 32-bits = BR2[19:20] = 11
275 * no parity checking = BR2[21:22] = 00
276 * SDRAM for MSEL = BR2[24:26] = 011
277 * Valid = BR[31] = 1
278 *
279 * 0 4 8 12 16 20 24 28
280 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
281 *
282 */
283
284#define CONFIG_SYS_BR4_PRELIM 0xf4001861
285
286/*
287 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
288 *
289 * For OR4, need:
290 * 64MB mask for AM, OR3[0:7] = 1111 1100
291 * XAM, OR3[17:18] = 11
292 * 10 columns OR3[19-21] = 011
293 * 12 rows OR3[23-25] = 011
294 * EAD set for extra time OR[31] = 0
295 *
296 * 0 4 8 12 16 20 24 28
297 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
298 */
299
300#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
303#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
304#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
305#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600306
307/*
Joe Hamman9e3ed392007-12-13 06:45:14 -0600308 * Common settings for all Local Bus SDRAM commands.
309 * At run time, either BSMA1516 (for CPU 1.1)
310 * or BSMA1617 (for CPU 1.0) (old)
311 * is OR'ed in too.
312 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500313#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
314 | LSDMR_PRETOACT7 \
315 | LSDMR_ACTTORW7 \
316 | LSDMR_BL8 \
317 | LSDMR_WRC4 \
318 | LSDMR_CL3 \
319 | LSDMR_RFEN \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600320 )
321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_INIT_RAM_LOCK 1
323#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200324#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600327
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200328#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hamman9e3ed392007-12-13 06:45:14 -0600330
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400331/*
332 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200333 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400334 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200335 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400336 * thing for MONITOR_LEN in both cases.
337 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200338#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600340
341/* Serial Port */
342#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_NS16550
344#define CONFIG_SYS_NS16550_SERIAL
345#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Gortmaker2738bc82009-09-20 20:36:06 -0400346#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600347
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600349 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
352#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600353
354/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_HUSH_PARSER
356#ifdef CONFIG_SYS_HUSH_PARSER
357#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Joe Hamman9e3ed392007-12-13 06:45:14 -0600358#endif
359
360/* pass open firmware flat tree */
361#define CONFIG_OF_LIBFDT 1
362#define CONFIG_OF_BOARD_SETUP 1
363#define CONFIG_OF_STDOUT_VIA_ALIAS 1
364
365/*
366 * I2C
367 */
368#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
369#define CONFIG_HARD_I2C /* I2C with hardware support*/
370#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
372#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
373#define CONFIG_SYS_I2C_SLAVE 0x7F
374#define CONFIG_SYS_I2C_OFFSET 0x3000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600375
376/*
377 * General PCI
378 * Memory space is mapped 1-1, but I/O space must start from 0.
379 */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400380#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600382
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400383#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
384#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
385#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400387#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
388#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
389#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
390#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600391
392#ifdef CONFIG_PCIE1
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400393#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
394#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
395#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400397#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
398#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
399#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
400#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600401#endif
402
403#ifdef CONFIG_RIO
404/*
405 * RapidIO MMU
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
408#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600409#endif
410
Joe Hamman9e3ed392007-12-13 06:45:14 -0600411#if defined(CONFIG_PCI)
412
413#define CONFIG_NET_MULTI
414#define CONFIG_PCI_PNP /* do pci plug-and-play */
415
416#undef CONFIG_EEPRO100
417#undef CONFIG_TULIP
418
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400419#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600420
Joe Hamman9e3ed392007-12-13 06:45:14 -0600421#endif /* CONFIG_PCI */
422
423
424#if defined(CONFIG_TSEC_ENET)
425
426#ifndef CONFIG_NET_MULTI
427#define CONFIG_NET_MULTI 1
428#endif
429
430#define CONFIG_MII 1 /* MII PHY management */
431#define CONFIG_TSEC1 1
432#define CONFIG_TSEC1_NAME "eTSEC0"
433#define CONFIG_TSEC2 1
434#define CONFIG_TSEC2_NAME "eTSEC1"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600435#undef CONFIG_MPC85XX_FEC
436
Paul Gortmaker58da8892008-12-11 15:47:50 -0500437#define TSEC1_PHY_ADDR 0x19
438#define TSEC2_PHY_ADDR 0x1a
Joe Hamman9e3ed392007-12-13 06:45:14 -0600439
440#define TSEC1_PHYIDX 0
441#define TSEC2_PHYIDX 0
Paul Gortmakerbd931052008-12-11 15:47:49 -0500442
Joe Hamman9e3ed392007-12-13 06:45:14 -0600443#define TSEC1_FLAGS TSEC_GIGABIT
444#define TSEC2_FLAGS TSEC_GIGABIT
Joe Hamman9e3ed392007-12-13 06:45:14 -0600445
446/* Options are: eTSEC[0-3] */
447#define CONFIG_ETHPRIME "eTSEC0"
448#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
449#endif /* CONFIG_TSEC_ENET */
450
451/*
452 * Environment
453 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200454#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200455#define CONFIG_ENV_SIZE 0x2000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200456#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400457#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
458#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200459#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400460#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
461#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
462#else
463#warning undefined environment size/location.
464#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -0600465
466#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600468
469/*
470 * BOOTP options
471 */
472#define CONFIG_BOOTP_BOOTFILESIZE
473#define CONFIG_BOOTP_BOOTPATH
474#define CONFIG_BOOTP_GATEWAY
475#define CONFIG_BOOTP_HOSTNAME
476
477
478/*
479 * Command line configuration.
480 */
481#include <config_cmd_default.h>
482
483#define CONFIG_CMD_PING
484#define CONFIG_CMD_I2C
485#define CONFIG_CMD_MII
486#define CONFIG_CMD_ELF
Becky Bruce199e2622010-06-17 11:37:25 -0500487#define CONFIG_CMD_REGINFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600488
489#if defined(CONFIG_PCI)
490 #define CONFIG_CMD_PCI
491#endif
492
493
494#undef CONFIG_WATCHDOG /* watchdog disabled */
495
496/*
497 * Miscellaneous configurable options
498 */
Paul Gortmakerad22f922008-12-11 15:47:51 -0500499#define CONFIG_CMDLINE_EDITING /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500500#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_LONGHELP /* undef to save memory */
502#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
503#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600504#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600506#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600508#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
510#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
511#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
512#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600513
514/*
515 * For booting Linux, the board info and command line data
516 * have to be in the first 8 MB of memory, since this is
517 * the maximum mapped by the Linux kernel during initialization.
518 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600520
Joe Hamman9e3ed392007-12-13 06:45:14 -0600521#if defined(CONFIG_CMD_KGDB)
522#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
523#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
524#endif
525
526/*
527 * Environment Configuration
528 */
529
530/* The mac addresses for all ethernet interface */
531#if defined(CONFIG_TSEC_ENET)
532#define CONFIG_HAS_ETH0
533#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
534#define CONFIG_HAS_ETH1
535#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600536#endif
537
538#define CONFIG_IPADDR 192.168.0.55
539
540#define CONFIG_HOSTNAME sbc8548
541#define CONFIG_ROOTPATH /opt/eldk/ppc_85xx
542#define CONFIG_BOOTFILE /uImage
543#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
544
545#define CONFIG_SERVERIP 192.168.0.2
546#define CONFIG_GATEWAYIP 192.168.0.1
547#define CONFIG_NETMASK 255.255.255.0
548
549#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
550
551#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
552#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
553
554#define CONFIG_BAUDRATE 115200
555
556#define CONFIG_EXTRA_ENV_SETTINGS \
557 "netdev=eth0\0" \
558 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
559 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200560 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
561 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
562 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
563 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
564 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600565 "consoledev=ttyS0\0" \
566 "ramdiskaddr=2000000\0" \
567 "ramdiskfile=uRamdisk\0" \
568 "fdtaddr=c00000\0" \
569 "fdtfile=sbc8548.dtb\0"
570
571#define CONFIG_NFSBOOTCOMMAND \
572 "setenv bootargs root=/dev/nfs rw " \
573 "nfsroot=$serverip:$rootpath " \
574 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
575 "console=$consoledev,$baudrate $othbootargs;" \
576 "tftp $loadaddr $bootfile;" \
577 "tftp $fdtaddr $fdtfile;" \
578 "bootm $loadaddr - $fdtaddr"
579
580
581#define CONFIG_RAMBOOTCOMMAND \
582 "setenv bootargs root=/dev/ram rw " \
583 "console=$consoledev,$baudrate $othbootargs;" \
584 "tftp $ramdiskaddr $ramdiskfile;" \
585 "tftp $loadaddr $bootfile;" \
586 "tftp $fdtaddr $fdtfile;" \
587 "bootm $loadaddr $ramdiskaddr $fdtaddr"
588
589#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
590
591#endif /* __CONFIG_H */