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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 13d46ab2572c0283d34f93bebc9a41295ef84ca5 / . / cpu / mcf52x2 / start.S
blob: 0dd4de5160c0d209de8564cd301100bb8a24d488 [file] [log] [blame]
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <config.h>
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]25#include <timestamp.h>
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]26#include "version.h"
27
28#ifndef CONFIG_IDENT_STRING
29#define CONFIG_IDENT_STRING ""
30#endif
31
32
33#define _START _start
34#define _FAULT _fault
35
36
37#define SAVE_ALL \
38 move.w #0x2700,%sr; /* disable intrs */ \
39 subl #60,%sp; /* space for 15 regs */ \
40 moveml %d0-%d7/%a0-%a6,%sp@; \
41
42#define RESTORE_ALL \
43 moveml %sp@,%d0-%d7/%a0-%a6; \
44 addl #60,%sp; /* space for 15 regs */ \
45 rte
46
47/* If we come from a pre-loader we don't need an initial exception
48 * table.
49 */
50#if !defined(CONFIG_MONITOR_IS_IN_RAM)
51
52.text
53/*
54 * Vector table. This is used for initial platform startup.
55 * These vectors are to catch any un-intended traps.
56 */
57_vectors:
58
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]59.long 0x00000000 /* Flash offset is 0 until we setup CS0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]60#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]61.long _start - TEXT_BASE
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]62#else
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]63.long _START
Zachary P. Landaueacbd312006-01-26 17:35:56 -0500[diff] [blame]64#endif
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]65
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74
75.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83
84.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92
93.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101
102#endif
103
104 .text
105
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]107#if defined(CONFIG_SYS_INT_FLASH_BASE) && \
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]108 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]109 #if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]110 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
111 .long 0xFFFFFFFF /* all sectors protected */
112 .long 0x00000000 /* supervisor/User restriction */
113 .long 0x00000000 /* programm/data space restriction */
114 .long 0x00000000 /* Flash security */
115 #endif
116#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]117 .globl _start
118_start:
119 nop
120 nop
121 move.w #0x2700,%sr
122
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]123#if defined(CONFIG_M5208)
124 /* Initialize RAMBAR: locate SRAM and validate it */
125 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
126 movec %d0, %RAMBAR1
127#endif
128
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]129#if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]130 move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]131 move.c %d0, %MBAR
132
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]133 /*** The 5249 has MBAR2 as well ***/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]134#ifdef CONFIG_SYS_MBAR2
135 move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]136 movec %d0, #0xc0e /* Set MBAR2 */
137#endif
138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]139 move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]140 movec %d0, %RAMBAR0
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]141#endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]142
Wolfgang Denk4176c792006-06-10 19:27:47 +0200[diff] [blame]143#if defined(CONFIG_M5282) || defined(CONFIG_M5271)
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]144 /* Initialize IPSBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]145 move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]146 move.l %d0, 0x40000000
147
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]148 /* Initialize RAMBAR1: locate SRAM and validate it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]149 move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]150 movec %d0, %RAMBAR1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]151
Bartlomiej Siekadaa6e412006-12-20 00:27:32 +0100[diff] [blame]152#if defined(CONFIG_M5282)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]153#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]154 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]156 move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0
157 move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1
158 move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]159_copy_flash:
160 move.l (%a0)+, (%a2)+
161 cmp.l %a0, %a1
162 bgt.s _copy_flash
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]163 jmp CONFIG_SYS_INIT_RAM_ADDR
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]164
165_flashbar_setup:
166 /* Initialize FLASHBAR: locate internal Flash and validate it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]167 move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
TsiChung Liew43d60642008-03-13 14:26:32 -0500[diff] [blame]168 movec %d0, %FLASHBAR
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]169 jmp _after_flashbar_copy.L /* Force jump to absolute address */
170_flashbar_setup_end:
171 nop
172_after_flashbar_copy:
173#else
174 /* Setup code to initialize FLASHBAR, if start from external Memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]175 move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0
TsiChung Liew4cb4e652008-08-11 15:54:25 +0000[diff] [blame]176 movec %d0, %FLASHBAR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]177#endif /* (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) */
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]178
179#endif
Wolfgang Denk6741ae92006-09-04 01:03:57 +0200[diff] [blame]180#endif
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]181 /* if we come from a pre-loader we have no exception table and
182 * therefore no VBR to set
183 */
184#if !defined(CONFIG_MONITOR_IS_IN_RAM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]185#if defined(CONFIG_M5282) && (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
186 move.l #CONFIG_SYS_INT_FLASH_BASE, %d0
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]187#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]188 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew2acefa72007-10-25 17:09:17 -0500[diff] [blame]189#endif
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]190 movec %d0, %VBR
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]191#endif
192
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]193#ifdef CONFIG_M5275
194 /* Initialize IPSBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]195 move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]196 move.l %d0, 0x40000000
197/* movec %d0, %MBAR */
198
199 /* Initialize RAMBAR: locate SRAM and validate it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]200 move.l #(CONFIG_SYS_INIT_RAM_ADDR + 0x21), %d0
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]201 movec %d0, %RAMBAR1
202#endif
203
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]204 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]205 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]206 clr.l %sp@-
207
208 move.l #__got_start, %a5 /* put relocation table address to a5 */
209
210 bsr cpu_init_f /* run low-level CPU init code (from flash) */
211 bsr board_init_f /* run low-level board init code (from flash) */
212
Marian Balakowicz6f5155a2006-05-09 11:51:51 +0200[diff] [blame]213 /* board_init_f() does not return */
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]214
215/*------------------------------------------------------------------------------*/
216
217/*
218 * void relocate_code (addr_sp, gd, addr_moni)
219 *
220 * This "function" does not return, instead it continues in RAM
221 * after relocating the monitor code.
222 *
223 * r3 = dest
224 * r4 = src
225 * r5 = length in bytes
226 * r6 = cachelinesize
227 */
228 .globl relocate_code
229relocate_code:
230 link.w %a6,#0
231 move.l 8(%a6), %sp /* set new stack pointer */
232
233 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
234 move.l 16(%a6), %a0 /* Save copy of Destination Address */
235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]236 move.l #CONFIG_SYS_MONITOR_BASE, %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]237 move.l #__init_end, %a2
238 move.l %a0, %a3
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]239 /* copy the code to RAM */
2401:
241 move.l (%a1)+, (%a3)+
242 cmp.l %a1,%a2
243 bgt.s 1b
244
245/*
246 * We are done. Do not return, instead branch to second part of board
247 * initialization, now running from RAM.
248 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]249 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]250 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]251 jmp (%a1)
252
253in_ram:
254
255clear_bss:
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]256 /*
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]257 * Now clear BSS segment
258 */
259 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]260 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]261 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]262 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]2636:
264 clr.l (%a1)+
265 cmp.l %a1,%d1
266 bgt.s 6b
267
268 /*
269 * fix got table in RAM
270 */
271 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]272 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]273 move.l %a1,%a5 /* * fix got pointer register a5 */
274
275 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]276 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]277
2787:
279 move.l (%a1),%d1
280 sub.l #_start,%d1
281 add.l %a0,%d1
282 move.l %d1,(%a1)+
283 cmp.l %a2, %a1
284 bne 7b
285
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]286#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
287 /* patch the 3 accesspoints to 3 ichache_state */
288 /* quick and dirty */
289
290 move.l %a0,%d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]291 add.l #(icache_state - CONFIG_SYS_MONITOR_BASE),%d1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]292 move.l %a0,%a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]293 add.l #(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]294 move.l %d1,(%a1)
295 move.l %a0,%a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]296 add.l #(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]297 move.l %d1,(%a1)
298 move.l %a0,%a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]299 add.l #(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]300 move.l %d1,(%a1)
301#endif
302
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]303 /* calculate relative jump to board_init_r in ram */
304 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]305 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]306
307 /* set parameters for board_init_r */
308 move.l %a0,-(%sp) /* dest_addr */
309 move.l %d0,-(%sp) /* gd */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]310#if defined(DEBUG) && (TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \
311 defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP)
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]312 halt
313#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]314 jsr (%a1)
315
316/*------------------------------------------------------------------------------*/
317/* exception code */
318 .globl _fault
319_fault:
320 jmp _fault
321
322 .globl _exc_handler
323_exc_handler:
324 SAVE_ALL
325 movel %sp,%sp@-
326 bsr exc_handler
327 addql #4,%sp
328 RESTORE_ALL
329
330 .globl _int_handler
331_int_handler:
332 SAVE_ALL
333 movel %sp,%sp@-
334 bsr int_handler
335 addql #4,%sp
336 RESTORE_ALL
337
338/*------------------------------------------------------------------------------*/
339/* cache functions */
TsiChung Liewbf9a5212009-06-12 11:29:00 +0000[diff] [blame]340#ifdef CONFIG_M5208
341 .globl icache_enable
342icache_enable:
343 move.l #0x01000000, %d0 /* Invalidate cache cmd */
344 movec %d0, %CACR /* Invalidate cache */
345 move.l #(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0 /* Setup cache mask */
346 movec %d0, %ACR0 /* Enable cache */
347
348 move.l #0x80000200, %d0 /* Setup cache mask */
349 movec %d0, %CACR /* Enable cache */
350 nop
351
352 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
353 moveq #1, %d0
354 move.l %d0, (%a1)
355 rts
356#endif
357
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]358#ifdef CONFIG_M5271
359 .globl icache_enable
360icache_enable:
361 move.l #0x01000000, %d0 /* Invalidate cache cmd */
362 movec %d0, %CACR /* Invalidate cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]363 move.l #(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]364 movec %d0, %ACR0 /* Enable cache */
365
366 move.l #0x80000200, %d0 /* Setup cache mask */
367 movec %d0, %CACR /* Enable cache */
368 nop
369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]370 move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]371 moveq #1, %d0
372 move.l %d0, (%a1)
373 rts
374#endif
375
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]376#ifdef CONFIG_M5272
377 .globl icache_enable
378icache_enable:
379 move.l #0x01000000, %d0 /* Invalidate cache cmd */
380 movec %d0, %CACR /* Invalidate cache */
381 move.l #0x0000c000, %d0 /* Setup cache mask */
382 movec %d0, %ACR0 /* Enable cache */
383 move.l #0xff00c000, %d0 /* Setup cache mask */
384 movec %d0, %ACR1 /* Enable cache */
385 move.l #0x80000100, %d0 /* Setup cache mask */
386 movec %d0, %CACR /* Enable cache */
387 moveq #1, %d0
388 move.l %d0, icache_state
389 rts
390#endif
391
Matthew Fettkef71d9d92008-02-04 15:38:20 -0600[diff] [blame]392#if defined(CONFIG_M5275)
393/*
394 * Instruction cache only
395 */
396 .globl icache_enable
397icache_enable:
398 move.l #0x01400000, %d0 /* Invalidate cache cmd */
399 movec %d0, %CACR /* Invalidate cache */
400 move.l #0x0000c000, %d0 /* Setup SDRAM caching */
401 movec %d0, %ACR0 /* Enable cache */
402 move.l #0x00000000, %d0 /* No other caching */
403 movec %d0, %ACR1 /* Enable cache */
404 move.l #0x80400100, %d0 /* Setup cache mask */
405 movec %d0, %CACR /* Enable cache */
406 moveq #1, %d0
407 move.l %d0, icache_state
408 rts
409#endif
410
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]411#ifdef CONFIG_M5282
412 .globl icache_enable
413icache_enable:
414 move.l #0x01000000, %d0 /* Invalidate cache cmd */
415 movec %d0, %CACR /* Invalidate cache */
416 move.l #0x0000c000, %d0 /* Setup cache mask */
417 movec %d0, %ACR0 /* Enable cache */
418 move.l #0xff00c000, %d0 /* Setup cache mask */
419 movec %d0, %ACR1 /* Enable cache */
420 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
421 movec %d0, %CACR /* Enable cache */
422 moveq #1, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]423icache_state_access_1:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]424 move.l %d0, icache_state
425 rts
426#endif
427
TsiChungLiewa1436a82007-08-16 13:20:50 -0500[diff] [blame]428#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]429 .globl icache_enable
430icache_enable:
431 /*
432 * Note: The 5249 Documentation doesn't give a bit position for CINV!
433 * From the 5272 and the 5307 documentation, I have deduced that it is
434 * probably CACR[24]. Should someone say something to Motorola?
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200[diff] [blame]435 * ~Jeremy
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]436 */
437 move.l #0x01000000, %d0 /* Invalidate whole cache */
438 move.c %d0,%CACR
439 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
440 move.c %d0, %ACR0
441 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
442 move.c %d0, %ACR1
443 move.l #0x90000200, %d0 /* Set cache enable cmd */
444 move.c %d0,%CACR
445 moveq #1, %d0
446 move.l %d0, icache_state
447 rts
448#endif
449
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]450 .globl icache_disable
451icache_disable:
452 move.l #0x00000100, %d0 /* Setup cache mask */
453 movec %d0, %CACR /* Enable cache */
454 clr.l %d0 /* Setup cache mask */
455 movec %d0, %ACR0 /* Enable cache */
456 movec %d0, %ACR1 /* Enable cache */
457 moveq #0, %d0
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]458icache_state_access_2:
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]459 move.l %d0, icache_state
460 rts
461
462 .globl icache_status
463icache_status:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]464icache_state_access_3:
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]465 move.l #(icache_state), %a0
466 move.l (%a0), %d0
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]467 rts
468
469 .data
470icache_state:
Heiko Schocher9acb6262006-04-20 08:42:42 +0200[diff] [blame]471 .long 0 /* cache is diabled on inirialization */
stroese8c725b92004-12-16 18:09:49 +0000[diff] [blame]472
TsiChungLiew83ec20b2007-08-15 19:21:21 -0500[diff] [blame]473 .globl dcache_enable
474dcache_enable:
475 /* dummy function */
476 rts
477
478 .globl dcache_disable
479dcache_disable:
480 /* dummy function */
481 rts
482
483 .globl dcache_status
484dcache_status:
485 /* dummy function */
486 rts
487
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]488/*------------------------------------------------------------------------------*/
489
490 .globl version_string
491version_string:
492 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -0600[diff] [blame]493 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
wdenkbf9e3b32004-02-12 00:47:09 +0000[diff] [blame]494 .ascii CONFIG_IDENT_STRING, "\0"
TsiChung Liew9b464322008-03-28 08:47:45 -0500[diff] [blame]495 .align 4