blob: 0d02279d5f8681af6240a1a57359c5d84a9f61dc [file] [log] [blame]
Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Jon Loeligercfc7a7f2007-08-02 14:42:20 -05002 * Copyright 2004, 2007 Freescale Semiconductor.
Jon Loeligerdebb7352006-04-26 17:58:56 -05003 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
25 *
26 *
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
32 */
33#include <config.h>
34#include <mpc86xx.h>
Peter Tyser561858e2008-11-03 09:30:59 -060035#include <timestamp.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050036#include <version.h>
37
38#include <ppc_asm.tmpl>
39#include <ppc_defs.h>
40
41#include <asm/cache.h>
42#include <asm/mmu.h>
43
Wolfgang Denk47a69892006-10-24 15:32:57 +020044#ifndef CONFIG_IDENT_STRING
45#define CONFIG_IDENT_STRING ""
Jon Loeligerdebb7352006-04-26 17:58:56 -050046#endif
47
Jon Loeligercfc7a7f2007-08-02 14:42:20 -050048/*
49 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
50 */
Jon Loeligerdebb7352006-04-26 17:58:56 -050051
52/*
53 * Set up GOT: Global Offset Table
54 *
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +010055 * Use r12 to access the GOT
Jon Loeligerdebb7352006-04-26 17:58:56 -050056 */
57 START_GOT
58 GOT_ENTRY(_GOT2_TABLE_)
59 GOT_ENTRY(_FIXUP_TABLE_)
60
61 GOT_ENTRY(_start)
62 GOT_ENTRY(_start_of_vectors)
63 GOT_ENTRY(_end_of_vectors)
64 GOT_ENTRY(transfer_to_handler)
65
66 GOT_ENTRY(__init_end)
67 GOT_ENTRY(_end)
68 GOT_ENTRY(__bss_start)
69 END_GOT
70
71/*
72 * r3 - 1st arg to board_init(): IMMP pointer
73 * r4 - 2nd arg to board_init(): boot flag
74 */
75 .text
Jon Loeligerffff3ae2006-08-22 12:06:18 -050076 .long 0x27051956 /* U-Boot Magic Number */
Jon Loeligerdebb7352006-04-26 17:58:56 -050077 .globl version_string
78version_string:
79 .ascii U_BOOT_VERSION
Peter Tyser561858e2008-11-03 09:30:59 -060080 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
Jon Loeligerdebb7352006-04-26 17:58:56 -050081 .ascii CONFIG_IDENT_STRING, "\0"
82
83 . = EXC_OFF_SYS_RESET
84 .globl _start
85_start:
Jon Loeligerdebb7352006-04-26 17:58:56 -050086 b boot_cold
Jon Loeligerdebb7352006-04-26 17:58:56 -050087
88 /* the boot code is located below the exception table */
89
90 .globl _start_of_vectors
91_start_of_vectors:
92
93/* Machine check */
94 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
95
96/* Data Storage exception. */
97 STD_EXCEPTION(0x300, DataStorage, UnknownException)
98
99/* Instruction Storage exception. */
100 STD_EXCEPTION(0x400, InstStorage, UnknownException)
101
102/* External Interrupt exception. */
103 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
104
105/* Alignment exception. */
106 . = 0x600
107Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200108 EXCEPTION_PROLOG(SRR0, SRR1)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500109 mfspr r4,DAR
110 stw r4,_DAR(r21)
111 mfspr r5,DSISR
112 stw r5,_DSISR(r21)
113 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100114 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500115
116/* Program check exception */
117 . = 0x700
118ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200119 EXCEPTION_PROLOG(SRR0, SRR1)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500120 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100121 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
122 MSR_KERNEL, COPY_EE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500123
124 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
125
126 /* I guess we could implement decrementer, and may have
127 * to someday for timekeeping.
128 */
129 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
130 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
131 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
132 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
133 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
134 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
135 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
136 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
137 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
138 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
139 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
140 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
141 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
142 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
143 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
144 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
145 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
146 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
147 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
148 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
149 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
150 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
151 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
152
153 .globl _end_of_vectors
154_end_of_vectors:
155
156 . = 0x2000
157
158boot_cold:
Becky Bruce1266df82008-11-03 15:44:01 -0600159 /*
160 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
161 * address specified by the BPTR
162 */
Jon Loeligercfc7a7f2007-08-02 14:42:20 -05001631:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#ifdef CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500165 /* disable everything */
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500166 li r0, 0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500167 mtspr HID0, r0
168 sync
169 mtmsr 0
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500170#endif
171
Dave Liudc2adad2008-10-28 17:46:12 +0800172 /* Invalidate BATs */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500173 bl invalidate_bats
174 sync
Dave Liudc2adad2008-10-28 17:46:12 +0800175 /* Invalidate all of TLB before MMU turn on */
176 bl clear_tlbs
177 sync
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#ifdef CONFIG_SYS_L2
Jon Loeligerdebb7352006-04-26 17:58:56 -0500180 /* init the L2 cache */
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500181 lis r3, L2_INIT@h
Jon Loeligerdebb7352006-04-26 17:58:56 -0500182 ori r3, r3, L2_INIT@l
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500183 mtspr l2cr, r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500184 /* invalidate the L2 cache */
185 bl l2cache_invalidate
186 sync
187#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500188
Jon Loeligerdebb7352006-04-26 17:58:56 -0500189 /*
190 * Calculate absolute address in FLASH and jump there
191 *------------------------------------------------------*/
Becky Brucebf9a8c32008-11-05 14:55:35 -0600192 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
193 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500194 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
195 mtlr r3
196 blr
197
198in_flash:
199 /* let the C-code set up the rest */
200 /* */
201 /* Be careful to keep code relocatable ! */
202 /*------------------------------------------------------*/
203 /* perform low-level init */
204
205 /* enable extended addressing */
206 bl enable_ext_addr
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500207
Jon Loeligerdebb7352006-04-26 17:58:56 -0500208 /* setup the bats */
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600209 bl early_bats
Jon Loeligerdebb7352006-04-26 17:58:56 -0500210
Jon Loeligerdebb7352006-04-26 17:58:56 -0500211 /*
212 * Cache must be enabled here for stack-in-cache trick.
213 * This means we need to enable the BATS.
214 * Cache should be turned on after BATs, since by default
215 * everything is write-through.
216 */
217
218 /* enable address translation */
Becky Brucec1e1cf62008-11-05 14:55:34 -0600219 mfmsr r5
220 ori r5, r5, (MSR_IR | MSR_DR)
221 lis r3,addr_trans_enabled@h
222 ori r3, r3, addr_trans_enabled@l
223 mtspr SPRN_SRR0,r3
224 mtspr SPRN_SRR1,r5
225 rfi
Jon Loeligerdebb7352006-04-26 17:58:56 -0500226
Becky Brucec1e1cf62008-11-05 14:55:34 -0600227addr_trans_enabled:
Jon Loeligerdebb7352006-04-26 17:58:56 -0500228 /* enable and invalidate the data cache */
229/* bl l1dcache_enable */
Wolfgang Denk47a69892006-10-24 15:32:57 +0200230 bl dcache_enable
Jon Loeligerdebb7352006-04-26 17:58:56 -0500231 sync
232
233#if 1
234 bl icache_enable
235#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#ifdef CONFIG_SYS_INIT_RAM_LOCK
Jon Loeligerdebb7352006-04-26 17:58:56 -0500238 bl lock_ram_in_cache
239 sync
240#endif
241
Becky Bruce3111d322008-11-06 17:37:35 -0600242#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
243 bl setup_ccsrbar
244#endif
245
Jon Loeligerdebb7352006-04-26 17:58:56 -0500246 /* set up the stack pointer in our newly created
247 * cache-ram (r1) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
249 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500250
Wolfgang Denk47a69892006-10-24 15:32:57 +0200251 li r0, 0 /* Make room for stack frame header and */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500252 stwu r0, -4(r1) /* clear final stack frame so that */
253 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
254
255 GET_GOT /* initialize GOT access */
256
Wolfgang Denk47a69892006-10-24 15:32:57 +0200257 /* run low-level CPU init code (from Flash) */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500258 bl cpu_init_f
259 sync
260
Wolfgang Denk47a69892006-10-24 15:32:57 +0200261#ifdef RUN_DIAG
Jon Loeligerdebb7352006-04-26 17:58:56 -0500262
Wolfgang Denk47a69892006-10-24 15:32:57 +0200263 /* Load PX_AUX register address in r4 */
Becky Brucec759a012008-11-06 17:36:04 -0600264 lis r4, PIXIS_BASE@h
Wolfgang Denk47a69892006-10-24 15:32:57 +0200265 ori r4, r4, 0x6
266 /* Load contents of PX_AUX in r3 bits 24 to 31*/
267 lbz r3, 0(r4)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500268
Wolfgang Denk47a69892006-10-24 15:32:57 +0200269 /* Mask and obtain the bit in r3 */
270 rlwinm. r3, r3, 0, 24, 24
271 /* If not zero, jump and continue with u-boot */
272 bne diag_done
Jon Loeligerdebb7352006-04-26 17:58:56 -0500273
Wolfgang Denk47a69892006-10-24 15:32:57 +0200274 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
275 lbz r3, 0(r4)
276 /* Set the MSB of the register value */
277 ori r3, r3, 0x80
278 /* Write value in r3 back to PX_AUX */
279 stb r3, 0(r4)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500280
Wolfgang Denk47a69892006-10-24 15:32:57 +0200281 /* Get the address to jump to in r3*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282 lis r3, CONFIG_SYS_DIAG_ADDR@h
283 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500284
Wolfgang Denk47a69892006-10-24 15:32:57 +0200285 /* Load the LR with the branch address */
286 mtlr r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500287
Wolfgang Denk47a69892006-10-24 15:32:57 +0200288 /* Branch to diagnostic */
289 blr
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500290
291diag_done:
292#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500293
Wolfgang Denk47a69892006-10-24 15:32:57 +0200294/* bl l2cache_enable */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500295
Wolfgang Denk47a69892006-10-24 15:32:57 +0200296 /* run 1st part of board init code (from Flash) */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500297 bl board_init_f
298 sync
299
Peter Tyser52ebd9c2010-09-14 19:13:53 -0500300 /* NOTREACHED - board_init_f() does not return */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500301
302 .globl invalidate_bats
303invalidate_bats:
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500304
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500305 li r0, 0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500306 /* invalidate BATs */
307 mtspr IBAT0U, r0
308 mtspr IBAT1U, r0
309 mtspr IBAT2U, r0
310 mtspr IBAT3U, r0
Wolfgang Denk47a69892006-10-24 15:32:57 +0200311 mtspr IBAT4U, r0
312 mtspr IBAT5U, r0
313 mtspr IBAT6U, r0
314 mtspr IBAT7U, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500315
316 isync
317 mtspr DBAT0U, r0
318 mtspr DBAT1U, r0
319 mtspr DBAT2U, r0
320 mtspr DBAT3U, r0
Wolfgang Denk47a69892006-10-24 15:32:57 +0200321 mtspr DBAT4U, r0
322 mtspr DBAT5U, r0
323 mtspr DBAT6U, r0
324 mtspr DBAT7U, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500325
326 isync
327 sync
328 blr
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500329
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600330/*
331 * early_bats:
332 *
333 * Set up bats needed early on - this is usually the BAT for the
Becky Bruce104992f2008-11-02 18:19:32 -0600334 * stack-in-cache, the Flash, and CCSR space
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600335 */
336 .globl early_bats
337early_bats:
Becky Bruce104992f2008-11-02 18:19:32 -0600338 /* IBAT 3 */
339 lis r4, CONFIG_SYS_IBAT3L@h
340 ori r4, r4, CONFIG_SYS_IBAT3L@l
341 lis r3, CONFIG_SYS_IBAT3U@h
342 ori r3, r3, CONFIG_SYS_IBAT3U@l
343 mtspr IBAT3L, r4
344 mtspr IBAT3U, r3
345 isync
346
347 /* DBAT 3 */
348 lis r4, CONFIG_SYS_DBAT3L@h
349 ori r4, r4, CONFIG_SYS_DBAT3L@l
350 lis r3, CONFIG_SYS_DBAT3U@h
351 ori r3, r3, CONFIG_SYS_DBAT3U@l
352 mtspr DBAT3L, r4
353 mtspr DBAT3U, r3
354 isync
355
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600356 /* IBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357 lis r4, CONFIG_SYS_IBAT5L@h
358 ori r4, r4, CONFIG_SYS_IBAT5L@l
359 lis r3, CONFIG_SYS_IBAT5U@h
360 ori r3, r3, CONFIG_SYS_IBAT5U@l
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600361 mtspr IBAT5L, r4
362 mtspr IBAT5U, r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500363 isync
364
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600365 /* DBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366 lis r4, CONFIG_SYS_DBAT5L@h
367 ori r4, r4, CONFIG_SYS_DBAT5L@l
368 lis r3, CONFIG_SYS_DBAT5U@h
369 ori r3, r3, CONFIG_SYS_DBAT5U@l
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600370 mtspr DBAT5L, r4
371 mtspr DBAT5U, r3
372 isync
Jon Loeligerdebb7352006-04-26 17:58:56 -0500373
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600374 /* IBAT 6 */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600375 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
376 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
377 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
378 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600379 mtspr IBAT6L, r4
380 mtspr IBAT6U, r3
381 isync
382
383 /* DBAT 6 */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600384 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
385 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
386 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
387 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600388 mtspr DBAT6L, r4
389 mtspr DBAT6U, r3
390 isync
Becky Bruce3111d322008-11-06 17:37:35 -0600391
392#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
393 /* IBAT 7 */
394 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
395 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
396 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
397 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
398 mtspr IBAT7L, r4
399 mtspr IBAT7U, r3
400 isync
401
402 /* DBAT 7 */
403 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
404 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
405 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
406 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
407 mtspr DBAT7L, r4
408 mtspr DBAT7U, r3
409 isync
410#endif
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600411 blr
412
413 .globl clear_tlbs
414clear_tlbs:
415 addis r3, 0, 0x0000
416 addis r5, 0, 0x4
417 isync
418tlblp:
419 tlbie r3
420 sync
421 addi r3, r3, 0x1000
422 cmp 0, 0, r3, r5
423 blt tlblp
Jon Loeligerdebb7352006-04-26 17:58:56 -0500424 blr
425
Jon Loeligerdebb7352006-04-26 17:58:56 -0500426 .globl disable_addr_trans
427disable_addr_trans:
428 /* disable address translation */
429 mflr r4
430 mfmsr r3
431 andi. r0, r3, (MSR_IR | MSR_DR)
432 beqlr
433 andc r3, r3, r0
434 mtspr SRR0, r4
435 mtspr SRR1, r3
436 rfi
437
438/*
439 * This code finishes saving the registers to the exception frame
440 * and jumps to the appropriate handler for the exception.
441 * Register r21 is pointer into trap frame, r1 has new stack pointer.
442 */
443 .globl transfer_to_handler
444transfer_to_handler:
445 stw r22,_NIP(r21)
446 lis r22,MSR_POW@h
447 andc r23,r23,r22
448 stw r23,_MSR(r21)
449 SAVE_GPR(7, r21)
450 SAVE_4GPRS(8, r21)
451 SAVE_8GPRS(12, r21)
452 SAVE_8GPRS(24, r21)
453 mflr r23
454 andi. r24,r23,0x3f00 /* get vector offset */
455 stw r24,TRAP(r21)
456 li r22,0
457 stw r22,RESULT(r21)
458 mtspr SPRG2,r22 /* r1 is now kernel sp */
459 lwz r24,0(r23) /* virtual address of handler */
460 lwz r23,4(r23) /* where to go when done */
461 mtspr SRR0,r24
462 mtspr SRR1,r20
463 mtlr r23
464 SYNC
465 rfi /* jump to handler, enable MMU */
466
467int_return:
468 mfmsr r28 /* Disable interrupts */
469 li r4,0
470 ori r4,r4,MSR_EE
471 andc r28,r28,r4
472 SYNC /* Some chip revs need this... */
473 mtmsr r28
474 SYNC
475 lwz r2,_CTR(r1)
476 lwz r0,_LINK(r1)
477 mtctr r2
478 mtlr r0
479 lwz r2,_XER(r1)
480 lwz r0,_CCR(r1)
481 mtspr XER,r2
482 mtcrf 0xFF,r0
483 REST_10GPRS(3, r1)
484 REST_10GPRS(13, r1)
485 REST_8GPRS(23, r1)
486 REST_GPR(31, r1)
487 lwz r2,_NIP(r1) /* Restore environment */
488 lwz r0,_MSR(r1)
489 mtspr SRR0,r2
490 mtspr SRR1,r0
491 lwz r0,GPR0(r1)
492 lwz r2,GPR2(r1)
493 lwz r1,GPR1(r1)
494 SYNC
495 rfi
496
497 .globl dc_read
498dc_read:
499 blr
500
501 .globl get_pvr
502get_pvr:
503 mfspr r3, PVR
504 blr
505
506 .globl get_svr
507get_svr:
508 mfspr r3, SVR
509 blr
510
511
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500512/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200513 * Function: in8
514 * Description: Input 8 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500515 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500516 .globl in8
517in8:
518 lbz r3,0x0000(r3)
519 blr
520
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500521/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200522 * Function: out8
523 * Description: Output 8 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500524 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500525 .globl out8
526out8:
527 stb r4,0x0000(r3)
528 blr
529
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500530/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200531 * Function: out16
532 * Description: Output 16 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500533 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500534 .globl out16
535out16:
536 sth r4,0x0000(r3)
537 blr
538
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500539/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200540 * Function: out16r
541 * Description: Byte reverse and output 16 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500542 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500543 .globl out16r
544out16r:
545 sthbrx r4,r0,r3
546 blr
547
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500548/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200549 * Function: out32
550 * Description: Output 32 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500551 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500552 .globl out32
553out32:
554 stw r4,0x0000(r3)
555 blr
556
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500557/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200558 * Function: out32r
559 * Description: Byte reverse and output 32 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500560 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500561 .globl out32r
562out32r:
563 stwbrx r4,r0,r3
564 blr
565
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500566/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200567 * Function: in16
568 * Description: Input 16 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500569 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500570 .globl in16
571in16:
572 lhz r3,0x0000(r3)
573 blr
574
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500575/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200576 * Function: in16r
577 * Description: Input 16 bits and byte reverse
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500578 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500579 .globl in16r
580in16r:
581 lhbrx r3,r0,r3
582 blr
583
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500584/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200585 * Function: in32
586 * Description: Input 32 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500587 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500588 .globl in32
589in32:
590 lwz 3,0x0000(3)
591 blr
592
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500593/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200594 * Function: in32r
595 * Description: Input 32 bits and byte reverse
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500596 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500597 .globl in32r
598in32r:
599 lwbrx r3,r0,r3
600 blr
601
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500602/*
Jon Loeligerdebb7352006-04-26 17:58:56 -0500603 * void relocate_code (addr_sp, gd, addr_moni)
604 *
605 * This "function" does not return, instead it continues in RAM
606 * after relocating the monitor code.
607 *
608 * r3 = dest
609 * r4 = src
610 * r5 = length in bytes
611 * r6 = cachelinesize
612 */
613 .globl relocate_code
614relocate_code:
615
Wolfgang Denk47a69892006-10-24 15:32:57 +0200616 mr r1, r3 /* Set new stack pointer */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500617 mr r9, r4 /* Save copy of Global Data pointer */
618 mr r10, r5 /* Save copy of Destination Address */
Haiying Wang67256672006-08-15 15:13:15 -0400619
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100620 GET_GOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500621 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200622 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
623 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500624 lwz r5, GOT(__init_end)
625 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500627
628 /*
629 * Fix GOT pointer:
630 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200631 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
Jon Loeligerdebb7352006-04-26 17:58:56 -0500632 *
633 * Offset:
634 */
635 sub r15, r10, r4
636
637 /* First our own GOT */
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100638 add r12, r12, r15
Jon Loeligerdebb7352006-04-26 17:58:56 -0500639 /* then the one used by the C code */
640 add r30, r30, r15
641
642 /*
643 * Now relocate code
644 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500645 cmplw cr1,r3,r4
646 addi r0,r5,3
647 srwi. r0,r0,2
648 beq cr1,4f /* In place copy is not necessary */
649 beq 7f /* Protect against 0 count */
650 mtctr r0
651 bge cr1,2f
652
653 la r8,-4(r4)
654 la r7,-4(r3)
6551: lwzu r0,4(r8)
656 stwu r0,4(r7)
657 bdnz 1b
658 b 4f
659
6602: slwi r0,r0,2
661 add r8,r4,r0
662 add r7,r3,r0
6633: lwzu r0,-4(r8)
664 stwu r0,-4(r7)
665 bdnz 3b
Jon Loeligerdebb7352006-04-26 17:58:56 -0500666/*
667 * Now flush the cache: note that we must start from a cache aligned
668 * address. Otherwise we might miss one cache line.
669 */
6704: cmpwi r6,0
671 add r5,r3,r5
672 beq 7f /* Always flush prefetch queue in any case */
673 subi r0,r6,1
674 andc r3,r3,r0
675 mr r4,r3
6765: dcbst 0,r4
677 add r4,r4,r6
678 cmplw r4,r5
679 blt 5b
680 sync /* Wait for all dcbst to complete on bus */
681 mr r4,r3
6826: icbi 0,r4
683 add r4,r4,r6
684 cmplw r4,r5
685 blt 6b
Wolfgang Denk47a69892006-10-24 15:32:57 +02006867: sync /* Wait for all icbi to complete on bus */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500687 isync
688
689/*
690 * We are done. Do not return, instead branch to second part of board
691 * initialization, now running from RAM.
692 */
693 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
694 mtlr r0
695 blr
696
697in_ram:
Jon Loeligerdebb7352006-04-26 17:58:56 -0500698 /*
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100699 * Relocation Function, r12 point to got2+0x8000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500700 *
701 * Adjust got2 pointers, no need to check for 0, this code
702 * already puts a few entries in the table.
703 */
704 li r0,__got2_entries@sectoff@l
705 la r3,GOT(_GOT2_TABLE_)
706 lwz r11,GOT(_GOT2_TABLE_)
707 mtctr r0
708 sub r11,r3,r11
709 addi r3,r3,-4
7101: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200711 cmpwi r0,0
712 beq- 2f
Jon Loeligerdebb7352006-04-26 17:58:56 -0500713 add r0,r0,r11
714 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02007152: bdnz 1b
Jon Loeligerdebb7352006-04-26 17:58:56 -0500716
717 /*
718 * Now adjust the fixups and the pointers to the fixups
719 * in case we need to move ourselves again.
720 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200721 li r0,__fixup_entries@sectoff@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500722 lwz r3,GOT(_FIXUP_TABLE_)
723 cmpwi r0,0
724 mtctr r0
725 addi r3,r3,-4
726 beq 4f
7273: lwzu r4,4(r3)
728 lwzux r0,r4,r11
729 add r0,r0,r11
730 stw r10,0(r3)
731 stw r0,0(r4)
732 bdnz 3b
7334:
734/* clear_bss: */
735 /*
736 * Now clear BSS segment
737 */
738 lwz r3,GOT(__bss_start)
739 lwz r4,GOT(_end)
740
741 cmplw 0, r3, r4
742 beq 6f
743
744 li r0, 0
7455:
746 stw r0, 0(r3)
747 addi r3, r3, 4
748 cmplw 0, r3, r4
749 bne 5b
7506:
Haiying Wang6cfea332006-05-10 09:38:06 -0500751 mr r3, r9 /* Init Date pointer */
752 mr r4, r10 /* Destination Address */
753 bl board_init_r
Jon Loeligerdebb7352006-04-26 17:58:56 -0500754
755 /* not reached - end relocate_code */
756/*-----------------------------------------------------------------------*/
757
758 /*
759 * Copy exception vector code to low memory
760 *
761 * r3: dest_addr
762 * r7: source address, r8: end address, r9: target address
763 */
764 .globl trap_init
765trap_init:
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100766 mflr r4 /* save link register */
767 GET_GOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500768 lwz r7, GOT(_start)
769 lwz r8, GOT(_end_of_vectors)
770
771 li r9, 0x100 /* reset vector always at 0x100 */
772
773 cmplw 0, r7, r8
774 bgelr /* return if r7>=r8 - just in case */
Jon Loeligerdebb7352006-04-26 17:58:56 -05007751:
776 lwz r0, 0(r7)
777 stw r0, 0(r9)
778 addi r7, r7, 4
779 addi r9, r9, 4
780 cmplw 0, r7, r8
781 bne 1b
782
783 /*
784 * relocate `hdlr' and `int_return' entries
785 */
786 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
787 li r8, Alignment - _start + EXC_OFF_SYS_RESET
7882:
789 bl trap_reloc
790 addi r7, r7, 0x100 /* next exception vector */
791 cmplw 0, r7, r8
792 blt 2b
793
794 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
795 bl trap_reloc
796
797 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
798 bl trap_reloc
799
800 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
801 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
8023:
803 bl trap_reloc
804 addi r7, r7, 0x100 /* next exception vector */
805 cmplw 0, r7, r8
806 blt 3b
807
808 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
809 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
8104:
811 bl trap_reloc
812 addi r7, r7, 0x100 /* next exception vector */
813 cmplw 0, r7, r8
814 blt 4b
815
816 /* enable execptions from RAM vectors */
817 mfmsr r7
818 li r8,MSR_IP
819 andc r7,r7,r8
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500820 ori r7,r7,MSR_ME /* Enable Machine Check */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500821 mtmsr r7
822
823 mtlr r4 /* restore link register */
824 blr
825
Jon Loeligerdebb7352006-04-26 17:58:56 -0500826.globl enable_ext_addr
827enable_ext_addr:
828 mfspr r0, HID0
Wolfgang Denk47a69892006-10-24 15:32:57 +0200829 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
Jon Loeligerdebb7352006-04-26 17:58:56 -0500830 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
Wolfgang Denk47a69892006-10-24 15:32:57 +0200831 mtspr HID0, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500832 sync
833 isync
834 blr
835
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200836#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500837.globl setup_ccsrbar
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500838setup_ccsrbar:
Jon Loeligerdebb7352006-04-26 17:58:56 -0500839 /* Special sequence needed to update CCSRBAR itself */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200840 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
841 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500842
Becky Bruce3111d322008-11-06 17:37:35 -0600843 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
844 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
845 srwi r5,r5,12
846 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
847 rlwimi r5,r6,20,8,11
848 stw r5, 0(r4) /* Store physical value of CCSR */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500849 isync
850
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200851 lis r5, CONFIG_SYS_TEXT_BASE@h
852 ori r5,r5,CONFIG_SYS_TEXT_BASE@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500853 lwz r5, 0(r5)
854 isync
855
Becky Bruce3111d322008-11-06 17:37:35 -0600856 /* Use VA of CCSR to do read */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200857 lis r3, CONFIG_SYS_CCSRBAR@h
858 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500859 isync
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500860
Jon Loeligerdebb7352006-04-26 17:58:56 -0500861 blr
862#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500863
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200864#ifdef CONFIG_SYS_INIT_RAM_LOCK
Jon Loeligerdebb7352006-04-26 17:58:56 -0500865lock_ram_in_cache:
866 /* Allocate Initial RAM in data cache.
867 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200868 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
869 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
870 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
871 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spence39243842008-08-28 14:09:15 -0700872 mtctr r4
Jon Loeligerdebb7352006-04-26 17:58:56 -05008731:
874 dcbz r0, r3
875 addi r3, r3, 32
876 bdnz 1b
877#if 1
878/* Lock the data cache */
879 mfspr r0, HID0
880 ori r0, r0, 0x1000
881 sync
882 mtspr HID0, r0
883 sync
884 blr
885#endif
886#if 0
887 /* Lock the first way of the data cache */
888 mfspr r0, LDSTCR
889 ori r0, r0, 0x0080
890#if defined(CONFIG_ALTIVEC)
891 dssall
892#endif
893 sync
894 mtspr LDSTCR, r0
895 sync
896 isync
897 blr
898#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500899
Jon Loeligerdebb7352006-04-26 17:58:56 -0500900.globl unlock_ram_in_cache
901unlock_ram_in_cache:
902 /* invalidate the INIT_RAM section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200903 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
904 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
905 li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
906 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spence39243842008-08-28 14:09:15 -0700907 mtctr r4
Jon Loeligerdebb7352006-04-26 17:58:56 -05009081: icbi r0, r3
909 addi r3, r3, 32
910 bdnz 1b
Wolfgang Denk47a69892006-10-24 15:32:57 +0200911 sync /* Wait for all icbi to complete on bus */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500912 isync
913#if 1
914/* Unlock the data cache and invalidate it */
Wolfgang Denk47a69892006-10-24 15:32:57 +0200915 mfspr r0, HID0
916 li r3,0x1000
917 andc r0,r0,r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500918 li r3,0x0400
919 or r0,r0,r3
920 sync
Wolfgang Denk47a69892006-10-24 15:32:57 +0200921 mtspr HID0, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500922 sync
923 blr
924#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500925#if 0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500926 /* Unlock the first way of the data cache */
Wolfgang Denk47a69892006-10-24 15:32:57 +0200927 mfspr r0, LDSTCR
928 li r3,0x0080
929 andc r0,r0,r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500930#ifdef CONFIG_ALTIVEC
931 dssall
932#endif
933 sync
Wolfgang Denk47a69892006-10-24 15:32:57 +0200934 mtspr LDSTCR, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500935 sync
936 isync
937 li r3,0x0400
938 or r0,r0,r3
939 sync
Wolfgang Denk47a69892006-10-24 15:32:57 +0200940 mtspr HID0, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500941 sync
942 blr
943#endif
944#endif