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Marek Vasut18a00df2010-03-07 23:35:48 +01001/*
Marek Vasutf9054322010-07-22 16:51:52 +02002 * Voipac PXA270 Support
Marek Vasut18a00df2010-03-07 23:35:48 +01003 *
Marek Vasutf9054322010-07-22 16:51:52 +02004 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
Marek Vasut18a00df2010-03-07 23:35:48 +01005 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Marek Vasut18a00df2010-03-07 23:35:48 +01007 */
8
9#include <common.h>
10#include <asm/arch/hardware.h>
Marek Vasut5d877f42011-08-28 06:30:40 +020011#include <asm/arch/regs-mmc.h>
Marek Vasut4438a452011-11-26 11:17:32 +010012#include <asm/arch/pxa.h>
Marek Vasutc7e61332010-08-08 15:55:51 +020013#include <netdev.h>
Marek Vasut3ba8bf72010-09-09 09:50:39 +020014#include <serial.h>
15#include <asm/io.h>
Mateusz Zalega16297cf2013-10-04 19:22:26 +020016#include <usb.h>
Marek Vasut18a00df2010-03-07 23:35:48 +010017
18DECLARE_GLOBAL_DATA_PTR;
19
Marek Vasut18a00df2010-03-07 23:35:48 +010020/*
21 * Miscelaneous platform dependent initialisations
22 */
Marek Vasutf9054322010-07-22 16:51:52 +020023int board_init(void)
Marek Vasut18a00df2010-03-07 23:35:48 +010024{
Marek Vasut720a6502010-09-28 15:50:49 +020025 /* We have RAM, disable cache */
26 dcache_disable();
27 icache_disable();
28
Marek Vasut18a00df2010-03-07 23:35:48 +010029 /* memory and cpu-speed are setup before relocation */
30 /* so we do _nothing_ here */
31
Marek Vasutf9054322010-07-22 16:51:52 +020032 /* Arch number of vpac270 */
Marek Vasut18a00df2010-03-07 23:35:48 +010033 gd->bd->bi_arch_number = MACH_TYPE_VPAC270;
34
35 /* adress of boot parameters */
36 gd->bd->bi_boot_params = 0xa0000100;
37
38 return 0;
39}
40
Marek Vasutf9054322010-07-22 16:51:52 +020041int dram_init(void)
Marek Vasut18a00df2010-03-07 23:35:48 +010042{
Marek Vasut411b9ea2011-10-31 14:17:21 +010043#ifndef CONFIG_ONENAND
Marek Vasutf68d2a22011-11-26 11:18:57 +010044 pxa2xx_dram_init();
Marek Vasut411b9ea2011-10-31 14:17:21 +010045#endif
Marek Vasut6ef6eb92010-09-23 09:46:57 +020046 gd->ram_size = PHYS_SDRAM_1_SIZE;
Marek Vasut6ef6eb92010-09-23 09:46:57 +020047 return 0;
48}
49
50void dram_init_banksize(void)
51{
Marek Vasut18a00df2010-03-07 23:35:48 +010052 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
Marek Vasut18a00df2010-03-07 23:35:48 +010053 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
Marek Vasut18a00df2010-03-07 23:35:48 +010054
Marek Vasutf97e9c62010-10-03 18:27:36 +020055#ifdef CONFIG_RAM_256M
Marek Vasutf9054322010-07-22 16:51:52 +020056 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
57 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
58#endif
Marek Vasut18a00df2010-03-07 23:35:48 +010059}
60
Marek Vasut5d877f42011-08-28 06:30:40 +020061#ifdef CONFIG_CMD_MMC
62int board_mmc_init(bd_t *bis)
63{
64 pxa_mmc_register(0);
65 return 0;
66}
67#endif
68
Marek Vasutf9054322010-07-22 16:51:52 +020069#ifdef CONFIG_CMD_USB
Mateusz Zalega16297cf2013-10-04 19:22:26 +020070int board_usb_init(int index, enum board_usb_init_type init)
Marek Vasut18a00df2010-03-07 23:35:48 +010071{
Marek Vasut3ba8bf72010-09-09 09:50:39 +020072 writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
73 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
74 UHCHR);
Marek Vasut18a00df2010-03-07 23:35:48 +010075
Marek Vasut3ba8bf72010-09-09 09:50:39 +020076 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
Marek Vasut18a00df2010-03-07 23:35:48 +010077
Marek Vasut3ba8bf72010-09-09 09:50:39 +020078 while (readl(UHCHR) & UHCHR_FSBIR)
79 ;
Marek Vasut18a00df2010-03-07 23:35:48 +010080
Marek Vasut3ba8bf72010-09-09 09:50:39 +020081 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
82 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
Marek Vasut18a00df2010-03-07 23:35:48 +010083
84 /* Clear any OTG Pin Hold */
Marek Vasut3ba8bf72010-09-09 09:50:39 +020085 if (readl(PSSR) & PSSR_OTGPH)
86 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
Marek Vasut18a00df2010-03-07 23:35:48 +010087
Marek Vasut3ba8bf72010-09-09 09:50:39 +020088 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
89 writel(readl(UHCRHDA) | 0x100, UHCRHDA);
Marek Vasut18a00df2010-03-07 23:35:48 +010090
91 /* Set port power control mask bits, only 3 ports. */
Marek Vasut3ba8bf72010-09-09 09:50:39 +020092 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
Marek Vasut18a00df2010-03-07 23:35:48 +010093
94 /* enable port 2 */
Marek Vasut3ba8bf72010-09-09 09:50:39 +020095 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
96 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
Marek Vasut18a00df2010-03-07 23:35:48 +010097
98 return 0;
99}
100
Mateusz Zalega16297cf2013-10-04 19:22:26 +0200101int board_usb_cleanup(int index, enum board_usb_init_type init)
Marek Vasut18a00df2010-03-07 23:35:48 +0100102{
Mateusz Zalega16297cf2013-10-04 19:22:26 +0200103 return 0;
Marek Vasut18a00df2010-03-07 23:35:48 +0100104}
105
106void usb_board_stop(void)
107{
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200108 writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
Marek Vasut18a00df2010-03-07 23:35:48 +0100109 udelay(11);
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200110 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
Marek Vasut18a00df2010-03-07 23:35:48 +0100111
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200112 writel(readl(UHCCOMS) | 1, UHCCOMS);
Marek Vasut18a00df2010-03-07 23:35:48 +0100113 udelay(10);
114
Marek Vasut3ba8bf72010-09-09 09:50:39 +0200115 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
Marek Vasut18a00df2010-03-07 23:35:48 +0100116
117 return;
118}
Marek Vasutf9054322010-07-22 16:51:52 +0200119#endif
Marek Vasut18a00df2010-03-07 23:35:48 +0100120
121#ifdef CONFIG_DRIVER_DM9000
122int board_eth_init(bd_t *bis)
123{
124 return dm9000_initialize(bis);
125}
126#endif