Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1 | /* |
| 2 | * cpu/ppc4xx/44x_spd_ddr2.c |
| 3 | * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a |
| 4 | * DDR2 controller (non Denali Core). Those are 440SP/SPe. |
| 5 | * |
| 6 | * (C) Copyright 2007 |
| 7 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 8 | * |
| 9 | * COPYRIGHT AMCC CORPORATION 2004 |
| 10 | * |
| 11 | * See file CREDITS for list of people who contributed to this |
| 12 | * project. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or |
| 15 | * modify it under the terms of the GNU General Public License as |
| 16 | * published by the Free Software Foundation; either version 2 of |
| 17 | * the License, or (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, write to the Free Software |
| 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 27 | * MA 02111-1307 USA |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | /* define DEBUG for debugging output (obviously ;-)) */ |
| 32 | #if 0 |
| 33 | #define DEBUG |
| 34 | #endif |
| 35 | |
| 36 | #include <common.h> |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 37 | #include <command.h> |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 38 | #include <ppc4xx.h> |
| 39 | #include <i2c.h> |
| 40 | #include <asm/io.h> |
| 41 | #include <asm/processor.h> |
| 42 | #include <asm/mmu.h> |
| 43 | |
| 44 | #if defined(CONFIG_SPD_EEPROM) && \ |
| 45 | (defined(CONFIG_440SP) || defined(CONFIG_440SPE)) |
| 46 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 47 | /*-----------------------------------------------------------------------------+ |
| 48 | * Defines |
| 49 | *-----------------------------------------------------------------------------*/ |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 50 | #ifndef TRUE |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 51 | #define TRUE 1 |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 52 | #endif |
| 53 | #ifndef FALSE |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 54 | #define FALSE 0 |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 55 | #endif |
| 56 | |
| 57 | #define SDRAM_DDR1 1 |
| 58 | #define SDRAM_DDR2 2 |
| 59 | #define SDRAM_NONE 0 |
| 60 | |
Wolfgang Denk | 1636d1c | 2007-06-22 23:59:00 +0200 | [diff] [blame^] | 61 | #define MAXDIMMS 2 |
| 62 | #define MAXRANKS 4 |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 63 | #define MAXBXCF 4 |
| 64 | #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ |
| 65 | |
| 66 | #define ONE_BILLION 1000000000 |
| 67 | |
| 68 | #define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) |
| 69 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 70 | #define CMD_NOP (7 << 19) |
| 71 | #define CMD_PRECHARGE (2 << 19) |
| 72 | #define CMD_REFRESH (1 << 19) |
| 73 | #define CMD_EMR (0 << 19) |
| 74 | #define CMD_READ (5 << 19) |
| 75 | #define CMD_WRITE (4 << 19) |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 76 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 77 | #define SELECT_MR (0 << 16) |
| 78 | #define SELECT_EMR (1 << 16) |
| 79 | #define SELECT_EMR2 (2 << 16) |
| 80 | #define SELECT_EMR3 (3 << 16) |
| 81 | |
| 82 | /* MR */ |
| 83 | #define DLL_RESET 0x00000100 |
| 84 | |
| 85 | #define WRITE_RECOV_2 (1 << 9) |
| 86 | #define WRITE_RECOV_3 (2 << 9) |
| 87 | #define WRITE_RECOV_4 (3 << 9) |
| 88 | #define WRITE_RECOV_5 (4 << 9) |
| 89 | #define WRITE_RECOV_6 (5 << 9) |
| 90 | |
| 91 | #define BURST_LEN_4 0x00000002 |
| 92 | |
| 93 | /* EMR */ |
| 94 | #define ODT_0_OHM 0x00000000 |
| 95 | #define ODT_50_OHM 0x00000044 |
| 96 | #define ODT_75_OHM 0x00000004 |
| 97 | #define ODT_150_OHM 0x00000040 |
| 98 | |
| 99 | #define ODS_FULL 0x00000000 |
| 100 | #define ODS_REDUCED 0x00000002 |
| 101 | |
| 102 | /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */ |
| 103 | #define ODT_EB0R (0x80000000 >> 8) |
| 104 | #define ODT_EB0W (0x80000000 >> 7) |
| 105 | #define CALC_ODT_R(n) (ODT_EB0R << (n << 1)) |
| 106 | #define CALC_ODT_W(n) (ODT_EB0W << (n << 1)) |
| 107 | #define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n)) |
| 108 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 109 | /* Defines for the Read Cycle Delay test */ |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 110 | #define NUMMEMTESTS 8 |
| 111 | #define NUMMEMWORDS 8 |
| 112 | #define NUMLOOPS 256 /* memory test loops */ |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 113 | |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 114 | #undef CONFIG_ECC_ERROR_RESET /* test-only: see description below, at check_ecc() */ |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 115 | |
| 116 | /* |
| 117 | * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory |
| 118 | * region. Right now the cache should still be disabled in U-Boot because of the |
| 119 | * EMAC driver, that need it's buffer descriptor to be located in non cached |
| 120 | * memory. |
| 121 | * |
| 122 | * If at some time this restriction doesn't apply anymore, just define |
| 123 | * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup |
| 124 | * everything correctly. |
| 125 | */ |
| 126 | #ifdef CFG_ENABLE_SDRAM_CACHE |
| 127 | #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ |
| 128 | #else |
| 129 | #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ |
| 130 | #endif |
| 131 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 132 | /* Private Structure Definitions */ |
| 133 | |
| 134 | /* enum only to ease code for cas latency setting */ |
| 135 | typedef enum ddr_cas_id { |
| 136 | DDR_CAS_2 = 20, |
| 137 | DDR_CAS_2_5 = 25, |
| 138 | DDR_CAS_3 = 30, |
| 139 | DDR_CAS_4 = 40, |
| 140 | DDR_CAS_5 = 50 |
| 141 | } ddr_cas_id_t; |
| 142 | |
| 143 | /*-----------------------------------------------------------------------------+ |
| 144 | * Prototypes |
| 145 | *-----------------------------------------------------------------------------*/ |
| 146 | static unsigned long sdram_memsize(void); |
Stefan Roese | dbca208 | 2007-06-14 11:14:32 +0200 | [diff] [blame] | 147 | void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 148 | static void get_spd_info(unsigned long *dimm_populated, |
| 149 | unsigned char *iic0_dimm_addr, |
| 150 | unsigned long num_dimm_banks); |
| 151 | static void check_mem_type(unsigned long *dimm_populated, |
| 152 | unsigned char *iic0_dimm_addr, |
| 153 | unsigned long num_dimm_banks); |
| 154 | static void check_frequency(unsigned long *dimm_populated, |
| 155 | unsigned char *iic0_dimm_addr, |
| 156 | unsigned long num_dimm_banks); |
| 157 | static void check_rank_number(unsigned long *dimm_populated, |
| 158 | unsigned char *iic0_dimm_addr, |
| 159 | unsigned long num_dimm_banks); |
| 160 | static void check_voltage_type(unsigned long *dimm_populated, |
| 161 | unsigned char *iic0_dimm_addr, |
| 162 | unsigned long num_dimm_banks); |
| 163 | static void program_memory_queue(unsigned long *dimm_populated, |
| 164 | unsigned char *iic0_dimm_addr, |
| 165 | unsigned long num_dimm_banks); |
| 166 | static void program_codt(unsigned long *dimm_populated, |
| 167 | unsigned char *iic0_dimm_addr, |
| 168 | unsigned long num_dimm_banks); |
| 169 | static void program_mode(unsigned long *dimm_populated, |
| 170 | unsigned char *iic0_dimm_addr, |
| 171 | unsigned long num_dimm_banks, |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 172 | ddr_cas_id_t *selected_cas, |
| 173 | int *write_recovery); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 174 | static void program_tr(unsigned long *dimm_populated, |
| 175 | unsigned char *iic0_dimm_addr, |
| 176 | unsigned long num_dimm_banks); |
| 177 | static void program_rtr(unsigned long *dimm_populated, |
| 178 | unsigned char *iic0_dimm_addr, |
| 179 | unsigned long num_dimm_banks); |
| 180 | static void program_bxcf(unsigned long *dimm_populated, |
| 181 | unsigned char *iic0_dimm_addr, |
| 182 | unsigned long num_dimm_banks); |
| 183 | static void program_copt1(unsigned long *dimm_populated, |
| 184 | unsigned char *iic0_dimm_addr, |
| 185 | unsigned long num_dimm_banks); |
| 186 | static void program_initplr(unsigned long *dimm_populated, |
| 187 | unsigned char *iic0_dimm_addr, |
| 188 | unsigned long num_dimm_banks, |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 189 | ddr_cas_id_t selected_cas, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 190 | int write_recovery); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 191 | static unsigned long is_ecc_enabled(void); |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 192 | #ifdef CONFIG_DDR_ECC |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 193 | static void program_ecc(unsigned long *dimm_populated, |
| 194 | unsigned char *iic0_dimm_addr, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 195 | unsigned long num_dimm_banks, |
| 196 | unsigned long tlb_word2_i_value); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 197 | static void program_ecc_addr(unsigned long start_address, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 198 | unsigned long num_bytes, |
| 199 | unsigned long tlb_word2_i_value); |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 200 | #endif |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 201 | static void program_DQS_calibration(unsigned long *dimm_populated, |
| 202 | unsigned char *iic0_dimm_addr, |
| 203 | unsigned long num_dimm_banks); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 204 | #ifdef HARD_CODED_DQS /* calibration test with hardvalues */ |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 205 | static void test(void); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 206 | #else |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 207 | static void DQS_calibration_process(void); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 208 | #endif |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 209 | #if defined(DEBUG) |
| 210 | static void ppc440sp_sdram_register_dump(void); |
| 211 | #endif |
| 212 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
| 213 | void dcbz_area(u32 start_address, u32 num_bytes); |
| 214 | void dflush(void); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 215 | |
| 216 | static u32 mfdcr_any(u32 dcr) |
| 217 | { |
| 218 | u32 val; |
| 219 | |
| 220 | switch (dcr) { |
| 221 | case SDRAM_R0BAS + 0: |
| 222 | val = mfdcr(SDRAM_R0BAS + 0); |
| 223 | break; |
| 224 | case SDRAM_R0BAS + 1: |
| 225 | val = mfdcr(SDRAM_R0BAS + 1); |
| 226 | break; |
| 227 | case SDRAM_R0BAS + 2: |
| 228 | val = mfdcr(SDRAM_R0BAS + 2); |
| 229 | break; |
| 230 | case SDRAM_R0BAS + 3: |
| 231 | val = mfdcr(SDRAM_R0BAS + 3); |
| 232 | break; |
| 233 | default: |
| 234 | printf("DCR %d not defined in case statement!!!\n", dcr); |
| 235 | val = 0; /* just to satisfy the compiler */ |
| 236 | } |
| 237 | |
| 238 | return val; |
| 239 | } |
| 240 | |
| 241 | static void mtdcr_any(u32 dcr, u32 val) |
| 242 | { |
| 243 | switch (dcr) { |
| 244 | case SDRAM_R0BAS + 0: |
| 245 | mtdcr(SDRAM_R0BAS + 0, val); |
| 246 | break; |
| 247 | case SDRAM_R0BAS + 1: |
| 248 | mtdcr(SDRAM_R0BAS + 1, val); |
| 249 | break; |
| 250 | case SDRAM_R0BAS + 2: |
| 251 | mtdcr(SDRAM_R0BAS + 2, val); |
| 252 | break; |
| 253 | case SDRAM_R0BAS + 3: |
| 254 | mtdcr(SDRAM_R0BAS + 3, val); |
| 255 | break; |
| 256 | default: |
| 257 | printf("DCR %d not defined in case statement!!!\n", dcr); |
| 258 | } |
| 259 | } |
| 260 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 261 | static unsigned char spd_read(uchar chip, uint addr) |
| 262 | { |
| 263 | unsigned char data[2]; |
| 264 | |
| 265 | if (i2c_probe(chip) == 0) |
| 266 | if (i2c_read(chip, addr, 1, data, 1) == 0) |
| 267 | return data[0]; |
| 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | /*-----------------------------------------------------------------------------+ |
| 273 | * sdram_memsize |
| 274 | *-----------------------------------------------------------------------------*/ |
| 275 | static unsigned long sdram_memsize(void) |
| 276 | { |
| 277 | unsigned long mem_size; |
| 278 | unsigned long mcopt2; |
| 279 | unsigned long mcstat; |
| 280 | unsigned long mb0cf; |
| 281 | unsigned long sdsz; |
| 282 | unsigned long i; |
| 283 | |
| 284 | mem_size = 0; |
| 285 | |
| 286 | mfsdram(SDRAM_MCOPT2, mcopt2); |
| 287 | mfsdram(SDRAM_MCSTAT, mcstat); |
| 288 | |
| 289 | /* DDR controller must be enabled and not in self-refresh. */ |
| 290 | /* Otherwise memsize is zero. */ |
| 291 | if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) |
| 292 | && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) |
| 293 | && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) |
| 294 | == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 295 | for (i = 0; i < MAXBXCF; i++) { |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 296 | mfsdram(SDRAM_MB0CF + (i << 2), mb0cf); |
| 297 | /* Banks enabled */ |
| 298 | if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { |
| 299 | sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK; |
| 300 | |
| 301 | switch(sdsz) { |
| 302 | case SDRAM_RXBAS_SDSZ_8: |
| 303 | mem_size+=8; |
| 304 | break; |
| 305 | case SDRAM_RXBAS_SDSZ_16: |
| 306 | mem_size+=16; |
| 307 | break; |
| 308 | case SDRAM_RXBAS_SDSZ_32: |
| 309 | mem_size+=32; |
| 310 | break; |
| 311 | case SDRAM_RXBAS_SDSZ_64: |
| 312 | mem_size+=64; |
| 313 | break; |
| 314 | case SDRAM_RXBAS_SDSZ_128: |
| 315 | mem_size+=128; |
| 316 | break; |
| 317 | case SDRAM_RXBAS_SDSZ_256: |
| 318 | mem_size+=256; |
| 319 | break; |
| 320 | case SDRAM_RXBAS_SDSZ_512: |
| 321 | mem_size+=512; |
| 322 | break; |
| 323 | case SDRAM_RXBAS_SDSZ_1024: |
| 324 | mem_size+=1024; |
| 325 | break; |
| 326 | case SDRAM_RXBAS_SDSZ_2048: |
| 327 | mem_size+=2048; |
| 328 | break; |
| 329 | case SDRAM_RXBAS_SDSZ_4096: |
| 330 | mem_size+=4096; |
| 331 | break; |
| 332 | default: |
| 333 | mem_size=0; |
| 334 | break; |
| 335 | } |
| 336 | } |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | mem_size *= 1024 * 1024; |
| 341 | return(mem_size); |
| 342 | } |
| 343 | |
| 344 | /*-----------------------------------------------------------------------------+ |
| 345 | * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller. |
| 346 | * Note: This routine runs from flash with a stack set up in the chip's |
| 347 | * sram space. It is important that the routine does not require .sbss, .bss or |
| 348 | * .data sections. It also cannot call routines that require these sections. |
| 349 | *-----------------------------------------------------------------------------*/ |
| 350 | /*----------------------------------------------------------------------------- |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 351 | * Function: initdram |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 352 | * Description: Configures SDRAM memory banks for DDR operation. |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 353 | * Auto Memory Configuration option reads the DDR SDRAM EEPROMs |
| 354 | * via the IIC bus and then configures the DDR SDRAM memory |
| 355 | * banks appropriately. If Auto Memory Configuration is |
| 356 | * not used, it is assumed that no DIMM is plugged |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 357 | *-----------------------------------------------------------------------------*/ |
| 358 | long int initdram(int board_type) |
| 359 | { |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 360 | unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 361 | unsigned char spd0[MAX_SPD_BYTES]; |
| 362 | unsigned char spd1[MAX_SPD_BYTES]; |
| 363 | unsigned char *dimm_spd[MAXDIMMS]; |
| 364 | unsigned long dimm_populated[MAXDIMMS]; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 365 | unsigned long num_dimm_banks; /* on board dimm banks */ |
| 366 | unsigned long val; |
| 367 | ddr_cas_id_t selected_cas; |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 368 | int write_recovery; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 369 | unsigned long dram_size = 0; |
| 370 | |
| 371 | num_dimm_banks = sizeof(iic0_dimm_addr); |
| 372 | |
| 373 | /*------------------------------------------------------------------ |
| 374 | * Set up an array of SPD matrixes. |
| 375 | *-----------------------------------------------------------------*/ |
| 376 | dimm_spd[0] = spd0; |
| 377 | dimm_spd[1] = spd1; |
| 378 | |
| 379 | /*------------------------------------------------------------------ |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 380 | * Reset the DDR-SDRAM controller. |
| 381 | *-----------------------------------------------------------------*/ |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 382 | mtsdr(SDR0_SRST, (0x80000000 >> 10)); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 383 | mtsdr(SDR0_SRST, 0x00000000); |
| 384 | |
| 385 | /* |
| 386 | * Make sure I2C controller is initialized |
| 387 | * before continuing. |
| 388 | */ |
| 389 | |
| 390 | /* switch to correct I2C bus */ |
| 391 | I2C_SET_BUS(CFG_SPD_BUS_NUM); |
| 392 | i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE); |
| 393 | |
| 394 | /*------------------------------------------------------------------ |
| 395 | * Clear out the serial presence detect buffers. |
| 396 | * Perform IIC reads from the dimm. Fill in the spds. |
| 397 | * Check to see if the dimm slots are populated |
| 398 | *-----------------------------------------------------------------*/ |
| 399 | get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 400 | |
| 401 | /*------------------------------------------------------------------ |
| 402 | * Check the memory type for the dimms plugged. |
| 403 | *-----------------------------------------------------------------*/ |
| 404 | check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 405 | |
| 406 | /*------------------------------------------------------------------ |
| 407 | * Check the frequency supported for the dimms plugged. |
| 408 | *-----------------------------------------------------------------*/ |
| 409 | check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 410 | |
| 411 | /*------------------------------------------------------------------ |
| 412 | * Check the total rank number. |
| 413 | *-----------------------------------------------------------------*/ |
| 414 | check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 415 | |
| 416 | /*------------------------------------------------------------------ |
| 417 | * Check the voltage type for the dimms plugged. |
| 418 | *-----------------------------------------------------------------*/ |
| 419 | check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 420 | |
| 421 | /*------------------------------------------------------------------ |
| 422 | * Program SDRAM controller options 2 register |
| 423 | * Except Enabling of the memory controller. |
| 424 | *-----------------------------------------------------------------*/ |
| 425 | mfsdram(SDRAM_MCOPT2, val); |
| 426 | mtsdram(SDRAM_MCOPT2, |
| 427 | (val & |
| 428 | ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK | |
| 429 | SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK | |
| 430 | SDRAM_MCOPT2_ISIE_MASK)) |
| 431 | | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE | |
| 432 | SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW | |
| 433 | SDRAM_MCOPT2_ISIE_ENABLE)); |
| 434 | |
| 435 | /*------------------------------------------------------------------ |
| 436 | * Program SDRAM controller options 1 register |
| 437 | * Note: Does not enable the memory controller. |
| 438 | *-----------------------------------------------------------------*/ |
| 439 | program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 440 | |
| 441 | /*------------------------------------------------------------------ |
| 442 | * Set the SDRAM Controller On Die Termination Register |
| 443 | *-----------------------------------------------------------------*/ |
| 444 | program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 445 | |
| 446 | /*------------------------------------------------------------------ |
| 447 | * Program SDRAM refresh register. |
| 448 | *-----------------------------------------------------------------*/ |
| 449 | program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 450 | |
| 451 | /*------------------------------------------------------------------ |
| 452 | * Program SDRAM mode register. |
| 453 | *-----------------------------------------------------------------*/ |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 454 | program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks, |
| 455 | &selected_cas, &write_recovery); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 456 | |
| 457 | /*------------------------------------------------------------------ |
| 458 | * Set the SDRAM Write Data/DM/DQS Clock Timing Reg |
| 459 | *-----------------------------------------------------------------*/ |
| 460 | mfsdram(SDRAM_WRDTR, val); |
| 461 | mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) | |
| 462 | (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV)); |
| 463 | |
| 464 | /*------------------------------------------------------------------ |
| 465 | * Set the SDRAM Clock Timing Register |
| 466 | *-----------------------------------------------------------------*/ |
| 467 | mfsdram(SDRAM_CLKTR, val); |
Stefan Roese | 7187db7 | 2007-06-01 13:45:00 +0200 | [diff] [blame] | 468 | #ifdef CFG_44x_DDR2_CKTR_180 |
| 469 | mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV); |
| 470 | #else |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 471 | mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG); |
Stefan Roese | 7187db7 | 2007-06-01 13:45:00 +0200 | [diff] [blame] | 472 | #endif |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 473 | |
| 474 | /*------------------------------------------------------------------ |
| 475 | * Program the BxCF registers. |
| 476 | *-----------------------------------------------------------------*/ |
| 477 | program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 478 | |
| 479 | /*------------------------------------------------------------------ |
| 480 | * Program SDRAM timing registers. |
| 481 | *-----------------------------------------------------------------*/ |
| 482 | program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 483 | |
| 484 | /*------------------------------------------------------------------ |
| 485 | * Set the Extended Mode register |
| 486 | *-----------------------------------------------------------------*/ |
| 487 | mfsdram(SDRAM_MEMODE, val); |
| 488 | mtsdram(SDRAM_MEMODE, |
| 489 | (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK | |
| 490 | SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) | |
| 491 | (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 492 | | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE)); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 493 | |
| 494 | /*------------------------------------------------------------------ |
| 495 | * Program Initialization preload registers. |
| 496 | *-----------------------------------------------------------------*/ |
| 497 | program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 498 | selected_cas, write_recovery); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 499 | |
| 500 | /*------------------------------------------------------------------ |
| 501 | * Delay to ensure 200usec have elapsed since reset. |
| 502 | *-----------------------------------------------------------------*/ |
| 503 | udelay(400); |
| 504 | |
| 505 | /*------------------------------------------------------------------ |
| 506 | * Set the memory queue core base addr. |
| 507 | *-----------------------------------------------------------------*/ |
| 508 | program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 509 | |
| 510 | /*------------------------------------------------------------------ |
| 511 | * Program SDRAM controller options 2 register |
| 512 | * Enable the memory controller. |
| 513 | *-----------------------------------------------------------------*/ |
| 514 | mfsdram(SDRAM_MCOPT2, val); |
| 515 | mtsdram(SDRAM_MCOPT2, |
| 516 | (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK | |
| 517 | SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) | |
| 518 | (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE)); |
| 519 | |
| 520 | /*------------------------------------------------------------------ |
| 521 | * Wait for SDRAM_CFG0_DC_EN to complete. |
| 522 | *-----------------------------------------------------------------*/ |
| 523 | do { |
| 524 | mfsdram(SDRAM_MCSTAT, val); |
| 525 | } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP); |
| 526 | |
| 527 | /* get installed memory size */ |
| 528 | dram_size = sdram_memsize(); |
| 529 | |
| 530 | /* and program tlb entries for this size (dynamic) */ |
Stefan Roese | dbca208 | 2007-06-14 11:14:32 +0200 | [diff] [blame] | 531 | program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 532 | |
| 533 | /*------------------------------------------------------------------ |
| 534 | * DQS calibration. |
| 535 | *-----------------------------------------------------------------*/ |
| 536 | program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
| 537 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 538 | #ifdef CONFIG_DDR_ECC |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 539 | /*------------------------------------------------------------------ |
| 540 | * If ecc is enabled, initialize the parity bits. |
| 541 | *-----------------------------------------------------------------*/ |
| 542 | program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, MY_TLB_WORD2_I_ENABLE); |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 543 | #endif |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 544 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 545 | #ifdef DEBUG |
| 546 | ppc440sp_sdram_register_dump(); |
| 547 | #endif |
| 548 | |
| 549 | return dram_size; |
| 550 | } |
| 551 | |
| 552 | static void get_spd_info(unsigned long *dimm_populated, |
| 553 | unsigned char *iic0_dimm_addr, |
| 554 | unsigned long num_dimm_banks) |
| 555 | { |
| 556 | unsigned long dimm_num; |
| 557 | unsigned long dimm_found; |
| 558 | unsigned char num_of_bytes; |
| 559 | unsigned char total_size; |
| 560 | |
| 561 | dimm_found = FALSE; |
| 562 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 563 | num_of_bytes = 0; |
| 564 | total_size = 0; |
| 565 | |
| 566 | num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0); |
| 567 | debug("\nspd_read(0x%x) returned %d\n", |
| 568 | iic0_dimm_addr[dimm_num], num_of_bytes); |
| 569 | total_size = spd_read(iic0_dimm_addr[dimm_num], 1); |
| 570 | debug("spd_read(0x%x) returned %d\n", |
| 571 | iic0_dimm_addr[dimm_num], total_size); |
| 572 | |
| 573 | if ((num_of_bytes != 0) && (total_size != 0)) { |
| 574 | dimm_populated[dimm_num] = TRUE; |
| 575 | dimm_found = TRUE; |
| 576 | debug("DIMM slot %lu: populated\n", dimm_num); |
| 577 | } else { |
| 578 | dimm_populated[dimm_num] = FALSE; |
| 579 | debug("DIMM slot %lu: Not populated\n", dimm_num); |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | if (dimm_found == FALSE) { |
| 584 | printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); |
| 585 | hang(); |
| 586 | } |
| 587 | } |
| 588 | |
| 589 | #ifdef CONFIG_ADD_RAM_INFO |
| 590 | void board_add_ram_info(int use_default) |
| 591 | { |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 592 | PPC440_SYS_INFO board_cfg; |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 593 | u32 val; |
| 594 | |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 595 | if (is_ecc_enabled()) |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 596 | puts(" (ECC"); |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 597 | else |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 598 | puts(" (ECC not"); |
| 599 | |
| 600 | get_sys_info(&board_cfg); |
| 601 | |
| 602 | mfsdr(SDR0_DDR0, val); |
| 603 | val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1); |
| 604 | printf(" enabled, %d MHz", (val * 2) / 1000000); |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 605 | |
| 606 | mfsdram(SDRAM_MMODE, val); |
| 607 | val = (val & SDRAM_MMODE_DCL_MASK) >> 4; |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 608 | printf(", CL%d)", val); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 609 | } |
| 610 | #endif |
| 611 | |
| 612 | /*------------------------------------------------------------------ |
| 613 | * For the memory DIMMs installed, this routine verifies that they |
| 614 | * really are DDR specific DIMMs. |
| 615 | *-----------------------------------------------------------------*/ |
| 616 | static void check_mem_type(unsigned long *dimm_populated, |
| 617 | unsigned char *iic0_dimm_addr, |
| 618 | unsigned long num_dimm_banks) |
| 619 | { |
| 620 | unsigned long dimm_num; |
| 621 | unsigned long dimm_type; |
| 622 | |
| 623 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 624 | if (dimm_populated[dimm_num] == TRUE) { |
| 625 | dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); |
| 626 | switch (dimm_type) { |
| 627 | case 1: |
| 628 | printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in " |
| 629 | "slot %d.\n", (unsigned int)dimm_num); |
| 630 | printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); |
| 631 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 632 | hang(); |
| 633 | break; |
| 634 | case 2: |
| 635 | printf("ERROR: EDO DIMM detected in slot %d.\n", |
| 636 | (unsigned int)dimm_num); |
| 637 | printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); |
| 638 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 639 | hang(); |
| 640 | break; |
| 641 | case 3: |
| 642 | printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n", |
| 643 | (unsigned int)dimm_num); |
| 644 | printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); |
| 645 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 646 | hang(); |
| 647 | break; |
| 648 | case 4: |
| 649 | printf("ERROR: SDRAM DIMM detected in slot %d.\n", |
| 650 | (unsigned int)dimm_num); |
| 651 | printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); |
| 652 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 653 | hang(); |
| 654 | break; |
| 655 | case 5: |
| 656 | printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n", |
| 657 | (unsigned int)dimm_num); |
| 658 | printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); |
| 659 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 660 | hang(); |
| 661 | break; |
| 662 | case 6: |
| 663 | printf("ERROR: SGRAM DIMM detected in slot %d.\n", |
| 664 | (unsigned int)dimm_num); |
| 665 | printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); |
| 666 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 667 | hang(); |
| 668 | break; |
| 669 | case 7: |
| 670 | debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num); |
| 671 | dimm_populated[dimm_num] = SDRAM_DDR1; |
| 672 | break; |
| 673 | case 8: |
| 674 | debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num); |
| 675 | dimm_populated[dimm_num] = SDRAM_DDR2; |
| 676 | break; |
| 677 | default: |
| 678 | printf("ERROR: Unknown DIMM detected in slot %d.\n", |
| 679 | (unsigned int)dimm_num); |
| 680 | printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n"); |
| 681 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 682 | hang(); |
| 683 | break; |
| 684 | } |
| 685 | } |
| 686 | } |
| 687 | for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) { |
| 688 | if ((dimm_populated[dimm_num-1] != SDRAM_NONE) |
| 689 | && (dimm_populated[dimm_num] != SDRAM_NONE) |
| 690 | && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) { |
| 691 | printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n"); |
| 692 | hang(); |
| 693 | } |
| 694 | } |
| 695 | } |
| 696 | |
| 697 | /*------------------------------------------------------------------ |
| 698 | * For the memory DIMMs installed, this routine verifies that |
| 699 | * frequency previously calculated is supported. |
| 700 | *-----------------------------------------------------------------*/ |
| 701 | static void check_frequency(unsigned long *dimm_populated, |
| 702 | unsigned char *iic0_dimm_addr, |
| 703 | unsigned long num_dimm_banks) |
| 704 | { |
| 705 | unsigned long dimm_num; |
| 706 | unsigned long tcyc_reg; |
| 707 | unsigned long cycle_time; |
| 708 | unsigned long calc_cycle_time; |
| 709 | unsigned long sdram_freq; |
| 710 | unsigned long sdr_ddrpll; |
| 711 | PPC440_SYS_INFO board_cfg; |
| 712 | |
| 713 | /*------------------------------------------------------------------ |
| 714 | * Get the board configuration info. |
| 715 | *-----------------------------------------------------------------*/ |
| 716 | get_sys_info(&board_cfg); |
| 717 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 718 | mfsdr(SDR0_DDR0, sdr_ddrpll); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 719 | sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); |
| 720 | |
| 721 | /* |
| 722 | * calc_cycle_time is calculated from DDR frequency set by board/chip |
| 723 | * and is expressed in multiple of 10 picoseconds |
| 724 | * to match the way DIMM cycle time is calculated below. |
| 725 | */ |
| 726 | calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq); |
| 727 | |
| 728 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 729 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 730 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); |
| 731 | /* |
| 732 | * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles: |
| 733 | * the higher order nibble (bits 4-7) designates the cycle time |
| 734 | * to a granularity of 1ns; |
| 735 | * the value presented by the lower order nibble (bits 0-3) |
| 736 | * has a granularity of .1ns and is added to the value designated |
| 737 | * by the higher nibble. In addition, four lines of the lower order |
| 738 | * nibble are assigned to support +.25,+.33, +.66 and +.75. |
| 739 | */ |
| 740 | /* Convert from hex to decimal */ |
| 741 | if ((tcyc_reg & 0x0F) == 0x0D) |
| 742 | cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75; |
| 743 | else if ((tcyc_reg & 0x0F) == 0x0C) |
| 744 | cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66; |
| 745 | else if ((tcyc_reg & 0x0F) == 0x0B) |
| 746 | cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33; |
| 747 | else if ((tcyc_reg & 0x0F) == 0x0A) |
| 748 | cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25; |
| 749 | else |
| 750 | cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + |
| 751 | ((tcyc_reg & 0x0F)*10); |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 752 | debug("cycle_time=%d [10 picoseconds]\n", cycle_time); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 753 | |
| 754 | if (cycle_time > (calc_cycle_time + 10)) { |
| 755 | /* |
| 756 | * the provided sdram cycle_time is too small |
| 757 | * for the available DIMM cycle_time. |
| 758 | * The additionnal 100ps is here to accept a small incertainty. |
| 759 | */ |
| 760 | printf("ERROR: DRAM DIMM detected with cycle_time %d ps in " |
| 761 | "slot %d \n while calculated cycle time is %d ps.\n", |
| 762 | (unsigned int)(cycle_time*10), |
| 763 | (unsigned int)dimm_num, |
| 764 | (unsigned int)(calc_cycle_time*10)); |
| 765 | printf("Replace the DIMM, or change DDR frequency via " |
| 766 | "strapping bits.\n\n"); |
| 767 | hang(); |
| 768 | } |
| 769 | } |
| 770 | } |
| 771 | } |
| 772 | |
| 773 | /*------------------------------------------------------------------ |
| 774 | * For the memory DIMMs installed, this routine verifies two |
| 775 | * ranks/banks maximum are availables. |
| 776 | *-----------------------------------------------------------------*/ |
| 777 | static void check_rank_number(unsigned long *dimm_populated, |
| 778 | unsigned char *iic0_dimm_addr, |
| 779 | unsigned long num_dimm_banks) |
| 780 | { |
| 781 | unsigned long dimm_num; |
| 782 | unsigned long dimm_rank; |
| 783 | unsigned long total_rank = 0; |
| 784 | |
| 785 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 786 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 787 | dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5); |
| 788 | if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) |
| 789 | dimm_rank = (dimm_rank & 0x0F) +1; |
| 790 | else |
| 791 | dimm_rank = dimm_rank & 0x0F; |
| 792 | |
| 793 | |
| 794 | if (dimm_rank > MAXRANKS) { |
| 795 | printf("ERROR: DRAM DIMM detected with %d ranks in " |
| 796 | "slot %d is not supported.\n", dimm_rank, dimm_num); |
| 797 | printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); |
| 798 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 799 | hang(); |
| 800 | } else |
| 801 | total_rank += dimm_rank; |
| 802 | } |
| 803 | if (total_rank > MAXRANKS) { |
| 804 | printf("ERROR: DRAM DIMM detected with a total of %d ranks " |
| 805 | "for all slots.\n", (unsigned int)total_rank); |
| 806 | printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); |
| 807 | printf("Remove one of the DIMM modules.\n\n"); |
| 808 | hang(); |
| 809 | } |
| 810 | } |
| 811 | } |
| 812 | |
| 813 | /*------------------------------------------------------------------ |
| 814 | * only support 2.5V modules. |
| 815 | * This routine verifies this. |
| 816 | *-----------------------------------------------------------------*/ |
| 817 | static void check_voltage_type(unsigned long *dimm_populated, |
| 818 | unsigned char *iic0_dimm_addr, |
| 819 | unsigned long num_dimm_banks) |
| 820 | { |
| 821 | unsigned long dimm_num; |
| 822 | unsigned long voltage_type; |
| 823 | |
| 824 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 825 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 826 | voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); |
| 827 | switch (voltage_type) { |
| 828 | case 0x00: |
| 829 | printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); |
| 830 | printf("This DIMM is 5.0 Volt/TTL.\n"); |
| 831 | printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", |
| 832 | (unsigned int)dimm_num); |
| 833 | hang(); |
| 834 | break; |
| 835 | case 0x01: |
| 836 | printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); |
| 837 | printf("This DIMM is LVTTL.\n"); |
| 838 | printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", |
| 839 | (unsigned int)dimm_num); |
| 840 | hang(); |
| 841 | break; |
| 842 | case 0x02: |
| 843 | printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); |
| 844 | printf("This DIMM is 1.5 Volt.\n"); |
| 845 | printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", |
| 846 | (unsigned int)dimm_num); |
| 847 | hang(); |
| 848 | break; |
| 849 | case 0x03: |
| 850 | printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); |
| 851 | printf("This DIMM is 3.3 Volt/TTL.\n"); |
| 852 | printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", |
| 853 | (unsigned int)dimm_num); |
| 854 | hang(); |
| 855 | break; |
| 856 | case 0x04: |
| 857 | /* 2.5 Voltage only for DDR1 */ |
| 858 | break; |
| 859 | case 0x05: |
| 860 | /* 1.8 Voltage only for DDR2 */ |
| 861 | break; |
| 862 | default: |
| 863 | printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); |
| 864 | printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", |
| 865 | (unsigned int)dimm_num); |
| 866 | hang(); |
| 867 | break; |
| 868 | } |
| 869 | } |
| 870 | } |
| 871 | } |
| 872 | |
| 873 | /*-----------------------------------------------------------------------------+ |
| 874 | * program_copt1. |
| 875 | *-----------------------------------------------------------------------------*/ |
| 876 | static void program_copt1(unsigned long *dimm_populated, |
| 877 | unsigned char *iic0_dimm_addr, |
| 878 | unsigned long num_dimm_banks) |
| 879 | { |
| 880 | unsigned long dimm_num; |
| 881 | unsigned long mcopt1; |
| 882 | unsigned long ecc_enabled; |
| 883 | unsigned long ecc = 0; |
| 884 | unsigned long data_width = 0; |
| 885 | unsigned long dimm_32bit; |
| 886 | unsigned long dimm_64bit; |
| 887 | unsigned long registered = 0; |
| 888 | unsigned long attribute = 0; |
| 889 | unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */ |
| 890 | unsigned long bankcount; |
| 891 | unsigned long ddrtype; |
| 892 | unsigned long val; |
| 893 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 894 | #ifdef CONFIG_DDR_ECC |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 895 | ecc_enabled = TRUE; |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 896 | #else |
| 897 | ecc_enabled = FALSE; |
| 898 | #endif |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 899 | dimm_32bit = FALSE; |
| 900 | dimm_64bit = FALSE; |
| 901 | buf0 = FALSE; |
| 902 | buf1 = FALSE; |
| 903 | |
| 904 | /*------------------------------------------------------------------ |
| 905 | * Set memory controller options reg 1, SDRAM_MCOPT1. |
| 906 | *-----------------------------------------------------------------*/ |
| 907 | mfsdram(SDRAM_MCOPT1, val); |
| 908 | mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK | |
| 909 | SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK | |
| 910 | SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK | |
| 911 | SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK | |
| 912 | SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK | |
| 913 | SDRAM_MCOPT1_DREF_MASK); |
| 914 | |
| 915 | mcopt1 |= SDRAM_MCOPT1_QDEP; |
| 916 | mcopt1 |= SDRAM_MCOPT1_PMU_OPEN; |
| 917 | mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED; |
| 918 | mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED; |
| 919 | mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED; |
| 920 | mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL; |
| 921 | |
| 922 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 923 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 924 | /* test ecc support */ |
| 925 | ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11); |
| 926 | if (ecc != 0x02) /* ecc not supported */ |
| 927 | ecc_enabled = FALSE; |
| 928 | |
| 929 | /* test bank count */ |
| 930 | bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17); |
| 931 | if (bankcount == 0x04) /* bank count = 4 */ |
| 932 | mcopt1 |= SDRAM_MCOPT1_4_BANKS; |
| 933 | else /* bank count = 8 */ |
| 934 | mcopt1 |= SDRAM_MCOPT1_8_BANKS; |
| 935 | |
| 936 | /* test DDR type */ |
| 937 | ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2); |
| 938 | /* test for buffered/unbuffered, registered, differential clocks */ |
| 939 | registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20); |
| 940 | attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21); |
| 941 | |
| 942 | /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */ |
| 943 | if (dimm_num == 0) { |
| 944 | if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */ |
| 945 | mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE; |
| 946 | if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */ |
| 947 | mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE; |
| 948 | if (registered == 1) { /* DDR2 always buffered */ |
| 949 | /* TODO: what about above comments ? */ |
| 950 | mcopt1 |= SDRAM_MCOPT1_RDEN; |
| 951 | buf0 = TRUE; |
| 952 | } else { |
| 953 | /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */ |
| 954 | if ((attribute & 0x02) == 0x00) { |
| 955 | /* buffered not supported */ |
| 956 | buf0 = FALSE; |
| 957 | } else { |
| 958 | mcopt1 |= SDRAM_MCOPT1_RDEN; |
| 959 | buf0 = TRUE; |
| 960 | } |
| 961 | } |
| 962 | } |
| 963 | else if (dimm_num == 1) { |
| 964 | if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */ |
| 965 | mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE; |
| 966 | if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */ |
| 967 | mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE; |
| 968 | if (registered == 1) { |
| 969 | /* DDR2 always buffered */ |
| 970 | mcopt1 |= SDRAM_MCOPT1_RDEN; |
| 971 | buf1 = TRUE; |
| 972 | } else { |
| 973 | if ((attribute & 0x02) == 0x00) { |
| 974 | /* buffered not supported */ |
| 975 | buf1 = FALSE; |
| 976 | } else { |
| 977 | mcopt1 |= SDRAM_MCOPT1_RDEN; |
| 978 | buf1 = TRUE; |
| 979 | } |
| 980 | } |
| 981 | } |
| 982 | |
| 983 | /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */ |
| 984 | data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) + |
| 985 | (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8); |
| 986 | |
| 987 | switch (data_width) { |
| 988 | case 72: |
| 989 | case 64: |
| 990 | dimm_64bit = TRUE; |
| 991 | break; |
| 992 | case 40: |
| 993 | case 32: |
| 994 | dimm_32bit = TRUE; |
| 995 | break; |
| 996 | default: |
| 997 | printf("WARNING: Detected a DIMM with a data width of %d bits.\n", |
| 998 | data_width); |
| 999 | printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n"); |
| 1000 | break; |
| 1001 | } |
| 1002 | } |
| 1003 | } |
| 1004 | |
| 1005 | /* verify matching properties */ |
| 1006 | if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) { |
| 1007 | if (buf0 != buf1) { |
| 1008 | printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n"); |
| 1009 | hang(); |
| 1010 | } |
| 1011 | } |
| 1012 | |
| 1013 | if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) { |
| 1014 | printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n"); |
| 1015 | hang(); |
| 1016 | } |
| 1017 | else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) { |
| 1018 | mcopt1 |= SDRAM_MCOPT1_DMWD_64; |
| 1019 | } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) { |
| 1020 | mcopt1 |= SDRAM_MCOPT1_DMWD_32; |
| 1021 | } else { |
| 1022 | printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n"); |
| 1023 | hang(); |
| 1024 | } |
| 1025 | |
| 1026 | if (ecc_enabled == TRUE) |
| 1027 | mcopt1 |= SDRAM_MCOPT1_MCHK_GEN; |
| 1028 | else |
| 1029 | mcopt1 |= SDRAM_MCOPT1_MCHK_NON; |
| 1030 | |
| 1031 | mtsdram(SDRAM_MCOPT1, mcopt1); |
| 1032 | } |
| 1033 | |
| 1034 | /*-----------------------------------------------------------------------------+ |
| 1035 | * program_codt. |
| 1036 | *-----------------------------------------------------------------------------*/ |
| 1037 | static void program_codt(unsigned long *dimm_populated, |
| 1038 | unsigned char *iic0_dimm_addr, |
| 1039 | unsigned long num_dimm_banks) |
| 1040 | { |
| 1041 | unsigned long codt; |
| 1042 | unsigned long modt0 = 0; |
| 1043 | unsigned long modt1 = 0; |
| 1044 | unsigned long modt2 = 0; |
| 1045 | unsigned long modt3 = 0; |
| 1046 | unsigned char dimm_num; |
| 1047 | unsigned char dimm_rank; |
| 1048 | unsigned char total_rank = 0; |
| 1049 | unsigned char total_dimm = 0; |
| 1050 | unsigned char dimm_type = 0; |
| 1051 | unsigned char firstSlot = 0; |
| 1052 | |
| 1053 | /*------------------------------------------------------------------ |
| 1054 | * Set the SDRAM Controller On Die Termination Register |
| 1055 | *-----------------------------------------------------------------*/ |
| 1056 | mfsdram(SDRAM_CODT, codt); |
| 1057 | codt |= (SDRAM_CODT_IO_NMODE |
| 1058 | & (~SDRAM_CODT_DQS_SINGLE_END |
| 1059 | & ~SDRAM_CODT_CKSE_SINGLE_END |
| 1060 | & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END |
| 1061 | & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END)); |
| 1062 | |
| 1063 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 1064 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 1065 | dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5); |
| 1066 | if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) { |
| 1067 | dimm_rank = (dimm_rank & 0x0F) + 1; |
| 1068 | dimm_type = SDRAM_DDR2; |
| 1069 | } else { |
| 1070 | dimm_rank = dimm_rank & 0x0F; |
| 1071 | dimm_type = SDRAM_DDR1; |
| 1072 | } |
| 1073 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1074 | total_rank += dimm_rank; |
| 1075 | total_dimm++; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1076 | if ((dimm_num == 0) && (total_dimm == 1)) |
| 1077 | firstSlot = TRUE; |
| 1078 | else |
| 1079 | firstSlot = FALSE; |
| 1080 | } |
| 1081 | } |
| 1082 | if (dimm_type == SDRAM_DDR2) { |
| 1083 | codt |= SDRAM_CODT_DQS_1_8_V_DDR2; |
| 1084 | if ((total_dimm == 1) && (firstSlot == TRUE)) { |
| 1085 | if (total_rank == 1) { |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1086 | codt |= CALC_ODT_R(0); |
| 1087 | modt0 = CALC_ODT_W(0); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1088 | modt1 = 0x00000000; |
| 1089 | modt2 = 0x00000000; |
| 1090 | modt3 = 0x00000000; |
| 1091 | } |
| 1092 | if (total_rank == 2) { |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1093 | codt |= CALC_ODT_R(0) | CALC_ODT_R(1); |
| 1094 | modt0 = CALC_ODT_W(0); |
| 1095 | modt1 = CALC_ODT_W(0); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1096 | modt2 = 0x00000000; |
| 1097 | modt3 = 0x00000000; |
| 1098 | } |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1099 | } else if ((total_dimm == 1) && (firstSlot != TRUE)) { |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1100 | if (total_rank == 1) { |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1101 | codt |= CALC_ODT_R(2); |
| 1102 | modt0 = 0x00000000; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1103 | modt1 = 0x00000000; |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1104 | modt2 = CALC_ODT_W(2); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1105 | modt3 = 0x00000000; |
| 1106 | } |
| 1107 | if (total_rank == 2) { |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1108 | codt |= CALC_ODT_R(2) | CALC_ODT_R(3); |
| 1109 | modt0 = 0x00000000; |
| 1110 | modt1 = 0x00000000; |
| 1111 | modt2 = CALC_ODT_W(2); |
| 1112 | modt3 = CALC_ODT_W(2); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1113 | } |
| 1114 | } |
| 1115 | if (total_dimm == 2) { |
| 1116 | if (total_rank == 2) { |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1117 | codt |= CALC_ODT_R(0) | CALC_ODT_R(2); |
| 1118 | modt0 = CALC_ODT_RW(2); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1119 | modt1 = 0x00000000; |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1120 | modt2 = CALC_ODT_RW(0); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1121 | modt3 = 0x00000000; |
| 1122 | } |
| 1123 | if (total_rank == 4) { |
Stefan Roese | 7187db7 | 2007-06-01 13:45:00 +0200 | [diff] [blame] | 1124 | codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | |
| 1125 | CALC_ODT_R(2) | CALC_ODT_R(3); |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1126 | modt0 = CALC_ODT_RW(2); |
| 1127 | modt1 = 0x00000000; |
| 1128 | modt2 = CALC_ODT_RW(0); |
| 1129 | modt3 = 0x00000000; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1130 | } |
| 1131 | } |
Wolfgang Denk | 647d3c3 | 2007-03-04 01:36:05 +0100 | [diff] [blame] | 1132 | } else { |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1133 | codt |= SDRAM_CODT_DQS_2_5_V_DDR1; |
| 1134 | modt0 = 0x00000000; |
| 1135 | modt1 = 0x00000000; |
| 1136 | modt2 = 0x00000000; |
| 1137 | modt3 = 0x00000000; |
| 1138 | |
| 1139 | if (total_dimm == 1) { |
| 1140 | if (total_rank == 1) |
| 1141 | codt |= 0x00800000; |
| 1142 | if (total_rank == 2) |
| 1143 | codt |= 0x02800000; |
| 1144 | } |
| 1145 | if (total_dimm == 2) { |
| 1146 | if (total_rank == 2) |
| 1147 | codt |= 0x08800000; |
| 1148 | if (total_rank == 4) |
| 1149 | codt |= 0x2a800000; |
| 1150 | } |
| 1151 | } |
| 1152 | |
| 1153 | debug("nb of dimm %d\n", total_dimm); |
| 1154 | debug("nb of rank %d\n", total_rank); |
| 1155 | if (total_dimm == 1) |
| 1156 | debug("dimm in slot %d\n", firstSlot); |
| 1157 | |
| 1158 | mtsdram(SDRAM_CODT, codt); |
| 1159 | mtsdram(SDRAM_MODT0, modt0); |
| 1160 | mtsdram(SDRAM_MODT1, modt1); |
| 1161 | mtsdram(SDRAM_MODT2, modt2); |
| 1162 | mtsdram(SDRAM_MODT3, modt3); |
| 1163 | } |
| 1164 | |
| 1165 | /*-----------------------------------------------------------------------------+ |
| 1166 | * program_initplr. |
| 1167 | *-----------------------------------------------------------------------------*/ |
| 1168 | static void program_initplr(unsigned long *dimm_populated, |
| 1169 | unsigned char *iic0_dimm_addr, |
| 1170 | unsigned long num_dimm_banks, |
Wolfgang Denk | ad5bb45 | 2007-03-06 18:08:43 +0100 | [diff] [blame] | 1171 | ddr_cas_id_t selected_cas, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1172 | int write_recovery) |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1173 | { |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1174 | u32 cas = 0; |
| 1175 | u32 odt = 0; |
| 1176 | u32 ods = 0; |
| 1177 | u32 mr; |
| 1178 | u32 wr; |
| 1179 | u32 emr; |
| 1180 | u32 emr2; |
| 1181 | u32 emr3; |
| 1182 | int dimm_num; |
| 1183 | int total_dimm = 0; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1184 | |
| 1185 | /****************************************************** |
| 1186 | ** Assumption: if more than one DIMM, all DIMMs are the same |
Wolfgang Denk | 7435711 | 2007-02-27 14:26:04 +0100 | [diff] [blame] | 1187 | ** as already checked in check_memory_type |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1188 | ******************************************************/ |
| 1189 | |
| 1190 | if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) { |
| 1191 | mtsdram(SDRAM_INITPLR0, 0x81B80000); |
| 1192 | mtsdram(SDRAM_INITPLR1, 0x81900400); |
| 1193 | mtsdram(SDRAM_INITPLR2, 0x81810000); |
| 1194 | mtsdram(SDRAM_INITPLR3, 0xff800162); |
| 1195 | mtsdram(SDRAM_INITPLR4, 0x81900400); |
| 1196 | mtsdram(SDRAM_INITPLR5, 0x86080000); |
| 1197 | mtsdram(SDRAM_INITPLR6, 0x86080000); |
| 1198 | mtsdram(SDRAM_INITPLR7, 0x81000062); |
| 1199 | } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) { |
| 1200 | switch (selected_cas) { |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1201 | case DDR_CAS_3: |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1202 | cas = 3 << 4; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1203 | break; |
| 1204 | case DDR_CAS_4: |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1205 | cas = 4 << 4; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1206 | break; |
| 1207 | case DDR_CAS_5: |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1208 | cas = 5 << 4; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1209 | break; |
| 1210 | default: |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1211 | printf("ERROR: ucode error on selected_cas value %d", selected_cas); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1212 | hang(); |
| 1213 | break; |
| 1214 | } |
| 1215 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1216 | #if 0 |
| 1217 | /* |
| 1218 | * ToDo - Still a problem with the write recovery: |
| 1219 | * On the Corsair CM2X512-5400C4 module, setting write recovery |
| 1220 | * in the INITPLR reg to the value calculated in program_mode() |
| 1221 | * results in not correctly working DDR2 memory (crash after |
| 1222 | * relocation). |
| 1223 | * |
| 1224 | * So for now, set the write recovery to 3. This seems to work |
| 1225 | * on the Corair module too. |
| 1226 | * |
| 1227 | * 2007-03-01, sr |
| 1228 | */ |
| 1229 | switch (write_recovery) { |
| 1230 | case 3: |
| 1231 | wr = WRITE_RECOV_3; |
| 1232 | break; |
| 1233 | case 4: |
| 1234 | wr = WRITE_RECOV_4; |
| 1235 | break; |
| 1236 | case 5: |
| 1237 | wr = WRITE_RECOV_5; |
| 1238 | break; |
| 1239 | case 6: |
| 1240 | wr = WRITE_RECOV_6; |
| 1241 | break; |
| 1242 | default: |
| 1243 | printf("ERROR: write recovery not support (%d)", write_recovery); |
| 1244 | hang(); |
| 1245 | break; |
| 1246 | } |
| 1247 | #else |
| 1248 | wr = WRITE_RECOV_3; /* test-only, see description above */ |
| 1249 | #endif |
| 1250 | |
| 1251 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) |
| 1252 | if (dimm_populated[dimm_num] != SDRAM_NONE) |
| 1253 | total_dimm++; |
| 1254 | if (total_dimm == 1) { |
| 1255 | odt = ODT_150_OHM; |
| 1256 | ods = ODS_FULL; |
| 1257 | } else if (total_dimm == 2) { |
| 1258 | odt = ODT_75_OHM; |
| 1259 | ods = ODS_REDUCED; |
| 1260 | } else { |
| 1261 | printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm); |
| 1262 | hang(); |
| 1263 | } |
| 1264 | |
| 1265 | mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas; |
| 1266 | emr = CMD_EMR | SELECT_EMR | odt | ods; |
| 1267 | emr2 = CMD_EMR | SELECT_EMR2; |
| 1268 | emr3 = CMD_EMR | SELECT_EMR3; |
| 1269 | mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */ |
| 1270 | udelay(1000); |
| 1271 | mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */ |
| 1272 | mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */ |
| 1273 | mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */ |
| 1274 | mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */ |
| 1275 | mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */ |
| 1276 | udelay(1000); |
| 1277 | mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */ |
| 1278 | mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */ |
| 1279 | mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */ |
| 1280 | mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */ |
| 1281 | mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */ |
| 1282 | mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */ |
| 1283 | mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */ |
| 1284 | mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */ |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1285 | } else { |
| 1286 | printf("ERROR: ucode error as unknown DDR type in program_initplr"); |
| 1287 | hang(); |
| 1288 | } |
| 1289 | } |
| 1290 | |
| 1291 | /*------------------------------------------------------------------ |
| 1292 | * This routine programs the SDRAM_MMODE register. |
| 1293 | * the selected_cas is an output parameter, that will be passed |
| 1294 | * by caller to call the above program_initplr( ) |
| 1295 | *-----------------------------------------------------------------*/ |
| 1296 | static void program_mode(unsigned long *dimm_populated, |
| 1297 | unsigned char *iic0_dimm_addr, |
| 1298 | unsigned long num_dimm_banks, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1299 | ddr_cas_id_t *selected_cas, |
| 1300 | int *write_recovery) |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1301 | { |
| 1302 | unsigned long dimm_num; |
| 1303 | unsigned long sdram_ddr1; |
| 1304 | unsigned long t_wr_ns; |
| 1305 | unsigned long t_wr_clk; |
| 1306 | unsigned long cas_bit; |
| 1307 | unsigned long cas_index; |
| 1308 | unsigned long sdram_freq; |
| 1309 | unsigned long ddr_check; |
| 1310 | unsigned long mmode; |
| 1311 | unsigned long tcyc_reg; |
| 1312 | unsigned long cycle_2_0_clk; |
| 1313 | unsigned long cycle_2_5_clk; |
| 1314 | unsigned long cycle_3_0_clk; |
| 1315 | unsigned long cycle_4_0_clk; |
| 1316 | unsigned long cycle_5_0_clk; |
| 1317 | unsigned long max_2_0_tcyc_ns_x_100; |
| 1318 | unsigned long max_2_5_tcyc_ns_x_100; |
| 1319 | unsigned long max_3_0_tcyc_ns_x_100; |
| 1320 | unsigned long max_4_0_tcyc_ns_x_100; |
| 1321 | unsigned long max_5_0_tcyc_ns_x_100; |
| 1322 | unsigned long cycle_time_ns_x_100[3]; |
| 1323 | PPC440_SYS_INFO board_cfg; |
| 1324 | unsigned char cas_2_0_available; |
| 1325 | unsigned char cas_2_5_available; |
| 1326 | unsigned char cas_3_0_available; |
| 1327 | unsigned char cas_4_0_available; |
| 1328 | unsigned char cas_5_0_available; |
| 1329 | unsigned long sdr_ddrpll; |
| 1330 | |
| 1331 | /*------------------------------------------------------------------ |
| 1332 | * Get the board configuration info. |
| 1333 | *-----------------------------------------------------------------*/ |
| 1334 | get_sys_info(&board_cfg); |
| 1335 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 1336 | mfsdr(SDR0_DDR0, sdr_ddrpll); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1337 | sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1); |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1338 | debug("sdram_freq=%d\n", sdram_freq); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1339 | |
| 1340 | /*------------------------------------------------------------------ |
| 1341 | * Handle the timing. We need to find the worst case timing of all |
| 1342 | * the dimm modules installed. |
| 1343 | *-----------------------------------------------------------------*/ |
| 1344 | t_wr_ns = 0; |
| 1345 | cas_2_0_available = TRUE; |
| 1346 | cas_2_5_available = TRUE; |
| 1347 | cas_3_0_available = TRUE; |
| 1348 | cas_4_0_available = TRUE; |
| 1349 | cas_5_0_available = TRUE; |
| 1350 | max_2_0_tcyc_ns_x_100 = 10; |
| 1351 | max_2_5_tcyc_ns_x_100 = 10; |
| 1352 | max_3_0_tcyc_ns_x_100 = 10; |
| 1353 | max_4_0_tcyc_ns_x_100 = 10; |
| 1354 | max_5_0_tcyc_ns_x_100 = 10; |
| 1355 | sdram_ddr1 = TRUE; |
| 1356 | |
| 1357 | /* loop through all the DIMM slots on the board */ |
| 1358 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 1359 | /* If a dimm is installed in a particular slot ... */ |
| 1360 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 1361 | if (dimm_populated[dimm_num] == SDRAM_DDR1) |
| 1362 | sdram_ddr1 = TRUE; |
| 1363 | else |
| 1364 | sdram_ddr1 = FALSE; |
| 1365 | |
| 1366 | /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */ |
| 1367 | cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1368 | debug("cas_bit[SPD byte 18]=%02x\n", cas_bit); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1369 | |
| 1370 | /* For a particular DIMM, grab the three CAS values it supports */ |
| 1371 | for (cas_index = 0; cas_index < 3; cas_index++) { |
| 1372 | switch (cas_index) { |
| 1373 | case 0: |
| 1374 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9); |
| 1375 | break; |
| 1376 | case 1: |
| 1377 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23); |
| 1378 | break; |
| 1379 | default: |
| 1380 | tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25); |
| 1381 | break; |
| 1382 | } |
| 1383 | |
| 1384 | if ((tcyc_reg & 0x0F) >= 10) { |
| 1385 | if ((tcyc_reg & 0x0F) == 0x0D) { |
| 1386 | /* Convert from hex to decimal */ |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1387 | cycle_time_ns_x_100[cas_index] = |
| 1388 | (((tcyc_reg & 0xF0) >> 4) * 100) + 75; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1389 | } else { |
| 1390 | printf("ERROR: SPD reported Tcyc is incorrect for DIMM " |
| 1391 | "in slot %d\n", (unsigned int)dimm_num); |
| 1392 | hang(); |
| 1393 | } |
| 1394 | } else { |
| 1395 | /* Convert from hex to decimal */ |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1396 | cycle_time_ns_x_100[cas_index] = |
| 1397 | (((tcyc_reg & 0xF0) >> 4) * 100) + |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1398 | ((tcyc_reg & 0x0F)*10); |
| 1399 | } |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1400 | debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index, |
| 1401 | cycle_time_ns_x_100[cas_index]); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1402 | } |
| 1403 | |
| 1404 | /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */ |
| 1405 | /* supported for a particular DIMM. */ |
| 1406 | cas_index = 0; |
| 1407 | |
| 1408 | if (sdram_ddr1) { |
| 1409 | /* |
| 1410 | * DDR devices use the following bitmask for CAS latency: |
| 1411 | * Bit 7 6 5 4 3 2 1 0 |
| 1412 | * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0 |
| 1413 | */ |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1414 | if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) && |
| 1415 | (cycle_time_ns_x_100[cas_index] != 0)) { |
| 1416 | max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, |
| 1417 | cycle_time_ns_x_100[cas_index]); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1418 | cas_index++; |
| 1419 | } else { |
| 1420 | if (cas_index != 0) |
| 1421 | cas_index++; |
| 1422 | cas_4_0_available = FALSE; |
| 1423 | } |
| 1424 | |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1425 | if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && |
| 1426 | (cycle_time_ns_x_100[cas_index] != 0)) { |
| 1427 | max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, |
| 1428 | cycle_time_ns_x_100[cas_index]); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1429 | cas_index++; |
| 1430 | } else { |
| 1431 | if (cas_index != 0) |
| 1432 | cas_index++; |
| 1433 | cas_3_0_available = FALSE; |
| 1434 | } |
| 1435 | |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1436 | if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && |
| 1437 | (cycle_time_ns_x_100[cas_index] != 0)) { |
| 1438 | max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100, |
| 1439 | cycle_time_ns_x_100[cas_index]); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1440 | cas_index++; |
| 1441 | } else { |
| 1442 | if (cas_index != 0) |
| 1443 | cas_index++; |
| 1444 | cas_2_5_available = FALSE; |
| 1445 | } |
| 1446 | |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1447 | if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && |
| 1448 | (cycle_time_ns_x_100[cas_index] != 0)) { |
| 1449 | max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100, |
| 1450 | cycle_time_ns_x_100[cas_index]); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1451 | cas_index++; |
| 1452 | } else { |
| 1453 | if (cas_index != 0) |
| 1454 | cas_index++; |
| 1455 | cas_2_0_available = FALSE; |
| 1456 | } |
| 1457 | } else { |
| 1458 | /* |
| 1459 | * DDR2 devices use the following bitmask for CAS latency: |
| 1460 | * Bit 7 6 5 4 3 2 1 0 |
| 1461 | * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD |
| 1462 | */ |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1463 | if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) && |
| 1464 | (cycle_time_ns_x_100[cas_index] != 0)) { |
| 1465 | max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100, |
| 1466 | cycle_time_ns_x_100[cas_index]); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1467 | cas_index++; |
| 1468 | } else { |
| 1469 | if (cas_index != 0) |
| 1470 | cas_index++; |
| 1471 | cas_5_0_available = FALSE; |
| 1472 | } |
| 1473 | |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1474 | if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && |
| 1475 | (cycle_time_ns_x_100[cas_index] != 0)) { |
| 1476 | max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100, |
| 1477 | cycle_time_ns_x_100[cas_index]); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1478 | cas_index++; |
| 1479 | } else { |
| 1480 | if (cas_index != 0) |
| 1481 | cas_index++; |
| 1482 | cas_4_0_available = FALSE; |
| 1483 | } |
| 1484 | |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1485 | if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && |
| 1486 | (cycle_time_ns_x_100[cas_index] != 0)) { |
| 1487 | max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100, |
| 1488 | cycle_time_ns_x_100[cas_index]); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1489 | cas_index++; |
| 1490 | } else { |
| 1491 | if (cas_index != 0) |
| 1492 | cas_index++; |
| 1493 | cas_3_0_available = FALSE; |
| 1494 | } |
| 1495 | } |
| 1496 | } |
| 1497 | } |
| 1498 | |
| 1499 | /*------------------------------------------------------------------ |
| 1500 | * Set the SDRAM mode, SDRAM_MMODE |
| 1501 | *-----------------------------------------------------------------*/ |
| 1502 | mfsdram(SDRAM_MMODE, mmode); |
| 1503 | mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK); |
| 1504 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 1505 | /* add 10 here because of rounding problems */ |
| 1506 | cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10; |
| 1507 | cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10; |
| 1508 | cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10; |
| 1509 | cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10; |
| 1510 | cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10; |
Stefan Roese | cabee75 | 2007-03-31 13:15:06 +0200 | [diff] [blame] | 1511 | debug("cycle_3_0_clk=%d\n", cycle_3_0_clk); |
| 1512 | debug("cycle_4_0_clk=%d\n", cycle_4_0_clk); |
| 1513 | debug("cycle_5_0_clk=%d\n", cycle_5_0_clk); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1514 | |
| 1515 | if (sdram_ddr1 == TRUE) { /* DDR1 */ |
| 1516 | if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) { |
| 1517 | mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK; |
| 1518 | *selected_cas = DDR_CAS_2; |
| 1519 | } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) { |
| 1520 | mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK; |
| 1521 | *selected_cas = DDR_CAS_2_5; |
| 1522 | } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { |
| 1523 | mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK; |
| 1524 | *selected_cas = DDR_CAS_3; |
| 1525 | } else { |
| 1526 | printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n"); |
| 1527 | printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); |
| 1528 | printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n"); |
| 1529 | hang(); |
| 1530 | } |
| 1531 | } else { /* DDR2 */ |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 1532 | debug("cas_3_0_available=%d\n", cas_3_0_available); |
| 1533 | debug("cas_4_0_available=%d\n", cas_4_0_available); |
| 1534 | debug("cas_5_0_available=%d\n", cas_5_0_available); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1535 | if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { |
| 1536 | mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK; |
| 1537 | *selected_cas = DDR_CAS_3; |
| 1538 | } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) { |
| 1539 | mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK; |
| 1540 | *selected_cas = DDR_CAS_4; |
| 1541 | } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) { |
| 1542 | mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK; |
| 1543 | *selected_cas = DDR_CAS_5; |
| 1544 | } else { |
| 1545 | printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n"); |
| 1546 | printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n"); |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 1547 | printf("Make sure the PLB speed is within the supported range of the DIMMs.\n"); |
| 1548 | printf("cas3=%d cas4=%d cas5=%d\n", |
| 1549 | cas_3_0_available, cas_4_0_available, cas_5_0_available); |
| 1550 | printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n", |
| 1551 | sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1552 | hang(); |
| 1553 | } |
| 1554 | } |
| 1555 | |
| 1556 | if (sdram_ddr1 == TRUE) |
| 1557 | mmode |= SDRAM_MMODE_WR_DDR1; |
| 1558 | else { |
| 1559 | |
| 1560 | /* loop through all the DIMM slots on the board */ |
| 1561 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 1562 | /* If a dimm is installed in a particular slot ... */ |
| 1563 | if (dimm_populated[dimm_num] != SDRAM_NONE) |
| 1564 | t_wr_ns = max(t_wr_ns, |
| 1565 | spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); |
| 1566 | } |
| 1567 | |
| 1568 | /* |
| 1569 | * convert from nanoseconds to ddr clocks |
| 1570 | * round up if necessary |
| 1571 | */ |
| 1572 | t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION); |
| 1573 | ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns); |
| 1574 | if (sdram_freq != ddr_check) |
| 1575 | t_wr_clk++; |
| 1576 | |
| 1577 | switch (t_wr_clk) { |
| 1578 | case 0: |
| 1579 | case 1: |
| 1580 | case 2: |
| 1581 | case 3: |
| 1582 | mmode |= SDRAM_MMODE_WR_DDR2_3_CYC; |
| 1583 | break; |
| 1584 | case 4: |
| 1585 | mmode |= SDRAM_MMODE_WR_DDR2_4_CYC; |
| 1586 | break; |
| 1587 | case 5: |
| 1588 | mmode |= SDRAM_MMODE_WR_DDR2_5_CYC; |
| 1589 | break; |
| 1590 | default: |
| 1591 | mmode |= SDRAM_MMODE_WR_DDR2_6_CYC; |
| 1592 | break; |
| 1593 | } |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1594 | *write_recovery = t_wr_clk; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1595 | } |
| 1596 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 1597 | debug("CAS latency = %d\n", *selected_cas); |
| 1598 | debug("Write recovery = %d\n", *write_recovery); |
| 1599 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1600 | mtsdram(SDRAM_MMODE, mmode); |
| 1601 | } |
| 1602 | |
| 1603 | /*-----------------------------------------------------------------------------+ |
| 1604 | * program_rtr. |
| 1605 | *-----------------------------------------------------------------------------*/ |
| 1606 | static void program_rtr(unsigned long *dimm_populated, |
| 1607 | unsigned char *iic0_dimm_addr, |
| 1608 | unsigned long num_dimm_banks) |
| 1609 | { |
| 1610 | PPC440_SYS_INFO board_cfg; |
| 1611 | unsigned long max_refresh_rate; |
| 1612 | unsigned long dimm_num; |
| 1613 | unsigned long refresh_rate_type; |
| 1614 | unsigned long refresh_rate; |
| 1615 | unsigned long rint; |
| 1616 | unsigned long sdram_freq; |
| 1617 | unsigned long sdr_ddrpll; |
| 1618 | unsigned long val; |
| 1619 | |
| 1620 | /*------------------------------------------------------------------ |
| 1621 | * Get the board configuration info. |
| 1622 | *-----------------------------------------------------------------*/ |
| 1623 | get_sys_info(&board_cfg); |
| 1624 | |
| 1625 | /*------------------------------------------------------------------ |
| 1626 | * Set the SDRAM Refresh Timing Register, SDRAM_RTR |
| 1627 | *-----------------------------------------------------------------*/ |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 1628 | mfsdr(SDR0_DDR0, sdr_ddrpll); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1629 | sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); |
| 1630 | |
| 1631 | max_refresh_rate = 0; |
| 1632 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 1633 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 1634 | |
| 1635 | refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12); |
| 1636 | refresh_rate_type &= 0x7F; |
| 1637 | switch (refresh_rate_type) { |
| 1638 | case 0: |
| 1639 | refresh_rate = 15625; |
| 1640 | break; |
| 1641 | case 1: |
| 1642 | refresh_rate = 3906; |
| 1643 | break; |
| 1644 | case 2: |
| 1645 | refresh_rate = 7812; |
| 1646 | break; |
| 1647 | case 3: |
| 1648 | refresh_rate = 31250; |
| 1649 | break; |
| 1650 | case 4: |
| 1651 | refresh_rate = 62500; |
| 1652 | break; |
| 1653 | case 5: |
| 1654 | refresh_rate = 125000; |
| 1655 | break; |
| 1656 | default: |
| 1657 | refresh_rate = 0; |
| 1658 | printf("ERROR: DIMM %d unsupported refresh rate/type.\n", |
| 1659 | (unsigned int)dimm_num); |
| 1660 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 1661 | hang(); |
| 1662 | break; |
| 1663 | } |
| 1664 | |
| 1665 | max_refresh_rate = max(max_refresh_rate, refresh_rate); |
| 1666 | } |
| 1667 | } |
| 1668 | |
| 1669 | rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION); |
| 1670 | mfsdram(SDRAM_RTR, val); |
| 1671 | mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) | |
| 1672 | (SDRAM_RTR_RINT_ENCODE(rint))); |
| 1673 | } |
| 1674 | |
| 1675 | /*------------------------------------------------------------------ |
| 1676 | * This routine programs the SDRAM_TRx registers. |
| 1677 | *-----------------------------------------------------------------*/ |
| 1678 | static void program_tr(unsigned long *dimm_populated, |
| 1679 | unsigned char *iic0_dimm_addr, |
| 1680 | unsigned long num_dimm_banks) |
| 1681 | { |
| 1682 | unsigned long dimm_num; |
| 1683 | unsigned long sdram_ddr1; |
| 1684 | unsigned long t_rp_ns; |
| 1685 | unsigned long t_rcd_ns; |
| 1686 | unsigned long t_rrd_ns; |
| 1687 | unsigned long t_ras_ns; |
| 1688 | unsigned long t_rc_ns; |
| 1689 | unsigned long t_rfc_ns; |
| 1690 | unsigned long t_wpc_ns; |
| 1691 | unsigned long t_wtr_ns; |
| 1692 | unsigned long t_rpc_ns; |
| 1693 | unsigned long t_rp_clk; |
| 1694 | unsigned long t_rcd_clk; |
| 1695 | unsigned long t_rrd_clk; |
| 1696 | unsigned long t_ras_clk; |
| 1697 | unsigned long t_rc_clk; |
| 1698 | unsigned long t_rfc_clk; |
| 1699 | unsigned long t_wpc_clk; |
| 1700 | unsigned long t_wtr_clk; |
| 1701 | unsigned long t_rpc_clk; |
| 1702 | unsigned long sdtr1, sdtr2, sdtr3; |
| 1703 | unsigned long ddr_check; |
| 1704 | unsigned long sdram_freq; |
| 1705 | unsigned long sdr_ddrpll; |
| 1706 | |
| 1707 | PPC440_SYS_INFO board_cfg; |
| 1708 | |
| 1709 | /*------------------------------------------------------------------ |
| 1710 | * Get the board configuration info. |
| 1711 | *-----------------------------------------------------------------*/ |
| 1712 | get_sys_info(&board_cfg); |
| 1713 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 1714 | mfsdr(SDR0_DDR0, sdr_ddrpll); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 1715 | sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); |
| 1716 | |
| 1717 | /*------------------------------------------------------------------ |
| 1718 | * Handle the timing. We need to find the worst case timing of all |
| 1719 | * the dimm modules installed. |
| 1720 | *-----------------------------------------------------------------*/ |
| 1721 | t_rp_ns = 0; |
| 1722 | t_rrd_ns = 0; |
| 1723 | t_rcd_ns = 0; |
| 1724 | t_ras_ns = 0; |
| 1725 | t_rc_ns = 0; |
| 1726 | t_rfc_ns = 0; |
| 1727 | t_wpc_ns = 0; |
| 1728 | t_wtr_ns = 0; |
| 1729 | t_rpc_ns = 0; |
| 1730 | sdram_ddr1 = TRUE; |
| 1731 | |
| 1732 | /* loop through all the DIMM slots on the board */ |
| 1733 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 1734 | /* If a dimm is installed in a particular slot ... */ |
| 1735 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 1736 | if (dimm_populated[dimm_num] == SDRAM_DDR2) |
| 1737 | sdram_ddr1 = TRUE; |
| 1738 | else |
| 1739 | sdram_ddr1 = FALSE; |
| 1740 | |
| 1741 | t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); |
| 1742 | t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); |
| 1743 | t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2); |
| 1744 | t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30)); |
| 1745 | t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41)); |
| 1746 | t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42)); |
| 1747 | } |
| 1748 | } |
| 1749 | |
| 1750 | /*------------------------------------------------------------------ |
| 1751 | * Set the SDRAM Timing Reg 1, SDRAM_TR1 |
| 1752 | *-----------------------------------------------------------------*/ |
| 1753 | mfsdram(SDRAM_SDTR1, sdtr1); |
| 1754 | sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK | |
| 1755 | SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK); |
| 1756 | |
| 1757 | /* default values */ |
| 1758 | sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK; |
| 1759 | sdtr1 |= SDRAM_SDTR1_RTW_2_CLK; |
| 1760 | |
| 1761 | /* normal operations */ |
| 1762 | sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK; |
| 1763 | sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK; |
| 1764 | |
| 1765 | mtsdram(SDRAM_SDTR1, sdtr1); |
| 1766 | |
| 1767 | /*------------------------------------------------------------------ |
| 1768 | * Set the SDRAM Timing Reg 2, SDRAM_TR2 |
| 1769 | *-----------------------------------------------------------------*/ |
| 1770 | mfsdram(SDRAM_SDTR2, sdtr2); |
| 1771 | sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK | |
| 1772 | SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK | |
| 1773 | SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK | |
| 1774 | SDRAM_SDTR2_RRD_MASK); |
| 1775 | |
| 1776 | /* |
| 1777 | * convert t_rcd from nanoseconds to ddr clocks |
| 1778 | * round up if necessary |
| 1779 | */ |
| 1780 | t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION); |
| 1781 | ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns); |
| 1782 | if (sdram_freq != ddr_check) |
| 1783 | t_rcd_clk++; |
| 1784 | |
| 1785 | switch (t_rcd_clk) { |
| 1786 | case 0: |
| 1787 | case 1: |
| 1788 | sdtr2 |= SDRAM_SDTR2_RCD_1_CLK; |
| 1789 | break; |
| 1790 | case 2: |
| 1791 | sdtr2 |= SDRAM_SDTR2_RCD_2_CLK; |
| 1792 | break; |
| 1793 | case 3: |
| 1794 | sdtr2 |= SDRAM_SDTR2_RCD_3_CLK; |
| 1795 | break; |
| 1796 | case 4: |
| 1797 | sdtr2 |= SDRAM_SDTR2_RCD_4_CLK; |
| 1798 | break; |
| 1799 | default: |
| 1800 | sdtr2 |= SDRAM_SDTR2_RCD_5_CLK; |
| 1801 | break; |
| 1802 | } |
| 1803 | |
| 1804 | if (sdram_ddr1 == TRUE) { /* DDR1 */ |
| 1805 | if (sdram_freq < 200000000) { |
| 1806 | sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; |
| 1807 | sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; |
| 1808 | sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; |
| 1809 | } else { |
| 1810 | sdtr2 |= SDRAM_SDTR2_WTR_2_CLK; |
| 1811 | sdtr2 |= SDRAM_SDTR2_WPC_3_CLK; |
| 1812 | sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; |
| 1813 | } |
| 1814 | } else { /* DDR2 */ |
| 1815 | /* loop through all the DIMM slots on the board */ |
| 1816 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 1817 | /* If a dimm is installed in a particular slot ... */ |
| 1818 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 1819 | t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2); |
| 1820 | t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2); |
| 1821 | t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2); |
| 1822 | } |
| 1823 | } |
| 1824 | |
| 1825 | /* |
| 1826 | * convert from nanoseconds to ddr clocks |
| 1827 | * round up if necessary |
| 1828 | */ |
| 1829 | t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION); |
| 1830 | ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns); |
| 1831 | if (sdram_freq != ddr_check) |
| 1832 | t_wpc_clk++; |
| 1833 | |
| 1834 | switch (t_wpc_clk) { |
| 1835 | case 0: |
| 1836 | case 1: |
| 1837 | case 2: |
| 1838 | sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; |
| 1839 | break; |
| 1840 | case 3: |
| 1841 | sdtr2 |= SDRAM_SDTR2_WPC_3_CLK; |
| 1842 | break; |
| 1843 | case 4: |
| 1844 | sdtr2 |= SDRAM_SDTR2_WPC_4_CLK; |
| 1845 | break; |
| 1846 | case 5: |
| 1847 | sdtr2 |= SDRAM_SDTR2_WPC_5_CLK; |
| 1848 | break; |
| 1849 | default: |
| 1850 | sdtr2 |= SDRAM_SDTR2_WPC_6_CLK; |
| 1851 | break; |
| 1852 | } |
| 1853 | |
| 1854 | /* |
| 1855 | * convert from nanoseconds to ddr clocks |
| 1856 | * round up if necessary |
| 1857 | */ |
| 1858 | t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION); |
| 1859 | ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns); |
| 1860 | if (sdram_freq != ddr_check) |
| 1861 | t_wtr_clk++; |
| 1862 | |
| 1863 | switch (t_wtr_clk) { |
| 1864 | case 0: |
| 1865 | case 1: |
| 1866 | sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; |
| 1867 | break; |
| 1868 | case 2: |
| 1869 | sdtr2 |= SDRAM_SDTR2_WTR_2_CLK; |
| 1870 | break; |
| 1871 | case 3: |
| 1872 | sdtr2 |= SDRAM_SDTR2_WTR_3_CLK; |
| 1873 | break; |
| 1874 | default: |
| 1875 | sdtr2 |= SDRAM_SDTR2_WTR_4_CLK; |
| 1876 | break; |
| 1877 | } |
| 1878 | |
| 1879 | /* |
| 1880 | * convert from nanoseconds to ddr clocks |
| 1881 | * round up if necessary |
| 1882 | */ |
| 1883 | t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION); |
| 1884 | ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns); |
| 1885 | if (sdram_freq != ddr_check) |
| 1886 | t_rpc_clk++; |
| 1887 | |
| 1888 | switch (t_rpc_clk) { |
| 1889 | case 0: |
| 1890 | case 1: |
| 1891 | case 2: |
| 1892 | sdtr2 |= SDRAM_SDTR2_RPC_2_CLK; |
| 1893 | break; |
| 1894 | case 3: |
| 1895 | sdtr2 |= SDRAM_SDTR2_RPC_3_CLK; |
| 1896 | break; |
| 1897 | default: |
| 1898 | sdtr2 |= SDRAM_SDTR2_RPC_4_CLK; |
| 1899 | break; |
| 1900 | } |
| 1901 | } |
| 1902 | |
| 1903 | /* default value */ |
| 1904 | sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK; |
| 1905 | |
| 1906 | /* |
| 1907 | * convert t_rrd from nanoseconds to ddr clocks |
| 1908 | * round up if necessary |
| 1909 | */ |
| 1910 | t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION); |
| 1911 | ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns); |
| 1912 | if (sdram_freq != ddr_check) |
| 1913 | t_rrd_clk++; |
| 1914 | |
| 1915 | if (t_rrd_clk == 3) |
| 1916 | sdtr2 |= SDRAM_SDTR2_RRD_3_CLK; |
| 1917 | else |
| 1918 | sdtr2 |= SDRAM_SDTR2_RRD_2_CLK; |
| 1919 | |
| 1920 | /* |
| 1921 | * convert t_rp from nanoseconds to ddr clocks |
| 1922 | * round up if necessary |
| 1923 | */ |
| 1924 | t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION); |
| 1925 | ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns); |
| 1926 | if (sdram_freq != ddr_check) |
| 1927 | t_rp_clk++; |
| 1928 | |
| 1929 | switch (t_rp_clk) { |
| 1930 | case 0: |
| 1931 | case 1: |
| 1932 | case 2: |
| 1933 | case 3: |
| 1934 | sdtr2 |= SDRAM_SDTR2_RP_3_CLK; |
| 1935 | break; |
| 1936 | case 4: |
| 1937 | sdtr2 |= SDRAM_SDTR2_RP_4_CLK; |
| 1938 | break; |
| 1939 | case 5: |
| 1940 | sdtr2 |= SDRAM_SDTR2_RP_5_CLK; |
| 1941 | break; |
| 1942 | case 6: |
| 1943 | sdtr2 |= SDRAM_SDTR2_RP_6_CLK; |
| 1944 | break; |
| 1945 | default: |
| 1946 | sdtr2 |= SDRAM_SDTR2_RP_7_CLK; |
| 1947 | break; |
| 1948 | } |
| 1949 | |
| 1950 | mtsdram(SDRAM_SDTR2, sdtr2); |
| 1951 | |
| 1952 | /*------------------------------------------------------------------ |
| 1953 | * Set the SDRAM Timing Reg 3, SDRAM_TR3 |
| 1954 | *-----------------------------------------------------------------*/ |
| 1955 | mfsdram(SDRAM_SDTR3, sdtr3); |
| 1956 | sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK | |
| 1957 | SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK); |
| 1958 | |
| 1959 | /* |
| 1960 | * convert t_ras from nanoseconds to ddr clocks |
| 1961 | * round up if necessary |
| 1962 | */ |
| 1963 | t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION); |
| 1964 | ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns); |
| 1965 | if (sdram_freq != ddr_check) |
| 1966 | t_ras_clk++; |
| 1967 | |
| 1968 | sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk); |
| 1969 | |
| 1970 | /* |
| 1971 | * convert t_rc from nanoseconds to ddr clocks |
| 1972 | * round up if necessary |
| 1973 | */ |
| 1974 | t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION); |
| 1975 | ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns); |
| 1976 | if (sdram_freq != ddr_check) |
| 1977 | t_rc_clk++; |
| 1978 | |
| 1979 | sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk); |
| 1980 | |
| 1981 | /* default xcs value */ |
| 1982 | sdtr3 |= SDRAM_SDTR3_XCS; |
| 1983 | |
| 1984 | /* |
| 1985 | * convert t_rfc from nanoseconds to ddr clocks |
| 1986 | * round up if necessary |
| 1987 | */ |
| 1988 | t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION); |
| 1989 | ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns); |
| 1990 | if (sdram_freq != ddr_check) |
| 1991 | t_rfc_clk++; |
| 1992 | |
| 1993 | sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk); |
| 1994 | |
| 1995 | mtsdram(SDRAM_SDTR3, sdtr3); |
| 1996 | } |
| 1997 | |
| 1998 | /*-----------------------------------------------------------------------------+ |
| 1999 | * program_bxcf. |
| 2000 | *-----------------------------------------------------------------------------*/ |
| 2001 | static void program_bxcf(unsigned long *dimm_populated, |
| 2002 | unsigned char *iic0_dimm_addr, |
| 2003 | unsigned long num_dimm_banks) |
| 2004 | { |
| 2005 | unsigned long dimm_num; |
| 2006 | unsigned long num_col_addr; |
| 2007 | unsigned long num_ranks; |
| 2008 | unsigned long num_banks; |
| 2009 | unsigned long mode; |
| 2010 | unsigned long ind_rank; |
| 2011 | unsigned long ind; |
| 2012 | unsigned long ind_bank; |
| 2013 | unsigned long bank_0_populated; |
| 2014 | |
| 2015 | /*------------------------------------------------------------------ |
| 2016 | * Set the BxCF regs. First, wipe out the bank config registers. |
| 2017 | *-----------------------------------------------------------------*/ |
| 2018 | mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF); |
| 2019 | mtdcr(SDRAMC_CFGDATA, 0x00000000); |
| 2020 | mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF); |
| 2021 | mtdcr(SDRAMC_CFGDATA, 0x00000000); |
| 2022 | mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF); |
| 2023 | mtdcr(SDRAMC_CFGDATA, 0x00000000); |
| 2024 | mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF); |
| 2025 | mtdcr(SDRAMC_CFGDATA, 0x00000000); |
| 2026 | |
| 2027 | mode = SDRAM_BXCF_M_BE_ENABLE; |
| 2028 | |
| 2029 | bank_0_populated = 0; |
| 2030 | |
| 2031 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 2032 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 2033 | num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); |
| 2034 | num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5); |
| 2035 | if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) |
| 2036 | num_ranks = (num_ranks & 0x0F) +1; |
| 2037 | else |
| 2038 | num_ranks = num_ranks & 0x0F; |
| 2039 | |
| 2040 | num_banks = spd_read(iic0_dimm_addr[dimm_num], 17); |
| 2041 | |
| 2042 | for (ind_bank = 0; ind_bank < 2; ind_bank++) { |
| 2043 | if (num_banks == 4) |
| 2044 | ind = 0; |
| 2045 | else |
| 2046 | ind = 5; |
| 2047 | switch (num_col_addr) { |
| 2048 | case 0x08: |
| 2049 | mode |= (SDRAM_BXCF_M_AM_0 + ind); |
| 2050 | break; |
| 2051 | case 0x09: |
| 2052 | mode |= (SDRAM_BXCF_M_AM_1 + ind); |
| 2053 | break; |
| 2054 | case 0x0A: |
| 2055 | mode |= (SDRAM_BXCF_M_AM_2 + ind); |
| 2056 | break; |
| 2057 | case 0x0B: |
| 2058 | mode |= (SDRAM_BXCF_M_AM_3 + ind); |
| 2059 | break; |
| 2060 | case 0x0C: |
| 2061 | mode |= (SDRAM_BXCF_M_AM_4 + ind); |
| 2062 | break; |
| 2063 | default: |
| 2064 | printf("DDR-SDRAM: DIMM %d BxCF configuration.\n", |
| 2065 | (unsigned int)dimm_num); |
| 2066 | printf("ERROR: Unsupported value for number of " |
| 2067 | "column addresses: %d.\n", (unsigned int)num_col_addr); |
| 2068 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 2069 | hang(); |
| 2070 | } |
| 2071 | } |
| 2072 | |
| 2073 | if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1)) |
| 2074 | bank_0_populated = 1; |
| 2075 | |
| 2076 | for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) { |
| 2077 | mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2)); |
| 2078 | mtdcr(SDRAMC_CFGDATA, mode); |
| 2079 | } |
| 2080 | } |
| 2081 | } |
| 2082 | } |
| 2083 | |
| 2084 | /*------------------------------------------------------------------ |
| 2085 | * program memory queue. |
| 2086 | *-----------------------------------------------------------------*/ |
| 2087 | static void program_memory_queue(unsigned long *dimm_populated, |
| 2088 | unsigned char *iic0_dimm_addr, |
| 2089 | unsigned long num_dimm_banks) |
| 2090 | { |
| 2091 | unsigned long dimm_num; |
| 2092 | unsigned long rank_base_addr; |
| 2093 | unsigned long rank_reg; |
| 2094 | unsigned long rank_size_bytes; |
| 2095 | unsigned long rank_size_id; |
| 2096 | unsigned long num_ranks; |
| 2097 | unsigned long baseadd_size; |
| 2098 | unsigned long i; |
| 2099 | unsigned long bank_0_populated = 0; |
| 2100 | |
| 2101 | /*------------------------------------------------------------------ |
| 2102 | * Reset the rank_base_address. |
| 2103 | *-----------------------------------------------------------------*/ |
| 2104 | rank_reg = SDRAM_R0BAS; |
| 2105 | |
| 2106 | rank_base_addr = 0x00000000; |
| 2107 | |
| 2108 | for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { |
| 2109 | if (dimm_populated[dimm_num] != SDRAM_NONE) { |
| 2110 | num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5); |
| 2111 | if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) |
| 2112 | num_ranks = (num_ranks & 0x0F) + 1; |
| 2113 | else |
| 2114 | num_ranks = num_ranks & 0x0F; |
| 2115 | |
| 2116 | rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31); |
| 2117 | |
| 2118 | /*------------------------------------------------------------------ |
| 2119 | * Set the sizes |
| 2120 | *-----------------------------------------------------------------*/ |
| 2121 | baseadd_size = 0; |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 2122 | rank_size_bytes = 4 * 1024 * 1024 * rank_size_id; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2123 | switch (rank_size_id) { |
| 2124 | case 0x02: |
| 2125 | baseadd_size |= SDRAM_RXBAS_SDSZ_8; |
| 2126 | break; |
| 2127 | case 0x04: |
| 2128 | baseadd_size |= SDRAM_RXBAS_SDSZ_16; |
| 2129 | break; |
| 2130 | case 0x08: |
| 2131 | baseadd_size |= SDRAM_RXBAS_SDSZ_32; |
| 2132 | break; |
| 2133 | case 0x10: |
| 2134 | baseadd_size |= SDRAM_RXBAS_SDSZ_64; |
| 2135 | break; |
| 2136 | case 0x20: |
| 2137 | baseadd_size |= SDRAM_RXBAS_SDSZ_128; |
| 2138 | break; |
| 2139 | case 0x40: |
| 2140 | baseadd_size |= SDRAM_RXBAS_SDSZ_256; |
| 2141 | break; |
| 2142 | case 0x80: |
| 2143 | baseadd_size |= SDRAM_RXBAS_SDSZ_512; |
| 2144 | break; |
| 2145 | default: |
| 2146 | printf("DDR-SDRAM: DIMM %d memory queue configuration.\n", |
| 2147 | (unsigned int)dimm_num); |
| 2148 | printf("ERROR: Unsupported value for the banksize: %d.\n", |
| 2149 | (unsigned int)rank_size_id); |
| 2150 | printf("Replace the DIMM module with a supported DIMM.\n\n"); |
| 2151 | hang(); |
| 2152 | } |
| 2153 | |
| 2154 | if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1)) |
| 2155 | bank_0_populated = 1; |
| 2156 | |
| 2157 | for (i = 0; i < num_ranks; i++) { |
| 2158 | mtdcr_any(rank_reg+i+dimm_num+bank_0_populated, |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 2159 | (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) | |
| 2160 | baseadd_size)); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2161 | rank_base_addr += rank_size_bytes; |
| 2162 | } |
| 2163 | } |
| 2164 | } |
| 2165 | } |
| 2166 | |
| 2167 | /*-----------------------------------------------------------------------------+ |
| 2168 | * is_ecc_enabled. |
| 2169 | *-----------------------------------------------------------------------------*/ |
| 2170 | static unsigned long is_ecc_enabled(void) |
| 2171 | { |
| 2172 | unsigned long dimm_num; |
| 2173 | unsigned long ecc; |
| 2174 | unsigned long val; |
| 2175 | |
| 2176 | ecc = 0; |
| 2177 | /* loop through all the DIMM slots on the board */ |
| 2178 | for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { |
| 2179 | mfsdram(SDRAM_MCOPT1, val); |
| 2180 | ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val)); |
| 2181 | } |
| 2182 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 2183 | return ecc; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2184 | } |
| 2185 | |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2186 | static void blank_string(int size) |
| 2187 | { |
| 2188 | int i; |
| 2189 | |
| 2190 | for (i=0; i<size; i++) |
| 2191 | putc('\b'); |
| 2192 | for (i=0; i<size; i++) |
| 2193 | putc(' '); |
| 2194 | for (i=0; i<size; i++) |
| 2195 | putc('\b'); |
| 2196 | } |
| 2197 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 2198 | #ifdef CONFIG_DDR_ECC |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2199 | /*-----------------------------------------------------------------------------+ |
| 2200 | * program_ecc. |
| 2201 | *-----------------------------------------------------------------------------*/ |
| 2202 | static void program_ecc(unsigned long *dimm_populated, |
| 2203 | unsigned char *iic0_dimm_addr, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2204 | unsigned long num_dimm_banks, |
| 2205 | unsigned long tlb_word2_i_value) |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2206 | { |
| 2207 | unsigned long mcopt1; |
| 2208 | unsigned long mcopt2; |
| 2209 | unsigned long mcstat; |
| 2210 | unsigned long dimm_num; |
| 2211 | unsigned long ecc; |
| 2212 | |
| 2213 | ecc = 0; |
| 2214 | /* loop through all the DIMM slots on the board */ |
| 2215 | for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { |
| 2216 | /* If a dimm is installed in a particular slot ... */ |
| 2217 | if (dimm_populated[dimm_num] != SDRAM_NONE) |
| 2218 | ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11)); |
| 2219 | } |
| 2220 | if (ecc == 0) |
| 2221 | return; |
| 2222 | |
| 2223 | mfsdram(SDRAM_MCOPT1, mcopt1); |
| 2224 | mfsdram(SDRAM_MCOPT2, mcopt2); |
| 2225 | |
| 2226 | if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { |
| 2227 | /* DDR controller must be enabled and not in self-refresh. */ |
| 2228 | mfsdram(SDRAM_MCSTAT, mcstat); |
| 2229 | if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) |
| 2230 | && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) |
| 2231 | && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) |
| 2232 | == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { |
| 2233 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2234 | program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2235 | } |
| 2236 | } |
| 2237 | |
| 2238 | return; |
| 2239 | } |
| 2240 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2241 | #ifdef CONFIG_ECC_ERROR_RESET |
| 2242 | /* |
| 2243 | * Check for ECC errors and reset board upon any error here |
| 2244 | * |
| 2245 | * On the Katmai 440SPe eval board, from time to time, the first |
| 2246 | * lword write access after DDR2 initializazion with ECC checking |
| 2247 | * enabled, leads to an ECC error. I couldn't find a configuration |
| 2248 | * without this happening. On my board with the current setup it |
| 2249 | * happens about 1 from 10 times. |
| 2250 | * |
| 2251 | * The ECC modules used for testing are: |
| 2252 | * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's) |
| 2253 | * |
| 2254 | * This has to get fixed for the Katmai and tested for the other |
| 2255 | * board (440SP/440SPe) that will eventually use this code in the |
| 2256 | * future. |
| 2257 | * |
| 2258 | * 2007-03-01, sr |
| 2259 | */ |
| 2260 | static void check_ecc(void) |
| 2261 | { |
| 2262 | u32 val; |
| 2263 | |
| 2264 | mfsdram(SDRAM_ECCCR, val); |
| 2265 | if (val != 0) { |
| 2266 | printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n", |
| 2267 | val, mfdcr(0x4c), mfdcr(0x4e)); |
| 2268 | printf("ECC error occured, resetting board...\n"); |
| 2269 | do_reset(NULL, 0, 0, NULL); |
| 2270 | } |
| 2271 | } |
| 2272 | #endif |
| 2273 | |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 2274 | static void wait_ddr_idle(void) |
| 2275 | { |
| 2276 | u32 val; |
| 2277 | |
| 2278 | do { |
| 2279 | mfsdram(SDRAM_MCSTAT, val); |
| 2280 | } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); |
| 2281 | } |
| 2282 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2283 | /*-----------------------------------------------------------------------------+ |
| 2284 | * program_ecc_addr. |
| 2285 | *-----------------------------------------------------------------------------*/ |
| 2286 | static void program_ecc_addr(unsigned long start_address, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2287 | unsigned long num_bytes, |
| 2288 | unsigned long tlb_word2_i_value) |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2289 | { |
| 2290 | unsigned long current_address; |
| 2291 | unsigned long end_address; |
| 2292 | unsigned long address_increment; |
| 2293 | unsigned long mcopt1; |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2294 | char str[] = "ECC generation -"; |
| 2295 | char slash[] = "\\|/-\\|/-"; |
| 2296 | int loop = 0; |
| 2297 | int loopi = 0; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2298 | |
| 2299 | current_address = start_address; |
| 2300 | mfsdram(SDRAM_MCOPT1, mcopt1); |
| 2301 | if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { |
| 2302 | mtsdram(SDRAM_MCOPT1, |
| 2303 | (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN); |
| 2304 | sync(); |
| 2305 | eieio(); |
| 2306 | wait_ddr_idle(); |
| 2307 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2308 | puts(str); |
| 2309 | if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { |
| 2310 | /* ECC bit set method for non-cached memory */ |
| 2311 | if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) |
| 2312 | address_increment = 4; |
| 2313 | else |
| 2314 | address_increment = 8; |
| 2315 | end_address = current_address + num_bytes; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2316 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2317 | while (current_address < end_address) { |
| 2318 | *((unsigned long *)current_address) = 0x00000000; |
| 2319 | current_address += address_increment; |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2320 | |
| 2321 | if ((loop++ % (2 << 20)) == 0) { |
| 2322 | putc('\b'); |
| 2323 | putc(slash[loopi++ % 8]); |
| 2324 | } |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2325 | } |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2326 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2327 | } else { |
| 2328 | /* ECC bit set method for cached memory */ |
| 2329 | dcbz_area(start_address, num_bytes); |
| 2330 | dflush(); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2331 | } |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2332 | |
| 2333 | blank_string(strlen(str)); |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2334 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2335 | sync(); |
| 2336 | eieio(); |
| 2337 | wait_ddr_idle(); |
| 2338 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2339 | /* clear ECC error repoting registers */ |
| 2340 | mtsdram(SDRAM_ECCCR, 0xffffffff); |
| 2341 | mtdcr(0x4c, 0xffffffff); |
| 2342 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2343 | mtsdram(SDRAM_MCOPT1, |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2344 | (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2345 | sync(); |
| 2346 | eieio(); |
| 2347 | wait_ddr_idle(); |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 2348 | |
| 2349 | #ifdef CONFIG_ECC_ERROR_RESET |
| 2350 | /* |
| 2351 | * One write to 0 is enough to trigger this ECC error |
| 2352 | * (see description above) |
| 2353 | */ |
| 2354 | out_be32(0, 0x12345678); |
| 2355 | check_ecc(); |
| 2356 | #endif |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2357 | } |
| 2358 | } |
Stefan Roese | df29449 | 2007-03-08 10:06:09 +0100 | [diff] [blame] | 2359 | #endif |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2360 | |
| 2361 | /*-----------------------------------------------------------------------------+ |
| 2362 | * program_DQS_calibration. |
| 2363 | *-----------------------------------------------------------------------------*/ |
| 2364 | static void program_DQS_calibration(unsigned long *dimm_populated, |
| 2365 | unsigned char *iic0_dimm_addr, |
| 2366 | unsigned long num_dimm_banks) |
| 2367 | { |
| 2368 | unsigned long val; |
| 2369 | |
| 2370 | #ifdef HARD_CODED_DQS /* calibration test with hardvalues */ |
| 2371 | mtsdram(SDRAM_RQDC, 0x80000037); |
| 2372 | mtsdram(SDRAM_RDCC, 0x40000000); |
| 2373 | mtsdram(SDRAM_RFDC, 0x000001DF); |
| 2374 | |
| 2375 | test(); |
| 2376 | #else |
| 2377 | /*------------------------------------------------------------------ |
| 2378 | * Program RDCC register |
| 2379 | * Read sample cycle auto-update enable |
| 2380 | *-----------------------------------------------------------------*/ |
| 2381 | |
| 2382 | /* |
| 2383 | * Modified for the Katmai platform: with some DIMMs, the DDR2 |
| 2384 | * controller automatically selects the T2 read cycle, but this |
| 2385 | * proves unreliable. Go ahead and force the DDR2 controller |
| 2386 | * to use the T4 sample and disable the automatic update of the |
| 2387 | * RDSS field. |
| 2388 | */ |
| 2389 | mfsdram(SDRAM_RDCC, val); |
| 2390 | mtsdram(SDRAM_RDCC, |
| 2391 | (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK)) |
| 2392 | | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE)); |
| 2393 | |
| 2394 | /*------------------------------------------------------------------ |
| 2395 | * Program RQDC register |
| 2396 | * Internal DQS delay mechanism enable |
| 2397 | *-----------------------------------------------------------------*/ |
| 2398 | mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38))); |
| 2399 | |
| 2400 | /*------------------------------------------------------------------ |
| 2401 | * Program RFDC register |
| 2402 | * Set Feedback Fractional Oversample |
| 2403 | * Auto-detect read sample cycle enable |
| 2404 | *-----------------------------------------------------------------*/ |
| 2405 | mfsdram(SDRAM_RFDC, val); |
| 2406 | mtsdram(SDRAM_RFDC, |
| 2407 | (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK | |
| 2408 | SDRAM_RFDC_RFFD_MASK)) |
| 2409 | | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) | |
| 2410 | SDRAM_RFDC_RFFD_ENCODE(0))); |
| 2411 | |
| 2412 | DQS_calibration_process(); |
| 2413 | #endif |
| 2414 | } |
| 2415 | |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2416 | static int short_mem_test(void) |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2417 | { |
| 2418 | u32 *membase; |
| 2419 | u32 bxcr_num; |
| 2420 | u32 bxcf; |
| 2421 | int i; |
| 2422 | int j; |
| 2423 | u32 test[NUMMEMTESTS][NUMMEMWORDS] = { |
| 2424 | {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, |
| 2425 | 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, |
| 2426 | {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, |
| 2427 | 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, |
| 2428 | {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, |
| 2429 | 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, |
| 2430 | {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, |
| 2431 | 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, |
| 2432 | {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, |
| 2433 | 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, |
| 2434 | {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, |
| 2435 | 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, |
| 2436 | {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, |
| 2437 | 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, |
| 2438 | {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, |
| 2439 | 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} }; |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2440 | int l; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2441 | |
| 2442 | for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) { |
| 2443 | mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf); |
| 2444 | |
| 2445 | /* Banks enabled */ |
| 2446 | if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2447 | /* Bank is enabled */ |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2448 | |
| 2449 | /*------------------------------------------------------------------ |
| 2450 | * Run the short memory test. |
| 2451 | *-----------------------------------------------------------------*/ |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2452 | membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num))); |
| 2453 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2454 | for (i = 0; i < NUMMEMTESTS; i++) { |
| 2455 | for (j = 0; j < NUMMEMWORDS; j++) { |
| 2456 | membase[j] = test[i][j]; |
| 2457 | ppcDcbf((u32)&(membase[j])); |
| 2458 | } |
| 2459 | sync(); |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2460 | for (l=0; l<NUMLOOPS; l++) { |
| 2461 | for (j = 0; j < NUMMEMWORDS; j++) { |
| 2462 | if (membase[j] != test[i][j]) { |
| 2463 | ppcDcbf((u32)&(membase[j])); |
| 2464 | return 0; |
| 2465 | } |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2466 | ppcDcbf((u32)&(membase[j])); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2467 | } |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2468 | sync(); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2469 | } |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2470 | } |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2471 | } /* if bank enabled */ |
| 2472 | } /* for bxcf_num */ |
| 2473 | |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2474 | return 1; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2475 | } |
| 2476 | |
| 2477 | #ifndef HARD_CODED_DQS |
| 2478 | /*-----------------------------------------------------------------------------+ |
| 2479 | * DQS_calibration_process. |
| 2480 | *-----------------------------------------------------------------------------*/ |
| 2481 | static void DQS_calibration_process(void) |
| 2482 | { |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2483 | unsigned long rfdc_reg; |
| 2484 | unsigned long rffd; |
| 2485 | unsigned long rqdc_reg; |
| 2486 | unsigned long rqfd; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2487 | unsigned long val; |
| 2488 | long rqfd_average; |
| 2489 | long rffd_average; |
| 2490 | long max_start; |
| 2491 | long min_end; |
| 2492 | unsigned long begin_rqfd[MAXRANKS]; |
| 2493 | unsigned long begin_rffd[MAXRANKS]; |
| 2494 | unsigned long end_rqfd[MAXRANKS]; |
| 2495 | unsigned long end_rffd[MAXRANKS]; |
| 2496 | char window_found; |
| 2497 | unsigned long dlycal; |
| 2498 | unsigned long dly_val; |
| 2499 | unsigned long max_pass_length; |
| 2500 | unsigned long current_pass_length; |
| 2501 | unsigned long current_fail_length; |
| 2502 | unsigned long current_start; |
| 2503 | long max_end; |
| 2504 | unsigned char fail_found; |
| 2505 | unsigned char pass_found; |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2506 | u32 rqfd_start; |
| 2507 | char str[] = "Auto calibration -"; |
| 2508 | char slash[] = "\\|/-\\|/-"; |
| 2509 | int loopi = 0; |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2510 | |
| 2511 | /*------------------------------------------------------------------ |
| 2512 | * Test to determine the best read clock delay tuning bits. |
| 2513 | * |
| 2514 | * Before the DDR controller can be used, the read clock delay needs to be |
| 2515 | * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD]. |
| 2516 | * This value cannot be hardcoded into the program because it changes |
| 2517 | * depending on the board's setup and environment. |
| 2518 | * To do this, all delay values are tested to see if they |
| 2519 | * work or not. By doing this, you get groups of fails with groups of |
| 2520 | * passing values. The idea is to find the start and end of a passing |
| 2521 | * window and take the center of it to use as the read clock delay. |
| 2522 | * |
| 2523 | * A failure has to be seen first so that when we hit a pass, we know |
| 2524 | * that it is truely the start of the window. If we get passing values |
| 2525 | * to start off with, we don't know if we are at the start of the window. |
| 2526 | * |
| 2527 | * The code assumes that a failure will always be found. |
| 2528 | * If a failure is not found, there is no easy way to get the middle |
| 2529 | * of the passing window. I guess we can pretty much pick any value |
| 2530 | * but some values will be better than others. Since the lowest speed |
| 2531 | * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed), |
| 2532 | * from experimentation it is safe to say you will always have a failure. |
| 2533 | *-----------------------------------------------------------------*/ |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2534 | |
| 2535 | /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */ |
| 2536 | rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */ |
| 2537 | |
| 2538 | puts(str); |
| 2539 | |
| 2540 | calibration_loop: |
| 2541 | mfsdram(SDRAM_RQDC, rqdc_reg); |
| 2542 | mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | |
| 2543 | SDRAM_RQDC_RQFD_ENCODE(rqfd_start)); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2544 | |
| 2545 | max_start = 0; |
| 2546 | min_end = 0; |
| 2547 | begin_rqfd[0] = 0; |
| 2548 | begin_rffd[0] = 0; |
| 2549 | begin_rqfd[1] = 0; |
| 2550 | begin_rffd[1] = 0; |
| 2551 | end_rqfd[0] = 0; |
| 2552 | end_rffd[0] = 0; |
| 2553 | end_rqfd[1] = 0; |
| 2554 | end_rffd[1] = 0; |
| 2555 | window_found = FALSE; |
| 2556 | |
| 2557 | max_pass_length = 0; |
| 2558 | max_start = 0; |
| 2559 | max_end = 0; |
| 2560 | current_pass_length = 0; |
| 2561 | current_fail_length = 0; |
| 2562 | current_start = 0; |
| 2563 | window_found = FALSE; |
| 2564 | fail_found = FALSE; |
| 2565 | pass_found = FALSE; |
| 2566 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2567 | /* |
| 2568 | * get the delay line calibration register value |
| 2569 | */ |
| 2570 | mfsdram(SDRAM_DLCR, dlycal); |
| 2571 | dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2; |
| 2572 | |
| 2573 | for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) { |
| 2574 | mfsdram(SDRAM_RFDC, rfdc_reg); |
| 2575 | rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK); |
| 2576 | |
| 2577 | /*------------------------------------------------------------------ |
| 2578 | * Set the timing reg for the test. |
| 2579 | *-----------------------------------------------------------------*/ |
| 2580 | mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd)); |
| 2581 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2582 | /*------------------------------------------------------------------ |
| 2583 | * See if the rffd value passed. |
| 2584 | *-----------------------------------------------------------------*/ |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2585 | if (short_mem_test()) { |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2586 | if (fail_found == TRUE) { |
| 2587 | pass_found = TRUE; |
| 2588 | if (current_pass_length == 0) |
| 2589 | current_start = rffd; |
| 2590 | |
| 2591 | current_fail_length = 0; |
| 2592 | current_pass_length++; |
| 2593 | |
| 2594 | if (current_pass_length > max_pass_length) { |
| 2595 | max_pass_length = current_pass_length; |
| 2596 | max_start = current_start; |
| 2597 | max_end = rffd; |
| 2598 | } |
| 2599 | } |
| 2600 | } else { |
| 2601 | current_pass_length = 0; |
| 2602 | current_fail_length++; |
| 2603 | |
| 2604 | if (current_fail_length >= (dly_val >> 2)) { |
| 2605 | if (fail_found == FALSE) { |
| 2606 | fail_found = TRUE; |
| 2607 | } else if (pass_found == TRUE) { |
| 2608 | window_found = TRUE; |
| 2609 | break; |
| 2610 | } |
| 2611 | } |
| 2612 | } |
| 2613 | } /* for rffd */ |
| 2614 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2615 | /*------------------------------------------------------------------ |
| 2616 | * Set the average RFFD value |
| 2617 | *-----------------------------------------------------------------*/ |
| 2618 | rffd_average = ((max_start + max_end) >> 1); |
| 2619 | |
| 2620 | if (rffd_average < 0) |
| 2621 | rffd_average = 0; |
| 2622 | |
| 2623 | if (rffd_average > SDRAM_RFDC_RFFD_MAX) |
| 2624 | rffd_average = SDRAM_RFDC_RFFD_MAX; |
| 2625 | /* now fix RFDC[RFFD] found and find RQDC[RQFD] */ |
| 2626 | mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average)); |
| 2627 | |
| 2628 | max_pass_length = 0; |
| 2629 | max_start = 0; |
| 2630 | max_end = 0; |
| 2631 | current_pass_length = 0; |
| 2632 | current_fail_length = 0; |
| 2633 | current_start = 0; |
| 2634 | window_found = FALSE; |
| 2635 | fail_found = FALSE; |
| 2636 | pass_found = FALSE; |
| 2637 | |
| 2638 | for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { |
| 2639 | mfsdram(SDRAM_RQDC, rqdc_reg); |
| 2640 | rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK); |
| 2641 | |
| 2642 | /*------------------------------------------------------------------ |
| 2643 | * Set the timing reg for the test. |
| 2644 | *-----------------------------------------------------------------*/ |
| 2645 | mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd)); |
| 2646 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2647 | /*------------------------------------------------------------------ |
| 2648 | * See if the rffd value passed. |
| 2649 | *-----------------------------------------------------------------*/ |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2650 | if (short_mem_test()) { |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2651 | if (fail_found == TRUE) { |
| 2652 | pass_found = TRUE; |
| 2653 | if (current_pass_length == 0) |
| 2654 | current_start = rqfd; |
| 2655 | |
| 2656 | current_fail_length = 0; |
| 2657 | current_pass_length++; |
| 2658 | |
| 2659 | if (current_pass_length > max_pass_length) { |
| 2660 | max_pass_length = current_pass_length; |
| 2661 | max_start = current_start; |
| 2662 | max_end = rqfd; |
| 2663 | } |
| 2664 | } |
| 2665 | } else { |
| 2666 | current_pass_length = 0; |
| 2667 | current_fail_length++; |
| 2668 | |
| 2669 | if (fail_found == FALSE) { |
| 2670 | fail_found = TRUE; |
| 2671 | } else if (pass_found == TRUE) { |
| 2672 | window_found = TRUE; |
| 2673 | break; |
| 2674 | } |
| 2675 | } |
| 2676 | } |
| 2677 | |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2678 | rqfd_average = ((max_start + max_end) >> 1); |
| 2679 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2680 | /*------------------------------------------------------------------ |
| 2681 | * Make sure we found the valid read passing window. Halt if not |
| 2682 | *-----------------------------------------------------------------*/ |
| 2683 | if (window_found == FALSE) { |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2684 | if (rqfd_start < SDRAM_RQDC_RQFD_MAX) { |
| 2685 | putc('\b'); |
| 2686 | putc(slash[loopi++ % 8]); |
| 2687 | |
| 2688 | /* try again from with a different RQFD start value */ |
| 2689 | rqfd_start++; |
| 2690 | goto calibration_loop; |
| 2691 | } |
| 2692 | |
| 2693 | printf("\nERROR: Cannot determine a common read delay for the " |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2694 | "DIMM(s) installed.\n"); |
| 2695 | debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__); |
| 2696 | hang(); |
| 2697 | } |
| 2698 | |
Stefan Roese | 94f5470 | 2007-03-31 08:46:08 +0200 | [diff] [blame] | 2699 | blank_string(strlen(str)); |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2700 | |
| 2701 | if (rqfd_average < 0) |
| 2702 | rqfd_average = 0; |
| 2703 | |
| 2704 | if (rqfd_average > SDRAM_RQDC_RQFD_MAX) |
| 2705 | rqfd_average = SDRAM_RQDC_RQFD_MAX; |
| 2706 | |
Stefan Roese | 4037ed3 | 2007-02-20 10:43:34 +0100 | [diff] [blame] | 2707 | mtsdram(SDRAM_RQDC, |
| 2708 | (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) | |
| 2709 | SDRAM_RQDC_RQFD_ENCODE(rqfd_average)); |
| 2710 | |
| 2711 | mfsdram(SDRAM_DLCR, val); |
| 2712 | debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val); |
| 2713 | mfsdram(SDRAM_RQDC, val); |
| 2714 | debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val); |
| 2715 | mfsdram(SDRAM_RFDC, val); |
| 2716 | debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val); |
| 2717 | } |
| 2718 | #else /* calibration test with hardvalues */ |
| 2719 | /*-----------------------------------------------------------------------------+ |
| 2720 | * DQS_calibration_process. |
| 2721 | *-----------------------------------------------------------------------------*/ |
| 2722 | static void test(void) |
| 2723 | { |
| 2724 | unsigned long dimm_num; |
| 2725 | unsigned long ecc_temp; |
| 2726 | unsigned long i, j; |
| 2727 | unsigned long *membase; |
| 2728 | unsigned long bxcf[MAXRANKS]; |
| 2729 | unsigned long val; |
| 2730 | char window_found; |
| 2731 | char begin_found[MAXDIMMS]; |
| 2732 | char end_found[MAXDIMMS]; |
| 2733 | char search_end[MAXDIMMS]; |
| 2734 | unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = { |
| 2735 | {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, |
| 2736 | 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF}, |
| 2737 | {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, |
| 2738 | 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000}, |
| 2739 | {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, |
| 2740 | 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555}, |
| 2741 | {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, |
| 2742 | 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA}, |
| 2743 | {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, |
| 2744 | 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A}, |
| 2745 | {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, |
| 2746 | 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5}, |
| 2747 | {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, |
| 2748 | 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA}, |
| 2749 | {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, |
| 2750 | 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} }; |
| 2751 | |
| 2752 | /*------------------------------------------------------------------ |
| 2753 | * Test to determine the best read clock delay tuning bits. |
| 2754 | * |
| 2755 | * Before the DDR controller can be used, the read clock delay needs to be |
| 2756 | * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD]. |
| 2757 | * This value cannot be hardcoded into the program because it changes |
| 2758 | * depending on the board's setup and environment. |
| 2759 | * To do this, all delay values are tested to see if they |
| 2760 | * work or not. By doing this, you get groups of fails with groups of |
| 2761 | * passing values. The idea is to find the start and end of a passing |
| 2762 | * window and take the center of it to use as the read clock delay. |
| 2763 | * |
| 2764 | * A failure has to be seen first so that when we hit a pass, we know |
| 2765 | * that it is truely the start of the window. If we get passing values |
| 2766 | * to start off with, we don't know if we are at the start of the window. |
| 2767 | * |
| 2768 | * The code assumes that a failure will always be found. |
| 2769 | * If a failure is not found, there is no easy way to get the middle |
| 2770 | * of the passing window. I guess we can pretty much pick any value |
| 2771 | * but some values will be better than others. Since the lowest speed |
| 2772 | * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed), |
| 2773 | * from experimentation it is safe to say you will always have a failure. |
| 2774 | *-----------------------------------------------------------------*/ |
| 2775 | mfsdram(SDRAM_MCOPT1, ecc_temp); |
| 2776 | ecc_temp &= SDRAM_MCOPT1_MCHK_MASK; |
| 2777 | mfsdram(SDRAM_MCOPT1, val); |
| 2778 | mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | |
| 2779 | SDRAM_MCOPT1_MCHK_NON); |
| 2780 | |
| 2781 | window_found = FALSE; |
| 2782 | begin_found[0] = FALSE; |
| 2783 | end_found[0] = FALSE; |
| 2784 | search_end[0] = FALSE; |
| 2785 | begin_found[1] = FALSE; |
| 2786 | end_found[1] = FALSE; |
| 2787 | search_end[1] = FALSE; |
| 2788 | |
| 2789 | for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { |
| 2790 | mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]); |
| 2791 | |
| 2792 | /* Banks enabled */ |
| 2793 | if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { |
| 2794 | |
| 2795 | /* Bank is enabled */ |
| 2796 | membase = |
| 2797 | (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num))); |
| 2798 | |
| 2799 | /*------------------------------------------------------------------ |
| 2800 | * Run the short memory test. |
| 2801 | *-----------------------------------------------------------------*/ |
| 2802 | for (i = 0; i < NUMMEMTESTS; i++) { |
| 2803 | for (j = 0; j < NUMMEMWORDS; j++) { |
| 2804 | membase[j] = test[i][j]; |
| 2805 | ppcDcbf((u32)&(membase[j])); |
| 2806 | } |
| 2807 | sync(); |
| 2808 | for (j = 0; j < NUMMEMWORDS; j++) { |
| 2809 | if (membase[j] != test[i][j]) { |
| 2810 | ppcDcbf((u32)&(membase[j])); |
| 2811 | break; |
| 2812 | } |
| 2813 | ppcDcbf((u32)&(membase[j])); |
| 2814 | } |
| 2815 | sync(); |
| 2816 | if (j < NUMMEMWORDS) |
| 2817 | break; |
| 2818 | } |
| 2819 | |
| 2820 | /*------------------------------------------------------------------ |
| 2821 | * See if the rffd value passed. |
| 2822 | *-----------------------------------------------------------------*/ |
| 2823 | if (i < NUMMEMTESTS) { |
| 2824 | if ((end_found[dimm_num] == FALSE) && |
| 2825 | (search_end[dimm_num] == TRUE)) { |
| 2826 | end_found[dimm_num] = TRUE; |
| 2827 | } |
| 2828 | if ((end_found[0] == TRUE) && |
| 2829 | (end_found[1] == TRUE)) |
| 2830 | break; |
| 2831 | } else { |
| 2832 | if (begin_found[dimm_num] == FALSE) { |
| 2833 | begin_found[dimm_num] = TRUE; |
| 2834 | search_end[dimm_num] = TRUE; |
| 2835 | } |
| 2836 | } |
| 2837 | } else { |
| 2838 | begin_found[dimm_num] = TRUE; |
| 2839 | end_found[dimm_num] = TRUE; |
| 2840 | } |
| 2841 | } |
| 2842 | |
| 2843 | if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE)) |
| 2844 | window_found = TRUE; |
| 2845 | |
| 2846 | /*------------------------------------------------------------------ |
| 2847 | * Make sure we found the valid read passing window. Halt if not |
| 2848 | *-----------------------------------------------------------------*/ |
| 2849 | if (window_found == FALSE) { |
| 2850 | printf("ERROR: Cannot determine a common read delay for the " |
| 2851 | "DIMM(s) installed.\n"); |
| 2852 | hang(); |
| 2853 | } |
| 2854 | |
| 2855 | /*------------------------------------------------------------------ |
| 2856 | * Restore the ECC variable to what it originally was |
| 2857 | *-----------------------------------------------------------------*/ |
| 2858 | mtsdram(SDRAM_MCOPT1, |
| 2859 | (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK) |
| 2860 | | ecc_temp); |
| 2861 | } |
| 2862 | #endif |
| 2863 | |
| 2864 | #if defined(DEBUG) |
| 2865 | static void ppc440sp_sdram_register_dump(void) |
| 2866 | { |
| 2867 | unsigned int sdram_reg; |
| 2868 | unsigned int sdram_data; |
| 2869 | unsigned int dcr_data; |
| 2870 | |
| 2871 | printf("\n Register Dump:\n"); |
| 2872 | sdram_reg = SDRAM_MCSTAT; |
| 2873 | mfsdram(sdram_reg, sdram_data); |
| 2874 | printf(" SDRAM_MCSTAT = 0x%08X", sdram_data); |
| 2875 | sdram_reg = SDRAM_MCOPT1; |
| 2876 | mfsdram(sdram_reg, sdram_data); |
| 2877 | printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data); |
| 2878 | sdram_reg = SDRAM_MCOPT2; |
| 2879 | mfsdram(sdram_reg, sdram_data); |
| 2880 | printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data); |
| 2881 | sdram_reg = SDRAM_MODT0; |
| 2882 | mfsdram(sdram_reg, sdram_data); |
| 2883 | printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data); |
| 2884 | sdram_reg = SDRAM_MODT1; |
| 2885 | mfsdram(sdram_reg, sdram_data); |
| 2886 | printf(" SDRAM_MODT1 = 0x%08X", sdram_data); |
| 2887 | sdram_reg = SDRAM_MODT2; |
| 2888 | mfsdram(sdram_reg, sdram_data); |
| 2889 | printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data); |
| 2890 | sdram_reg = SDRAM_MODT3; |
| 2891 | mfsdram(sdram_reg, sdram_data); |
| 2892 | printf(" SDRAM_MODT3 = 0x%08X", sdram_data); |
| 2893 | sdram_reg = SDRAM_CODT; |
| 2894 | mfsdram(sdram_reg, sdram_data); |
| 2895 | printf(" SDRAM_CODT = 0x%08X\n", sdram_data); |
| 2896 | sdram_reg = SDRAM_VVPR; |
| 2897 | mfsdram(sdram_reg, sdram_data); |
| 2898 | printf(" SDRAM_VVPR = 0x%08X", sdram_data); |
| 2899 | sdram_reg = SDRAM_OPARS; |
| 2900 | mfsdram(sdram_reg, sdram_data); |
| 2901 | printf(" SDRAM_OPARS = 0x%08X\n", sdram_data); |
| 2902 | /* |
| 2903 | * OPAR2 is only used as a trigger register. |
| 2904 | * No data is contained in this register, and reading or writing |
| 2905 | * to is can cause bad things to happen (hangs). Just skip it |
| 2906 | * and report NA |
| 2907 | * sdram_reg = SDRAM_OPAR2; |
| 2908 | * mfsdram(sdram_reg, sdram_data); |
| 2909 | * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data); |
| 2910 | */ |
| 2911 | printf(" SDRAM_OPART = N/A "); |
| 2912 | sdram_reg = SDRAM_RTR; |
| 2913 | mfsdram(sdram_reg, sdram_data); |
| 2914 | printf(" SDRAM_RTR = 0x%08X\n", sdram_data); |
| 2915 | sdram_reg = SDRAM_MB0CF; |
| 2916 | mfsdram(sdram_reg, sdram_data); |
| 2917 | printf(" SDRAM_MB0CF = 0x%08X", sdram_data); |
| 2918 | sdram_reg = SDRAM_MB1CF; |
| 2919 | mfsdram(sdram_reg, sdram_data); |
| 2920 | printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data); |
| 2921 | sdram_reg = SDRAM_MB2CF; |
| 2922 | mfsdram(sdram_reg, sdram_data); |
| 2923 | printf(" SDRAM_MB2CF = 0x%08X", sdram_data); |
| 2924 | sdram_reg = SDRAM_MB3CF; |
| 2925 | mfsdram(sdram_reg, sdram_data); |
| 2926 | printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data); |
| 2927 | sdram_reg = SDRAM_INITPLR0; |
| 2928 | mfsdram(sdram_reg, sdram_data); |
| 2929 | printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data); |
| 2930 | sdram_reg = SDRAM_INITPLR1; |
| 2931 | mfsdram(sdram_reg, sdram_data); |
| 2932 | printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data); |
| 2933 | sdram_reg = SDRAM_INITPLR2; |
| 2934 | mfsdram(sdram_reg, sdram_data); |
| 2935 | printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data); |
| 2936 | sdram_reg = SDRAM_INITPLR3; |
| 2937 | mfsdram(sdram_reg, sdram_data); |
| 2938 | printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data); |
| 2939 | sdram_reg = SDRAM_INITPLR4; |
| 2940 | mfsdram(sdram_reg, sdram_data); |
| 2941 | printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data); |
| 2942 | sdram_reg = SDRAM_INITPLR5; |
| 2943 | mfsdram(sdram_reg, sdram_data); |
| 2944 | printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data); |
| 2945 | sdram_reg = SDRAM_INITPLR6; |
| 2946 | mfsdram(sdram_reg, sdram_data); |
| 2947 | printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data); |
| 2948 | sdram_reg = SDRAM_INITPLR7; |
| 2949 | mfsdram(sdram_reg, sdram_data); |
| 2950 | printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data); |
| 2951 | sdram_reg = SDRAM_INITPLR8; |
| 2952 | mfsdram(sdram_reg, sdram_data); |
| 2953 | printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data); |
| 2954 | sdram_reg = SDRAM_INITPLR9; |
| 2955 | mfsdram(sdram_reg, sdram_data); |
| 2956 | printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data); |
| 2957 | sdram_reg = SDRAM_INITPLR10; |
| 2958 | mfsdram(sdram_reg, sdram_data); |
| 2959 | printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data); |
| 2960 | sdram_reg = SDRAM_INITPLR11; |
| 2961 | mfsdram(sdram_reg, sdram_data); |
| 2962 | printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data); |
| 2963 | sdram_reg = SDRAM_INITPLR12; |
| 2964 | mfsdram(sdram_reg, sdram_data); |
| 2965 | printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data); |
| 2966 | sdram_reg = SDRAM_INITPLR13; |
| 2967 | mfsdram(sdram_reg, sdram_data); |
| 2968 | printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data); |
| 2969 | sdram_reg = SDRAM_INITPLR14; |
| 2970 | mfsdram(sdram_reg, sdram_data); |
| 2971 | printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data); |
| 2972 | sdram_reg = SDRAM_INITPLR15; |
| 2973 | mfsdram(sdram_reg, sdram_data); |
| 2974 | printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data); |
| 2975 | sdram_reg = SDRAM_RQDC; |
| 2976 | mfsdram(sdram_reg, sdram_data); |
| 2977 | printf(" SDRAM_RQDC = 0x%08X", sdram_data); |
| 2978 | sdram_reg = SDRAM_RFDC; |
| 2979 | mfsdram(sdram_reg, sdram_data); |
| 2980 | printf(" SDRAM_RFDC = 0x%08X\n", sdram_data); |
| 2981 | sdram_reg = SDRAM_RDCC; |
| 2982 | mfsdram(sdram_reg, sdram_data); |
| 2983 | printf(" SDRAM_RDCC = 0x%08X", sdram_data); |
| 2984 | sdram_reg = SDRAM_DLCR; |
| 2985 | mfsdram(sdram_reg, sdram_data); |
| 2986 | printf(" SDRAM_DLCR = 0x%08X\n", sdram_data); |
| 2987 | sdram_reg = SDRAM_CLKTR; |
| 2988 | mfsdram(sdram_reg, sdram_data); |
| 2989 | printf(" SDRAM_CLKTR = 0x%08X", sdram_data); |
| 2990 | sdram_reg = SDRAM_WRDTR; |
| 2991 | mfsdram(sdram_reg, sdram_data); |
| 2992 | printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data); |
| 2993 | sdram_reg = SDRAM_SDTR1; |
| 2994 | mfsdram(sdram_reg, sdram_data); |
| 2995 | printf(" SDRAM_SDTR1 = 0x%08X", sdram_data); |
| 2996 | sdram_reg = SDRAM_SDTR2; |
| 2997 | mfsdram(sdram_reg, sdram_data); |
| 2998 | printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data); |
| 2999 | sdram_reg = SDRAM_SDTR3; |
| 3000 | mfsdram(sdram_reg, sdram_data); |
| 3001 | printf(" SDRAM_SDTR3 = 0x%08X", sdram_data); |
| 3002 | sdram_reg = SDRAM_MMODE; |
| 3003 | mfsdram(sdram_reg, sdram_data); |
| 3004 | printf(" SDRAM_MMODE = 0x%08X\n", sdram_data); |
| 3005 | sdram_reg = SDRAM_MEMODE; |
| 3006 | mfsdram(sdram_reg, sdram_data); |
| 3007 | printf(" SDRAM_MEMODE = 0x%08X", sdram_data); |
| 3008 | sdram_reg = SDRAM_ECCCR; |
| 3009 | mfsdram(sdram_reg, sdram_data); |
| 3010 | printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data); |
| 3011 | |
| 3012 | dcr_data = mfdcr(SDRAM_R0BAS); |
| 3013 | printf(" MQ0_B0BAS = 0x%08X", dcr_data); |
| 3014 | dcr_data = mfdcr(SDRAM_R1BAS); |
| 3015 | printf(" MQ1_B0BAS = 0x%08X\n", dcr_data); |
| 3016 | dcr_data = mfdcr(SDRAM_R2BAS); |
| 3017 | printf(" MQ2_B0BAS = 0x%08X", dcr_data); |
| 3018 | dcr_data = mfdcr(SDRAM_R3BAS); |
| 3019 | printf(" MQ3_B0BAS = 0x%08X\n", dcr_data); |
| 3020 | } |
| 3021 | #endif |
| 3022 | #endif /* CONFIG_SPD_EEPROM */ |