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Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +02001/*
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3 *
4 * Configuration settings for the MX31ADS Freescale board.
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +02007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Stefano Babic86271112011-03-14 15:43:56 +010012#include <asm/arch/imx-regs.h>
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020013
14 /* High Level Configuration Options */
15#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
16#define CONFIG_MX31 1 /* in a mx31 */
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020017
18#define CONFIG_DISPLAY_CPUINFO
19#define CONFIG_DISPLAY_BOARDINFO
20
Fabio Estevam4ac2e2d2011-06-05 06:26:49 +000021#define CONFIG_SYS_TEXT_BASE 0xA0000000
22
Fabio Estevamda3598a2011-09-22 08:07:16 +000023#define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS
24
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020025/*
26 * Disabled for now due to build problems under Debian and a significant increase
27 * in the final file size: 144260 vs. 109536 Bytes.
28 */
29#if 0
30#define CONFIG_OF_LIBFDT 1
31#define CONFIG_FIT 1
32#define CONFIG_FIT_VERBOSE 1
33#endif
34
35#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
36#define CONFIG_SETUP_MEMORY_TAGS 1
37#define CONFIG_INITRD_TAG 1
38
39/*
40 * Size of malloc() pool
41 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020043
44/*
45 * Hardware drivers
46 */
47
Stefano Babic40f6fff2011-11-22 15:22:39 +010048#define CONFIG_MXC_UART
49#define CONFIG_MXC_UART_BASE UART1_BASE
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020050
Guennadi Liakhovetski0a0b6062008-04-15 13:33:11 +020051#define CONFIG_HARD_SPI 1
52#define CONFIG_MXC_SPI 1
Haavard Skinnemoend255bb02008-05-16 11:10:31 +020053#define CONFIG_DEFAULT_SPI_BUS 1
Stefano Babic9f481e92010-08-23 20:41:19 +020054#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babic5bd9a9b2011-08-26 11:44:52 +020055#define CONFIG_MXC_GPIO
Guennadi Liakhovetski0a0b6062008-04-15 13:33:11 +020056
Stefano Babicd7d67802011-10-08 11:02:53 +020057/* PMIC Controller */
Ɓukasz Majewskibe3b51a2012-11-13 03:22:14 +000058#define CONFIG_POWER
59#define CONFIG_POWER_SPI
60#define CONFIG_POWER_FSL
Stefano Babicdfe5e142010-04-16 17:11:19 +020061#define CONFIG_FSL_PMIC_BUS 1
62#define CONFIG_FSL_PMIC_CS 0
63#define CONFIG_FSL_PMIC_CLK 1000000
Stefano Babic9f481e92010-08-23 20:41:19 +020064#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
Stefano Babicd7d67802011-10-08 11:02:53 +020065#define CONFIG_FSL_PMIC_BITLEN 32
Fabio Estevam4e8b7542011-10-24 06:44:15 +000066#define CONFIG_RTC_MC13XXX
Guennadi Liakhovetski0a0b6062008-04-15 13:33:11 +020067
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020068/* allow to overwrite serial and ethaddr */
69#define CONFIG_ENV_OVERWRITE
70#define CONFIG_CONS_INDEX 1
71#define CONFIG_BAUDRATE 115200
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020072
73/***********************************************************
74 * Command definition
75 ***********************************************************/
76
77#include <config_cmd_default.h>
78
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020079#define CONFIG_CMD_PING
Guennadi Liakhovetski7602ed52008-04-28 00:25:32 +020080#define CONFIG_CMD_DHCP
Guennadi Liakhovetski0a0b6062008-04-15 13:33:11 +020081#define CONFIG_CMD_SPI
82#define CONFIG_CMD_DATE
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020083
84#define CONFIG_BOOTDELAY 3
85
Guennadi Liakhovetski7602ed52008-04-28 00:25:32 +020086#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +020087
Guennadi Liakhovetski0a0b6062008-04-15 13:33:11 +020088#define CONFIG_EXTRA_ENV_SETTINGS \
89 "netdev=eth0\0" \
90 "uboot_addr=0xa0000000\0" \
91 "uboot=mx31ads/u-boot.bin\0" \
92 "kernel=mx31ads/uImage\0" \
93 "nfsroot=/opt/eldk/arm\0" \
94 "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
95 "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \
96 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
97 "bootcmd=run bootcmd_net\0" \
98 "bootcmd_net=run bootargs_base bootargs_nfs; " \
99 "tftpboot ${loadaddr} ${kernel}; bootm\0" \
100 "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \
101 "protect off ${uboot_addr} 0xa003ffff; " \
102 "erase ${uboot_addr} 0xa003ffff; " \
103 "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \
104 "setenv filesize; saveenv\0"
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200105
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700106#define CONFIG_CS8900
107#define CONFIG_CS8900_BASE 0xb4020300
108#define CONFIG_CS8900_BUS16 1 /* follow the Linux driver */
Guennadi Liakhovetskid23ff682008-04-03 17:04:22 +0200109
110/*
111 * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
112 * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
113 * controller inverted. The controller is capable of detecting and correcting
114 * this, but it needs 4 network packets for that. Which means, at startup, you
115 * will not receive answers to the first 4 packest, unless there have been some
116 * broadcasts on the network, or your board is on a hub. Reducing the ARP
117 * timeout from default 5 seconds to 200ms we speed up the initial TFTP
118 * transfer, should the user wish one, significantly.
119 */
120#define CONFIG_ARP_TIMEOUT 200UL
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200121
122/*
123 * Miscellaneous configurable options
124 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200127/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
129#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
130#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
133#define CONFIG_SYS_MEMTEST_END 0x10000
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200136
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200137#define CONFIG_CMDLINE_EDITING 1
138
139/*-----------------------------------------------------------------------
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200140 * Physical Memory Map
141 */
142#define CONFIG_NR_DRAM_BANKS 1
143#define PHYS_SDRAM_1 CSD0_BASE
144#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
Fabio Estevam4ac2e2d2011-06-05 06:26:49 +0000145#define CONFIG_BOARD_EARLY_INIT_F
146
147#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
148#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
149#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
150#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
151 GENERATED_GBL_DATA_SIZE)
152#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
153 CONFIG_SYS_GBL_DATA_OFFSET)
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200154
155/*-----------------------------------------------------------------------
156 * FLASH and environment organization
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_BASE CS0_BASE
159#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
160#define CONFIG_SYS_MAX_FLASH_SECT 262 /* max number of sectors on one chip */
161#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
162#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200163
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200164#define CONFIG_ENV_IS_IN_FLASH 1
Felix Radenskyba8dcca2011-06-06 05:06:07 +0000165#define CONFIG_ENV_SECT_SIZE (128 * 1024)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200166#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Felix Radenskyba8dcca2011-06-06 05:06:07 +0000167#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Guennadi Liakhovetskid23ff682008-04-03 17:04:22 +0200168
169/* Address and size of Redundant Environment Sector */
Felix Radenskyba8dcca2011-06-06 05:06:07 +0000170#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200171#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Guennadi Liakhovetskid23ff682008-04-03 17:04:22 +0200172
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200173
174/*-----------------------------------------------------------------------
175 * CFI FLASH driver setup
176 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200178#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
Guennadi Liakhovetskid23ff682008-04-03 17:04:22 +0200179#define CONFIG_FLASH_SPANSION_S29WS_N 1 /* A non-standard buffered write algorithm */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
181#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200182
183/*
184 * JFFS2 partitions
185 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100186#undef CONFIG_CMD_MTDPARTS
Guennadi Liakhovetskib5dc9b32008-04-14 10:53:12 +0200187#define CONFIG_JFFS2_DEV "nor0"
188
189#endif /* __CONFIG_H */