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Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * (C) Copyright 2019, Xilinx, Inc,
Michal Simek174d72842023-07-10 14:35:49 +02004 * Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +05305 */
6
7#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -07008#include <cpu_func.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053010#include <asm/arch/sys_proto.h>
11#include <memalign.h>
12#include <versalpl.h>
Michal Simek866225f2019-10-04 15:45:29 +020013#include <zynqmp_firmware.h>
Simon Glass90526e92020-05-10 11:39:56 -060014#include <asm/cache.h>
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053015
16static ulong versal_align_dma_buffer(ulong *buf, u32 len)
17{
18 ulong *new_buf;
19
20 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
21 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
22 memcpy(new_buf, buf, len);
23 buf = new_buf;
24 }
25
26 return (ulong)buf;
27}
28
29static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
Oleksandr Suvorov3e784812022-07-22 17:16:10 +030030 bitstream_type bstype, int flags)
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053031{
32 ulong bin_buf;
33 int ret;
34 u32 buf_lo, buf_hi;
Ibai Erkiagaf6cccbb2020-08-04 23:17:26 +010035 u32 ret_payload[PAYLOAD_ARG_CNT];
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053036
37 bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
38
39 debug("%s called!\n", __func__);
40 flush_dcache_range(bin_buf, bin_buf + bsize);
41
42 buf_lo = lower_32_bits(bin_buf);
43 buf_hi = upper_32_bits(bin_buf);
44
Michal Simek65962702019-10-04 15:52:43 +020045 ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053046 buf_hi, 0, ret_payload);
47 if (ret)
T Karthik Reddy33d3f8e2020-05-14 07:49:36 -060048 printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053049
50 return ret;
51}
52
53struct xilinx_fpga_op versal_op = {
54 .load = versal_load,
55};