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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00002/*
wdenk97d80fc2004-06-09 00:34:46 +00003 * Freescale Three Speed Ethernet Controller driver
wdenk42d1f032003-10-15 23:53:47 +00004 *
Claudiu Manoilaec84bf2013-09-30 12:44:42 +03005 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00006 * (C) Copyright 2003, Motorola, Inc.
wdenk42d1f032003-10-15 23:53:47 +00007 * author Andy Fleming
wdenk42d1f032003-10-15 23:53:47 +00008 */
9
10#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000011#include <common.h>
Bin Meng9a1d6af2016-01-11 22:41:24 -080012#include <dm.h>
wdenk42d1f032003-10-15 23:53:47 +000013#include <malloc.h>
14#include <net.h>
15#include <command.h>
Andy Flemingdd3d1f52008-08-31 16:33:25 -050016#include <tsec.h>
Andy Fleming063c1262011-04-08 02:10:54 -050017#include <fsl_mdio.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090018#include <linux/errno.h>
chenhui zhaoaada81d2011-10-03 08:38:50 -050019#include <asm/processor.h>
Alison Wang52d00a82014-09-05 13:52:38 +080020#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000021
Bin Meng9a1d6af2016-01-11 22:41:24 -080022#ifndef CONFIG_DM_ETH
Andy Fleming75b9d4a2008-08-31 16:33:26 -050023/* Default initializations for TSEC controllers. */
24
25static struct tsec_info_struct tsec_info[] = {
26#ifdef CONFIG_TSEC1
27 STD_TSEC_INFO(1), /* TSEC1 */
28#endif
29#ifdef CONFIG_TSEC2
30 STD_TSEC_INFO(2), /* TSEC2 */
31#endif
32#ifdef CONFIG_MPC85XX_FEC
33 {
Claudiu Manoilaec84bf2013-09-30 12:44:42 +030034 .regs = TSEC_GET_REGS(2, 0x2000),
Andy Fleming75b9d4a2008-08-31 16:33:26 -050035 .devname = CONFIG_MPC85XX_FEC_NAME,
36 .phyaddr = FEC_PHY_ADDR,
Andy Fleming063c1262011-04-08 02:10:54 -050037 .flags = FEC_FLAGS,
38 .mii_devname = DEFAULT_MII_NAME
Andy Fleming75b9d4a2008-08-31 16:33:26 -050039 }, /* FEC */
40#endif
41#ifdef CONFIG_TSEC3
42 STD_TSEC_INFO(3), /* TSEC3 */
43#endif
44#ifdef CONFIG_TSEC4
45 STD_TSEC_INFO(4), /* TSEC4 */
46#endif
47};
Bin Meng9a1d6af2016-01-11 22:41:24 -080048#endif /* CONFIG_DM_ETH */
Andy Fleming75b9d4a2008-08-31 16:33:26 -050049
Andy Fleming2abe3612008-08-31 16:33:27 -050050#define TBIANA_SETTINGS ( \
51 TBIANA_ASYMMETRIC_PAUSE \
52 | TBIANA_SYMMETRIC_PAUSE \
53 | TBIANA_FULL_DUPLEX \
54 )
55
Felix Radensky90b5bf22010-06-28 01:57:39 +030056/* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
57#ifndef CONFIG_TSEC_TBICR_SETTINGS
Kumar Gala72c96a62010-12-01 22:55:54 -060058#define CONFIG_TSEC_TBICR_SETTINGS ( \
Andy Fleming2abe3612008-08-31 16:33:27 -050059 TBICR_PHY_RESET \
Kumar Gala72c96a62010-12-01 22:55:54 -060060 | TBICR_ANEG_ENABLE \
Andy Fleming2abe3612008-08-31 16:33:27 -050061 | TBICR_FULL_DUPLEX \
62 | TBICR_SPEED1_SET \
63 )
Felix Radensky90b5bf22010-06-28 01:57:39 +030064#endif /* CONFIG_TSEC_TBICR_SETTINGS */
Peter Tyser46e91672009-11-03 17:52:07 -060065
Andy Fleming2abe3612008-08-31 16:33:27 -050066/* Configure the TBI for SGMII operation */
67static void tsec_configure_serdes(struct tsec_private *priv)
68{
Bin Meng9872b732016-01-11 22:41:18 -080069 /*
70 * Access TBI PHY registers at given TSEC register offset as opposed
71 * to the register offset used for external PHY accesses
72 */
Andy Fleming063c1262011-04-08 02:10:54 -050073 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixd38de332018-01-15 11:08:21 +010074 0, TBI_ANA, TBIANA_SETTINGS);
Andy Fleming063c1262011-04-08 02:10:54 -050075 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixd38de332018-01-15 11:08:21 +010076 0, TBI_TBICON, TBICON_CLK_SELECT);
Andy Fleming063c1262011-04-08 02:10:54 -050077 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
Mario Sixd38de332018-01-15 11:08:21 +010078 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
Andy Fleming2abe3612008-08-31 16:33:27 -050079}
michael.firth@bt.com55fe7c52008-01-16 11:40:51 +000080
David Updegraff53a5c422007-06-11 10:41:07 -050081#ifdef CONFIG_MCAST_TFTP
82
83/* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
84
85/* Set the appropriate hash bit for the given addr */
86
Bin Meng9872b732016-01-11 22:41:18 -080087/*
88 * The algorithm works like so:
David Updegraff53a5c422007-06-11 10:41:07 -050089 * 1) Take the Destination Address (ie the multicast address), and
90 * do a CRC on it (little endian), and reverse the bits of the
91 * result.
92 * 2) Use the 8 most significant bits as a hash into a 256-entry
93 * table. The table is controlled through 8 32-bit registers:
Claudiu Manoil876d4512013-09-30 12:44:40 +030094 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
95 * 255. This means that the 3 most significant bits in the
David Updegraff53a5c422007-06-11 10:41:07 -050096 * hash index which gaddr register to use, and the 5 other bits
97 * indicate which bit (assuming an IBM numbering scheme, which
Claudiu Manoil876d4512013-09-30 12:44:40 +030098 * for PowerPC (tm) is usually the case) in the register holds
Bin Meng9872b732016-01-11 22:41:18 -080099 * the entry.
100 */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800101#ifndef CONFIG_DM_ETH
Bin Meng9872b732016-01-11 22:41:18 -0800102static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac, u8 set)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800103#else
104static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int set)
105#endif
David Updegraff53a5c422007-06-11 10:41:07 -0500106{
Claudiu Manoilb2002042013-09-30 12:44:41 +0300107 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Claudiu Manoil876d4512013-09-30 12:44:40 +0300108 struct tsec __iomem *regs = priv->regs;
109 u32 result, value;
110 u8 whichbit, whichreg;
David Updegraff53a5c422007-06-11 10:41:07 -0500111
Claudiu Manoil876d4512013-09-30 12:44:40 +0300112 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
113 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
114 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
David Updegraff53a5c422007-06-11 10:41:07 -0500115
Mario Sixd38de332018-01-15 11:08:21 +0100116 value = BIT(31 - whichbit);
David Updegraff53a5c422007-06-11 10:41:07 -0500117
Claudiu Manoil876d4512013-09-30 12:44:40 +0300118 if (set)
119 setbits_be32(&regs->hash.gaddr0 + whichreg, value);
120 else
121 clrbits_be32(&regs->hash.gaddr0 + whichreg, value);
122
David Updegraff53a5c422007-06-11 10:41:07 -0500123 return 0;
124}
125#endif /* Multicast TFTP ? */
Mingkai Hu90751912011-01-27 12:52:46 +0800126
Bin Meng9872b732016-01-11 22:41:18 -0800127/*
128 * Initialized required registers to appropriate values, zeroing
Mingkai Hu90751912011-01-27 12:52:46 +0800129 * those we don't care about (unless zero is bad, in which case,
130 * choose a more appropriate value)
131 */
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300132static void init_registers(struct tsec __iomem *regs)
Mingkai Hu90751912011-01-27 12:52:46 +0800133{
134 /* Clear IEVENT */
135 out_be32(&regs->ievent, IEVENT_INIT_CLEAR);
136
137 out_be32(&regs->imask, IMASK_INIT_CLEAR);
138
139 out_be32(&regs->hash.iaddr0, 0);
140 out_be32(&regs->hash.iaddr1, 0);
141 out_be32(&regs->hash.iaddr2, 0);
142 out_be32(&regs->hash.iaddr3, 0);
143 out_be32(&regs->hash.iaddr4, 0);
144 out_be32(&regs->hash.iaddr5, 0);
145 out_be32(&regs->hash.iaddr6, 0);
146 out_be32(&regs->hash.iaddr7, 0);
147
148 out_be32(&regs->hash.gaddr0, 0);
149 out_be32(&regs->hash.gaddr1, 0);
150 out_be32(&regs->hash.gaddr2, 0);
151 out_be32(&regs->hash.gaddr3, 0);
152 out_be32(&regs->hash.gaddr4, 0);
153 out_be32(&regs->hash.gaddr5, 0);
154 out_be32(&regs->hash.gaddr6, 0);
155 out_be32(&regs->hash.gaddr7, 0);
156
157 out_be32(&regs->rctrl, 0x00000000);
158
159 /* Init RMON mib registers */
Claudiu Manoil82ef75c2013-09-30 12:44:46 +0300160 memset((void *)&regs->rmon, 0, sizeof(regs->rmon));
Mingkai Hu90751912011-01-27 12:52:46 +0800161
162 out_be32(&regs->rmon.cam1, 0xffffffff);
163 out_be32(&regs->rmon.cam2, 0xffffffff);
164
165 out_be32(&regs->mrblr, MRBLR_INIT_SETTINGS);
166
167 out_be32(&regs->minflr, MINFLR_INIT_SETTINGS);
168
169 out_be32(&regs->attr, ATTR_INIT_SETTINGS);
170 out_be32(&regs->attreli, ATTRELI_INIT_SETTINGS);
Mingkai Hu90751912011-01-27 12:52:46 +0800171}
172
Bin Meng9872b732016-01-11 22:41:18 -0800173/*
174 * Configure maccfg2 based on negotiated speed and duplex
Mingkai Hu90751912011-01-27 12:52:46 +0800175 * reported by PHY handling code
176 */
Andy Fleming063c1262011-04-08 02:10:54 -0500177static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
Mingkai Hu90751912011-01-27 12:52:46 +0800178{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300179 struct tsec __iomem *regs = priv->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800180 u32 ecntrl, maccfg2;
181
Andy Fleming063c1262011-04-08 02:10:54 -0500182 if (!phydev->link) {
183 printf("%s: No link.\n", phydev->dev->name);
Mingkai Hu90751912011-01-27 12:52:46 +0800184 return;
185 }
186
187 /* clear all bits relative with interface mode */
188 ecntrl = in_be32(&regs->ecntrl);
189 ecntrl &= ~ECNTRL_R100;
190
191 maccfg2 = in_be32(&regs->maccfg2);
192 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
193
Andy Fleming063c1262011-04-08 02:10:54 -0500194 if (phydev->duplex)
Mingkai Hu90751912011-01-27 12:52:46 +0800195 maccfg2 |= MACCFG2_FULL_DUPLEX;
196
Andy Fleming063c1262011-04-08 02:10:54 -0500197 switch (phydev->speed) {
Mingkai Hu90751912011-01-27 12:52:46 +0800198 case 1000:
199 maccfg2 |= MACCFG2_GMII;
200 break;
201 case 100:
202 case 10:
203 maccfg2 |= MACCFG2_MII;
204
Bin Meng9872b732016-01-11 22:41:18 -0800205 /*
206 * Set R100 bit in all modes although
Mingkai Hu90751912011-01-27 12:52:46 +0800207 * it is only used in RGMII mode
208 */
Andy Fleming063c1262011-04-08 02:10:54 -0500209 if (phydev->speed == 100)
Mingkai Hu90751912011-01-27 12:52:46 +0800210 ecntrl |= ECNTRL_R100;
211 break;
212 default:
Andy Fleming063c1262011-04-08 02:10:54 -0500213 printf("%s: Speed was bad\n", phydev->dev->name);
Mingkai Hu90751912011-01-27 12:52:46 +0800214 break;
215 }
216
217 out_be32(&regs->ecntrl, ecntrl);
218 out_be32(&regs->maccfg2, maccfg2);
219
Andy Fleming063c1262011-04-08 02:10:54 -0500220 printf("Speed: %d, %s duplex%s\n", phydev->speed,
Mario Sixd38de332018-01-15 11:08:21 +0100221 (phydev->duplex) ? "full" : "half",
222 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
Mingkai Hu90751912011-01-27 12:52:46 +0800223}
224
Bin Meng8ba50172016-01-11 22:41:21 -0800225/*
226 * This returns the status bits of the device. The return value
227 * is never checked, and this is what the 8260 driver did, so we
228 * do the same. Presumably, this would be zero if there were no
229 * errors
230 */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800231#ifndef CONFIG_DM_ETH
Bin Meng8ba50172016-01-11 22:41:21 -0800232static int tsec_send(struct eth_device *dev, void *packet, int length)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800233#else
234static int tsec_send(struct udevice *dev, void *packet, int length)
235#endif
Bin Meng8ba50172016-01-11 22:41:21 -0800236{
237 struct tsec_private *priv = (struct tsec_private *)dev->priv;
238 struct tsec __iomem *regs = priv->regs;
Mario Sixd38de332018-01-15 11:08:21 +0100239 u16 status;
Bin Meng8ba50172016-01-11 22:41:21 -0800240 int result = 0;
241 int i;
242
243 /* Find an empty buffer descriptor */
244 for (i = 0;
245 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
246 i++) {
247 if (i >= TOUT_LOOP) {
248 debug("%s: tsec: tx buffers full\n", dev->name);
249 return result;
250 }
251 }
252
253 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
254 out_be16(&priv->txbd[priv->tx_idx].length, length);
255 status = in_be16(&priv->txbd[priv->tx_idx].status);
256 out_be16(&priv->txbd[priv->tx_idx].status, status |
257 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
258
259 /* Tell the DMA to go */
260 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
261
262 /* Wait for buffer to be transmitted */
263 for (i = 0;
264 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
265 i++) {
266 if (i >= TOUT_LOOP) {
267 debug("%s: tsec: tx error\n", dev->name);
268 return result;
269 }
270 }
271
272 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
273 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
274
275 return result;
276}
277
Bin Meng9a1d6af2016-01-11 22:41:24 -0800278#ifndef CONFIG_DM_ETH
Bin Meng8ba50172016-01-11 22:41:21 -0800279static int tsec_recv(struct eth_device *dev)
280{
281 struct tsec_private *priv = (struct tsec_private *)dev->priv;
282 struct tsec __iomem *regs = priv->regs;
283
284 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
285 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
Mario Sixd38de332018-01-15 11:08:21 +0100286 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
Bin Meng8ba50172016-01-11 22:41:21 -0800287 uchar *packet = net_rx_packets[priv->rx_idx];
288
289 /* Send the packet up if there were no errors */
290 if (!(status & RXBD_STATS))
291 net_process_received_packet(packet, length - 4);
292 else
293 printf("Got error %x\n", (status & RXBD_STATS));
294
295 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
296
297 status = RXBD_EMPTY;
298 /* Set the wrap bit if this is the last element in the list */
299 if ((priv->rx_idx + 1) == PKTBUFSRX)
300 status |= RXBD_WRAP;
301 out_be16(&priv->rxbd[priv->rx_idx].status, status);
302
303 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
304 }
305
306 if (in_be32(&regs->ievent) & IEVENT_BSY) {
307 out_be32(&regs->ievent, IEVENT_BSY);
308 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
309 }
310
311 return -1;
312}
Bin Meng9a1d6af2016-01-11 22:41:24 -0800313#else
314static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
315{
316 struct tsec_private *priv = (struct tsec_private *)dev->priv;
317 struct tsec __iomem *regs = priv->regs;
318 int ret = -1;
319
320 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
321 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
Mario Sixd38de332018-01-15 11:08:21 +0100322 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
323 u32 buf;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800324
325 /* Send the packet up if there were no errors */
326 if (!(status & RXBD_STATS)) {
327 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
328 *packetp = (uchar *)buf;
329 ret = length - 4;
330 } else {
331 printf("Got error %x\n", (status & RXBD_STATS));
332 }
333 }
334
335 if (in_be32(&regs->ievent) & IEVENT_BSY) {
336 out_be32(&regs->ievent, IEVENT_BSY);
337 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
338 }
339
340 return ret;
341}
342
343static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
344{
345 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Mario Sixd38de332018-01-15 11:08:21 +0100346 u16 status;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800347
348 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
349
350 status = RXBD_EMPTY;
351 /* Set the wrap bit if this is the last element in the list */
352 if ((priv->rx_idx + 1) == PKTBUFSRX)
353 status |= RXBD_WRAP;
354 out_be16(&priv->rxbd[priv->rx_idx].status, status);
355
356 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
357
358 return 0;
359}
360#endif
Bin Meng8ba50172016-01-11 22:41:21 -0800361
362/* Stop the interface */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800363#ifndef CONFIG_DM_ETH
Bin Meng8ba50172016-01-11 22:41:21 -0800364static void tsec_halt(struct eth_device *dev)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800365#else
366static void tsec_halt(struct udevice *dev)
367#endif
Bin Meng8ba50172016-01-11 22:41:21 -0800368{
369 struct tsec_private *priv = (struct tsec_private *)dev->priv;
370 struct tsec __iomem *regs = priv->regs;
371
372 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
373 setbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
374
375 while ((in_be32(&regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
376 != (IEVENT_GRSC | IEVENT_GTSC))
377 ;
378
379 clrbits_be32(&regs->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
380
381 /* Shut down the PHY, as needed */
382 phy_shutdown(priv->phydev);
383}
384
chenhui zhaoaada81d2011-10-03 08:38:50 -0500385#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
386/*
387 * When MACCFG1[Rx_EN] is enabled during system boot as part
388 * of the eTSEC port initialization sequence,
389 * the eTSEC Rx logic may not be properly initialized.
390 */
Bin Meng56a27a12016-01-11 22:41:22 -0800391void redundant_init(struct tsec_private *priv)
chenhui zhaoaada81d2011-10-03 08:38:50 -0500392{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300393 struct tsec __iomem *regs = priv->regs;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500394 uint t, count = 0;
395 int fail = 1;
396 static const u8 pkt[] = {
397 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
398 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
399 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
400 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
401 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
402 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
403 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
404 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
405 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
406 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
407 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
408 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
409 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
410 0x71, 0x72};
411
412 /* Enable promiscuous mode */
413 setbits_be32(&regs->rctrl, 0x8);
414 /* Enable loopback mode */
415 setbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
416 /* Enable transmit and receive */
417 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
418
419 /* Tell the DMA it is clear to go */
420 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
421 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
422 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
423 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
424
425 do {
Mario Sixd38de332018-01-15 11:08:21 +0100426 u16 status;
427
Bin Meng56a27a12016-01-11 22:41:22 -0800428 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
chenhui zhaoaada81d2011-10-03 08:38:50 -0500429
430 /* Wait for buffer to be received */
Bin Menge677da92016-01-11 22:41:20 -0800431 for (t = 0;
432 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
Bin Meng362b1232016-01-11 22:41:19 -0800433 t++) {
chenhui zhaoaada81d2011-10-03 08:38:50 -0500434 if (t >= 10 * TOUT_LOOP) {
Bin Meng56a27a12016-01-11 22:41:22 -0800435 printf("%s: tsec: rx error\n", priv->dev->name);
chenhui zhaoaada81d2011-10-03 08:38:50 -0500436 break;
437 }
438 }
439
Bin Meng362b1232016-01-11 22:41:19 -0800440 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
chenhui zhaoaada81d2011-10-03 08:38:50 -0500441 fail = 0;
442
Bin Menge677da92016-01-11 22:41:20 -0800443 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300444 status = RXBD_EMPTY;
Bin Meng362b1232016-01-11 22:41:19 -0800445 if ((priv->rx_idx + 1) == PKTBUFSRX)
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300446 status |= RXBD_WRAP;
Bin Menge677da92016-01-11 22:41:20 -0800447 out_be16(&priv->rxbd[priv->rx_idx].status, status);
Bin Meng362b1232016-01-11 22:41:19 -0800448 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500449
450 if (in_be32(&regs->ievent) & IEVENT_BSY) {
451 out_be32(&regs->ievent, IEVENT_BSY);
452 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
453 }
454 if (fail) {
455 printf("loopback recv packet error!\n");
456 clrbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
457 udelay(1000);
458 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN);
459 }
460 } while ((count++ < 4) && (fail == 1));
461
462 if (fail)
463 panic("eTSEC init fail!\n");
464 /* Disable promiscuous mode */
465 clrbits_be32(&regs->rctrl, 0x8);
466 /* Disable loopback mode */
467 clrbits_be32(&regs->maccfg1, MACCFG1_LOOPBACK);
468}
469#endif
470
Bin Meng9872b732016-01-11 22:41:18 -0800471/*
472 * Set up the buffers and their descriptors, and bring up the
Mingkai Hu90751912011-01-27 12:52:46 +0800473 * interface
474 */
Bin Meng56a27a12016-01-11 22:41:22 -0800475static void startup_tsec(struct tsec_private *priv)
Mingkai Hu90751912011-01-27 12:52:46 +0800476{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300477 struct tsec __iomem *regs = priv->regs;
Mario Sixd38de332018-01-15 11:08:21 +0100478 u16 status;
Claudiu Manoil9c9141f2013-10-04 19:13:53 +0300479 int i;
Mingkai Hu90751912011-01-27 12:52:46 +0800480
Andy Fleming063c1262011-04-08 02:10:54 -0500481 /* reset the indices to zero */
Bin Meng362b1232016-01-11 22:41:19 -0800482 priv->rx_idx = 0;
483 priv->tx_idx = 0;
chenhui zhaoaada81d2011-10-03 08:38:50 -0500484#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
485 uint svr;
486#endif
Andy Fleming063c1262011-04-08 02:10:54 -0500487
Mingkai Hu90751912011-01-27 12:52:46 +0800488 /* Point to the buffer descriptors */
Bin Menge677da92016-01-11 22:41:20 -0800489 out_be32(&regs->tbase, (u32)&priv->txbd[0]);
490 out_be32(&regs->rbase, (u32)&priv->rxbd[0]);
Mingkai Hu90751912011-01-27 12:52:46 +0800491
492 /* Initialize the Rx Buffer descriptors */
493 for (i = 0; i < PKTBUFSRX; i++) {
Bin Menge677da92016-01-11 22:41:20 -0800494 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
495 out_be16(&priv->rxbd[i].length, 0);
496 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
Mingkai Hu90751912011-01-27 12:52:46 +0800497 }
Bin Menge677da92016-01-11 22:41:20 -0800498 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
499 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
Mingkai Hu90751912011-01-27 12:52:46 +0800500
501 /* Initialize the TX Buffer Descriptors */
502 for (i = 0; i < TX_BUF_CNT; i++) {
Bin Menge677da92016-01-11 22:41:20 -0800503 out_be16(&priv->txbd[i].status, 0);
504 out_be16(&priv->txbd[i].length, 0);
505 out_be32(&priv->txbd[i].bufptr, 0);
Mingkai Hu90751912011-01-27 12:52:46 +0800506 }
Bin Menge677da92016-01-11 22:41:20 -0800507 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
508 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
Mingkai Hu90751912011-01-27 12:52:46 +0800509
chenhui zhaoaada81d2011-10-03 08:38:50 -0500510#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
511 svr = get_svr();
512 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
Bin Meng56a27a12016-01-11 22:41:22 -0800513 redundant_init(priv);
chenhui zhaoaada81d2011-10-03 08:38:50 -0500514#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800515 /* Enable Transmit and Receive */
516 setbits_be32(&regs->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
517
518 /* Tell the DMA it is clear to go */
519 setbits_be32(&regs->dmactrl, DMACTRL_INIT_SETTINGS);
520 out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
521 out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
522 clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
523}
524
Bin Meng9872b732016-01-11 22:41:18 -0800525/*
Bin Meng9872b732016-01-11 22:41:18 -0800526 * Initializes data structures and registers for the controller,
527 * and brings the interface up. Returns the link status, meaning
Mingkai Hu90751912011-01-27 12:52:46 +0800528 * that it returns success if the link is up, failure otherwise.
Bin Meng9872b732016-01-11 22:41:18 -0800529 * This allows U-Boot to find the first active controller.
Mingkai Hu90751912011-01-27 12:52:46 +0800530 */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800531#ifndef CONFIG_DM_ETH
Mario Sixd38de332018-01-15 11:08:21 +0100532static int tsec_init(struct eth_device *dev, bd_t *bd)
Bin Meng9a1d6af2016-01-11 22:41:24 -0800533#else
534static int tsec_init(struct udevice *dev)
535#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800536{
Mingkai Hu90751912011-01-27 12:52:46 +0800537 struct tsec_private *priv = (struct tsec_private *)dev->priv;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800538#ifdef CONFIG_DM_ETH
539 struct eth_pdata *pdata = dev_get_platdata(dev);
540#endif
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300541 struct tsec __iomem *regs = priv->regs;
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300542 u32 tempval;
Timur Tabi11af8d62012-07-09 08:52:43 +0000543 int ret;
Mingkai Hu90751912011-01-27 12:52:46 +0800544
545 /* Make sure the controller is stopped */
546 tsec_halt(dev);
547
548 /* Init MACCFG2. Defaults to GMII */
549 out_be32(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
550
551 /* Init ECNTRL */
552 out_be32(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
553
Bin Meng9872b732016-01-11 22:41:18 -0800554 /*
555 * Copy the station address into the address registers.
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300556 * For a station address of 0x12345678ABCD in transmission
557 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
558 * MACnADDR2 is set to 0x34120000.
559 */
Bin Meng9a1d6af2016-01-11 22:41:24 -0800560#ifndef CONFIG_DM_ETH
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300561 tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
562 (dev->enetaddr[3] << 8) | dev->enetaddr[2];
Bin Meng9a1d6af2016-01-11 22:41:24 -0800563#else
564 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
565 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
566#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800567
568 out_be32(&regs->macstnaddr1, tempval);
569
Bin Meng9a1d6af2016-01-11 22:41:24 -0800570#ifndef CONFIG_DM_ETH
Claudiu Manoilb1690bc2013-09-30 12:44:47 +0300571 tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
Bin Meng9a1d6af2016-01-11 22:41:24 -0800572#else
573 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
574#endif
Mingkai Hu90751912011-01-27 12:52:46 +0800575
576 out_be32(&regs->macstnaddr2, tempval);
577
Mingkai Hu90751912011-01-27 12:52:46 +0800578 /* Clear out (for the most part) the other registers */
579 init_registers(regs);
580
581 /* Ready the device for tx/rx */
Bin Meng56a27a12016-01-11 22:41:22 -0800582 startup_tsec(priv);
Mingkai Hu90751912011-01-27 12:52:46 +0800583
Andy Fleming063c1262011-04-08 02:10:54 -0500584 /* Start up the PHY */
Timur Tabi11af8d62012-07-09 08:52:43 +0000585 ret = phy_startup(priv->phydev);
586 if (ret) {
587 printf("Could not initialize PHY %s\n",
588 priv->phydev->dev->name);
589 return ret;
590 }
Andy Fleming063c1262011-04-08 02:10:54 -0500591
592 adjust_link(priv, priv->phydev);
593
Mingkai Hu90751912011-01-27 12:52:46 +0800594 /* If there's no link, fail */
Andy Fleming063c1262011-04-08 02:10:54 -0500595 return priv->phydev->link ? 0 : -1;
Mingkai Hu90751912011-01-27 12:52:46 +0800596}
597
Andy Fleming063c1262011-04-08 02:10:54 -0500598static phy_interface_t tsec_get_interface(struct tsec_private *priv)
599{
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300600 struct tsec __iomem *regs = priv->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500601 u32 ecntrl;
602
603 ecntrl = in_be32(&regs->ecntrl);
604
605 if (ecntrl & ECNTRL_SGMII_MODE)
606 return PHY_INTERFACE_MODE_SGMII;
607
608 if (ecntrl & ECNTRL_TBI_MODE) {
609 if (ecntrl & ECNTRL_REDUCED_MODE)
610 return PHY_INTERFACE_MODE_RTBI;
611 else
612 return PHY_INTERFACE_MODE_TBI;
613 }
614
615 if (ecntrl & ECNTRL_REDUCED_MODE) {
Mario Sixd38de332018-01-15 11:08:21 +0100616 phy_interface_t interface;
617
Andy Fleming063c1262011-04-08 02:10:54 -0500618 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
619 return PHY_INTERFACE_MODE_RMII;
Andy Fleming063c1262011-04-08 02:10:54 -0500620
Mario Sixd38de332018-01-15 11:08:21 +0100621 interface = priv->interface;
Andy Fleming063c1262011-04-08 02:10:54 -0500622
Mario Sixd38de332018-01-15 11:08:21 +0100623 /*
624 * This isn't autodetected, so it must
625 * be set by the platform code.
626 */
627 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
628 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
629 interface == PHY_INTERFACE_MODE_RGMII_RXID)
630 return interface;
631
632 return PHY_INTERFACE_MODE_RGMII;
Andy Fleming063c1262011-04-08 02:10:54 -0500633 }
634
635 if (priv->flags & TSEC_GIGABIT)
636 return PHY_INTERFACE_MODE_GMII;
637
638 return PHY_INTERFACE_MODE_MII;
639}
640
Bin Meng9872b732016-01-11 22:41:18 -0800641/*
642 * Discover which PHY is attached to the device, and configure it
Mingkai Hu90751912011-01-27 12:52:46 +0800643 * properly. If the PHY is not recognized, then return 0
644 * (failure). Otherwise, return 1
645 */
Bin Meng56a27a12016-01-11 22:41:22 -0800646static int init_phy(struct tsec_private *priv)
Mingkai Hu90751912011-01-27 12:52:46 +0800647{
Andy Fleming063c1262011-04-08 02:10:54 -0500648 struct phy_device *phydev;
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300649 struct tsec __iomem *regs = priv->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500650 u32 supported = (SUPPORTED_10baseT_Half |
651 SUPPORTED_10baseT_Full |
652 SUPPORTED_100baseT_Half |
653 SUPPORTED_100baseT_Full);
654
655 if (priv->flags & TSEC_GIGABIT)
656 supported |= SUPPORTED_1000baseT_Full;
Mingkai Hu90751912011-01-27 12:52:46 +0800657
658 /* Assign a Physical address to the TBI */
Bin Menga1c76c12016-01-11 22:41:25 -0800659 out_be32(&regs->tbipa, priv->tbiaddr);
Mingkai Hu90751912011-01-27 12:52:46 +0800660
Andy Fleming063c1262011-04-08 02:10:54 -0500661 priv->interface = tsec_get_interface(priv);
Mingkai Hu90751912011-01-27 12:52:46 +0800662
Andy Fleming063c1262011-04-08 02:10:54 -0500663 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
Mingkai Hu90751912011-01-27 12:52:46 +0800664 tsec_configure_serdes(priv);
665
Bin Meng56a27a12016-01-11 22:41:22 -0800666 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
667 priv->interface);
Claudiu Manoil7f233c02013-12-10 15:21:04 +0200668 if (!phydev)
669 return 0;
Mingkai Hu90751912011-01-27 12:52:46 +0800670
Andy Fleming063c1262011-04-08 02:10:54 -0500671 phydev->supported &= supported;
672 phydev->advertising = phydev->supported;
673
674 priv->phydev = phydev;
675
676 phy_config(phydev);
Mingkai Hu90751912011-01-27 12:52:46 +0800677
678 return 1;
679}
680
Bin Meng9a1d6af2016-01-11 22:41:24 -0800681#ifndef CONFIG_DM_ETH
Bin Meng9872b732016-01-11 22:41:18 -0800682/*
683 * Initialize device structure. Returns success if PHY
Mingkai Hu90751912011-01-27 12:52:46 +0800684 * initialization succeeded (i.e. if it recognizes the PHY)
685 */
686static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
687{
688 struct eth_device *dev;
689 int i;
690 struct tsec_private *priv;
691
Mario Sixd38de332018-01-15 11:08:21 +0100692 dev = (struct eth_device *)malloc(sizeof(*dev));
Mingkai Hu90751912011-01-27 12:52:46 +0800693
Mario Sixd38de332018-01-15 11:08:21 +0100694 if (!dev)
Mingkai Hu90751912011-01-27 12:52:46 +0800695 return 0;
696
Mario Sixd38de332018-01-15 11:08:21 +0100697 memset(dev, 0, sizeof(*dev));
Mingkai Hu90751912011-01-27 12:52:46 +0800698
699 priv = (struct tsec_private *)malloc(sizeof(*priv));
700
Mario Six5775f002018-01-15 11:08:22 +0100701 if (!priv) {
702 free(dev);
Mingkai Hu90751912011-01-27 12:52:46 +0800703 return 0;
Mario Six5775f002018-01-15 11:08:22 +0100704 }
Mingkai Hu90751912011-01-27 12:52:46 +0800705
Mingkai Hu90751912011-01-27 12:52:46 +0800706 priv->regs = tsec_info->regs;
Mingkai Hu90751912011-01-27 12:52:46 +0800707 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
708
709 priv->phyaddr = tsec_info->phyaddr;
Bin Menga1c76c12016-01-11 22:41:25 -0800710 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
Mingkai Hu90751912011-01-27 12:52:46 +0800711 priv->flags = tsec_info->flags;
712
Ben Whitten192bc692015-12-30 13:05:58 +0000713 strcpy(dev->name, tsec_info->devname);
Andy Fleming063c1262011-04-08 02:10:54 -0500714 priv->interface = tsec_info->interface;
715 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
Bin Meng56a27a12016-01-11 22:41:22 -0800716 priv->dev = dev;
Mingkai Hu90751912011-01-27 12:52:46 +0800717 dev->iobase = 0;
718 dev->priv = priv;
719 dev->init = tsec_init;
720 dev->halt = tsec_halt;
721 dev->send = tsec_send;
722 dev->recv = tsec_recv;
723#ifdef CONFIG_MCAST_TFTP
724 dev->mcast = tsec_mcast_addr;
725#endif
726
Bin Meng9872b732016-01-11 22:41:18 -0800727 /* Tell U-Boot to get the addr from the env */
Mingkai Hu90751912011-01-27 12:52:46 +0800728 for (i = 0; i < 6; i++)
729 dev->enetaddr[i] = 0;
730
731 eth_register(dev);
732
733 /* Reset the MAC */
734 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
735 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
736 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
737
Mingkai Hu90751912011-01-27 12:52:46 +0800738 /* Try to initialize PHY here, and return */
Bin Meng56a27a12016-01-11 22:41:22 -0800739 return init_phy(priv);
Mingkai Hu90751912011-01-27 12:52:46 +0800740}
741
742/*
743 * Initialize all the TSEC devices
744 *
745 * Returns the number of TSEC devices that were initialized
746 */
747int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
748{
749 int i;
Mario Sixd38de332018-01-15 11:08:21 +0100750 int count = 0;
Mingkai Hu90751912011-01-27 12:52:46 +0800751
752 for (i = 0; i < num; i++) {
Mario Sixd38de332018-01-15 11:08:21 +0100753 int ret = tsec_initialize(bis, &tsecs[i]);
754
Mingkai Hu90751912011-01-27 12:52:46 +0800755 if (ret > 0)
756 count += ret;
757 }
758
759 return count;
760}
761
762int tsec_standard_init(bd_t *bis)
763{
Andy Fleming063c1262011-04-08 02:10:54 -0500764 struct fsl_pq_mdio_info info;
765
Claudiu Manoilaec84bf2013-09-30 12:44:42 +0300766 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
Andy Fleming063c1262011-04-08 02:10:54 -0500767 info.name = DEFAULT_MII_NAME;
768
769 fsl_pq_mdio_init(bis, &info);
770
Mingkai Hu90751912011-01-27 12:52:46 +0800771 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
772}
Bin Meng9a1d6af2016-01-11 22:41:24 -0800773#else /* CONFIG_DM_ETH */
774int tsec_probe(struct udevice *dev)
775{
776 struct tsec_private *priv = dev_get_priv(dev);
777 struct eth_pdata *pdata = dev_get_platdata(dev);
778 struct fsl_pq_mdio_info mdio_info;
Mario Six1313aaf2018-01-15 11:08:23 +0100779 struct ofnode_phandle_args phandle_args;
780 ofnode parent;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800781 const char *phy_mode;
782 int ret;
783
Mario Six1313aaf2018-01-15 11:08:23 +0100784 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
Bin Meng9a1d6af2016-01-11 22:41:24 -0800785 priv->regs = (struct tsec *)pdata->iobase;
786
Mario Six1313aaf2018-01-15 11:08:23 +0100787 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
788 &phandle_args)) {
Bin Meng9a1d6af2016-01-11 22:41:24 -0800789 debug("phy-handle does not exist under tsec %s\n", dev->name);
790 return -ENOENT;
Mario Six1313aaf2018-01-15 11:08:23 +0100791 } else {
792 int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
793
794 priv->phyaddr = reg;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800795 }
796
Mario Six1313aaf2018-01-15 11:08:23 +0100797 parent = ofnode_get_parent(phandle_args.node);
798 if (ofnode_valid(parent)) {
Mario Six5e9d9ab2018-04-27 14:52:57 +0200799 int reg = ofnode_get_addr_index(parent, 0);
800
801 priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
Bin Meng9a1d6af2016-01-11 22:41:24 -0800802 } else {
803 debug("No parent node for PHY?\n");
804 return -ENOENT;
805 }
806
Mario Six1313aaf2018-01-15 11:08:23 +0100807 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
808 &phandle_args)) {
Bin Menga1c76c12016-01-11 22:41:25 -0800809 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
Mario Six1313aaf2018-01-15 11:08:23 +0100810 } else {
811 int reg = ofnode_read_u32_default(phandle_args.node, "reg",
812 CONFIG_SYS_TBIPA_VALUE);
813 priv->tbiaddr = reg;
Bin Menga1c76c12016-01-11 22:41:25 -0800814 }
815
Mario Six1313aaf2018-01-15 11:08:23 +0100816 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
Bin Meng9a1d6af2016-01-11 22:41:24 -0800817 if (phy_mode)
818 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
819 if (pdata->phy_interface == -1) {
820 debug("Invalid PHY interface '%s'\n", phy_mode);
821 return -EINVAL;
822 }
823 priv->interface = pdata->phy_interface;
824
825 /* Initialize flags */
826 priv->flags = TSEC_GIGABIT;
827 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
828 priv->flags |= TSEC_SGMII;
829
830 mdio_info.regs = priv->phyregs_sgmii;
831 mdio_info.name = (char *)dev->name;
832 ret = fsl_pq_mdio_init(NULL, &mdio_info);
833 if (ret)
834 return ret;
835
836 /* Reset the MAC */
837 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
838 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
839 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
840
841 priv->dev = dev;
842 priv->bus = miiphy_get_dev_by_name(dev->name);
843
844 /* Try to initialize PHY here, and return */
845 return !init_phy(priv);
846}
847
848int tsec_remove(struct udevice *dev)
849{
850 struct tsec_private *priv = dev->priv;
851
852 free(priv->phydev);
853 mdio_unregister(priv->bus);
854 mdio_free(priv->bus);
855
856 return 0;
857}
858
859static const struct eth_ops tsec_ops = {
860 .start = tsec_init,
861 .send = tsec_send,
862 .recv = tsec_recv,
863 .free_pkt = tsec_free_pkt,
864 .stop = tsec_halt,
865#ifdef CONFIG_MCAST_TFTP
866 .mcast = tsec_mcast_addr,
867#endif
868};
869
870static const struct udevice_id tsec_ids[] = {
871 { .compatible = "fsl,tsec" },
872 { }
873};
874
875U_BOOT_DRIVER(eth_tsec) = {
876 .name = "tsec",
877 .id = UCLASS_ETH,
878 .of_match = tsec_ids,
879 .probe = tsec_probe,
880 .remove = tsec_remove,
881 .ops = &tsec_ops,
882 .priv_auto_alloc_size = sizeof(struct tsec_private),
883 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
884 .flags = DM_FLAG_ALLOC_PRIV_DMA,
885};
886#endif /* CONFIG_DM_ETH */