blob: 86df141d6071201d7aecf1d8817083db3d7e9d73 [file] [log] [blame]
Simon Glassff3e0772015-03-05 12:25:25 -07001/*
2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
Simon Glassff3e0772015-03-05 12:25:25 -070011#include <inttypes.h>
12#include <pci.h>
Simon Glass21d1fe72015-11-29 13:18:03 -070013#include <asm/io.h>
Simon Glassff3e0772015-03-05 12:25:25 -070014#include <dm/device-internal.h>
Simon Glassbf501592017-05-18 20:09:51 -060015#include <dm/lists.h>
Bin Meng348b7442015-08-20 06:40:23 -070016#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
17#include <asm/fsp/fsp_support.h>
18#endif
Simon Glass5e23b8b2015-11-29 13:17:49 -070019#include "pci_internal.h"
Simon Glassff3e0772015-03-05 12:25:25 -070020
21DECLARE_GLOBAL_DATA_PTR;
22
Simon Glassa6eb93b2016-01-18 20:19:14 -070023int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass983c6ba22015-08-31 18:55:35 -060024{
25 int ret;
26
27 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
28
29 /* Since buses may not be numbered yet try a little harder with bus 0 */
30 if (ret == -ENODEV) {
Simon Glass3f603cb2016-02-11 13:23:26 -070031 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass983c6ba22015-08-31 18:55:35 -060032 if (ret)
33 return ret;
Simon Glass983c6ba22015-08-31 18:55:35 -060034 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
35 }
36
37 return ret;
38}
39
Simon Glass9f60fb02015-11-19 20:27:00 -070040struct udevice *pci_get_controller(struct udevice *dev)
41{
42 while (device_is_on_pci_bus(dev))
43 dev = dev->parent;
44
45 return dev;
46}
47
Simon Glass21ccce12015-11-29 13:17:47 -070048pci_dev_t dm_pci_get_bdf(struct udevice *dev)
Simon Glass4b515e42015-07-06 16:47:46 -060049{
50 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
51 struct udevice *bus = dev->parent;
52
53 return PCI_ADD_BUS(bus->seq, pplat->devfn);
54}
55
Simon Glassff3e0772015-03-05 12:25:25 -070056/**
57 * pci_get_bus_max() - returns the bus number of the last active bus
58 *
59 * @return last bus number, or -1 if no active buses
60 */
61static int pci_get_bus_max(void)
62{
63 struct udevice *bus;
64 struct uclass *uc;
65 int ret = -1;
66
67 ret = uclass_get(UCLASS_PCI, &uc);
68 uclass_foreach_dev(bus, uc) {
69 if (bus->seq > ret)
70 ret = bus->seq;
71 }
72
73 debug("%s: ret=%d\n", __func__, ret);
74
75 return ret;
76}
77
78int pci_last_busno(void)
79{
Bin Meng069155c2015-10-01 00:36:01 -070080 return pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -070081}
82
83int pci_get_ff(enum pci_size_t size)
84{
85 switch (size) {
86 case PCI_SIZE_8:
87 return 0xff;
88 case PCI_SIZE_16:
89 return 0xffff;
90 default:
91 return 0xffffffff;
92 }
93}
94
95int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
96 struct udevice **devp)
97{
98 struct udevice *dev;
99
100 for (device_find_first_child(bus, &dev);
101 dev;
102 device_find_next_child(&dev)) {
103 struct pci_child_platdata *pplat;
104
105 pplat = dev_get_parent_platdata(dev);
106 if (pplat && pplat->devfn == find_devfn) {
107 *devp = dev;
108 return 0;
109 }
110 }
111
112 return -ENODEV;
113}
114
Simon Glassf3f1fae2015-11-29 13:17:48 -0700115int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassff3e0772015-03-05 12:25:25 -0700116{
117 struct udevice *bus;
118 int ret;
119
Simon Glass983c6ba22015-08-31 18:55:35 -0600120 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700121 if (ret)
122 return ret;
123 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
124}
125
126static int pci_device_matches_ids(struct udevice *dev,
127 struct pci_device_id *ids)
128{
129 struct pci_child_platdata *pplat;
130 int i;
131
132 pplat = dev_get_parent_platdata(dev);
133 if (!pplat)
134 return -EINVAL;
135 for (i = 0; ids[i].vendor != 0; i++) {
136 if (pplat->vendor == ids[i].vendor &&
137 pplat->device == ids[i].device)
138 return i;
139 }
140
141 return -EINVAL;
142}
143
144int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
145 int *indexp, struct udevice **devp)
146{
147 struct udevice *dev;
148
149 /* Scan all devices on this bus */
150 for (device_find_first_child(bus, &dev);
151 dev;
152 device_find_next_child(&dev)) {
153 if (pci_device_matches_ids(dev, ids) >= 0) {
154 if ((*indexp)-- <= 0) {
155 *devp = dev;
156 return 0;
157 }
158 }
159 }
160
161 return -ENODEV;
162}
163
164int pci_find_device_id(struct pci_device_id *ids, int index,
165 struct udevice **devp)
166{
167 struct udevice *bus;
168
169 /* Scan all known buses */
170 for (uclass_first_device(UCLASS_PCI, &bus);
171 bus;
172 uclass_next_device(&bus)) {
173 if (!pci_bus_find_devices(bus, ids, &index, devp))
174 return 0;
175 }
176 *devp = NULL;
177
178 return -ENODEV;
179}
180
Simon Glass5c0bf642015-11-29 13:17:50 -0700181static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
182 unsigned int device, int *indexp,
183 struct udevice **devp)
184{
185 struct pci_child_platdata *pplat;
186 struct udevice *dev;
187
188 for (device_find_first_child(bus, &dev);
189 dev;
190 device_find_next_child(&dev)) {
191 pplat = dev_get_parent_platdata(dev);
192 if (pplat->vendor == vendor && pplat->device == device) {
193 if (!(*indexp)--) {
194 *devp = dev;
195 return 0;
196 }
197 }
198 }
199
200 return -ENODEV;
201}
202
203int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
204 struct udevice **devp)
205{
206 struct udevice *bus;
207
208 /* Scan all known buses */
209 for (uclass_first_device(UCLASS_PCI, &bus);
210 bus;
211 uclass_next_device(&bus)) {
212 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
213 return device_probe(*devp);
214 }
215 *devp = NULL;
216
217 return -ENODEV;
218}
219
Simon Glassa0eb8352015-11-29 13:17:52 -0700220int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
221{
222 struct udevice *dev;
223
224 /* Scan all known buses */
225 for (pci_find_first_device(&dev);
226 dev;
227 pci_find_next_device(&dev)) {
228 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
229
230 if (pplat->class == find_class && !index--) {
231 *devp = dev;
232 return device_probe(*devp);
233 }
234 }
235 *devp = NULL;
236
237 return -ENODEV;
238}
239
Simon Glassff3e0772015-03-05 12:25:25 -0700240int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
241 unsigned long value, enum pci_size_t size)
242{
243 struct dm_pci_ops *ops;
244
245 ops = pci_get_ops(bus);
246 if (!ops->write_config)
247 return -ENOSYS;
248 return ops->write_config(bus, bdf, offset, value, size);
249}
250
Simon Glass319dba12016-03-06 19:27:52 -0700251int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
252 u32 clr, u32 set)
253{
254 ulong val;
255 int ret;
256
257 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
258 if (ret)
259 return ret;
260 val &= ~clr;
261 val |= set;
262
263 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
264}
265
Simon Glassff3e0772015-03-05 12:25:25 -0700266int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
267 enum pci_size_t size)
268{
269 struct udevice *bus;
270 int ret;
271
Simon Glass983c6ba22015-08-31 18:55:35 -0600272 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700273 if (ret)
274 return ret;
275
Bin Meng4d8615c2015-07-19 00:20:04 +0800276 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700277}
278
Simon Glass66afb4e2015-08-10 07:05:03 -0600279int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
280 enum pci_size_t size)
281{
282 struct udevice *bus;
283
Bin Meng1e0f2262015-09-11 03:24:34 -0700284 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600285 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700286 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
287 size);
Simon Glass66afb4e2015-08-10 07:05:03 -0600288}
289
Simon Glassff3e0772015-03-05 12:25:25 -0700290int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
291{
292 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
293}
294
295int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
296{
297 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
298}
299
300int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
301{
302 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
303}
304
Simon Glass66afb4e2015-08-10 07:05:03 -0600305int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
306{
307 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
308}
309
310int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
311{
312 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
313}
314
315int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
316{
317 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
318}
319
Simon Glassff3e0772015-03-05 12:25:25 -0700320int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
321 unsigned long *valuep, enum pci_size_t size)
322{
323 struct dm_pci_ops *ops;
324
325 ops = pci_get_ops(bus);
326 if (!ops->read_config)
327 return -ENOSYS;
328 return ops->read_config(bus, bdf, offset, valuep, size);
329}
330
331int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
332 enum pci_size_t size)
333{
334 struct udevice *bus;
335 int ret;
336
Simon Glass983c6ba22015-08-31 18:55:35 -0600337 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700338 if (ret)
339 return ret;
340
Bin Meng4d8615c2015-07-19 00:20:04 +0800341 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700342}
343
Simon Glass66afb4e2015-08-10 07:05:03 -0600344int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
345 enum pci_size_t size)
346{
347 struct udevice *bus;
348
Bin Meng1e0f2262015-09-11 03:24:34 -0700349 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600350 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700351 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass66afb4e2015-08-10 07:05:03 -0600352 size);
353}
354
Simon Glassff3e0772015-03-05 12:25:25 -0700355int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
356{
357 unsigned long value;
358 int ret;
359
360 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
361 if (ret)
362 return ret;
363 *valuep = value;
364
365 return 0;
366}
367
368int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
369{
370 unsigned long value;
371 int ret;
372
373 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
374 if (ret)
375 return ret;
376 *valuep = value;
377
378 return 0;
379}
380
381int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
382{
383 unsigned long value;
384 int ret;
385
386 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
387 if (ret)
388 return ret;
389 *valuep = value;
390
391 return 0;
392}
393
Simon Glass66afb4e2015-08-10 07:05:03 -0600394int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
395{
396 unsigned long value;
397 int ret;
398
399 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
400 if (ret)
401 return ret;
402 *valuep = value;
403
404 return 0;
405}
406
407int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
408{
409 unsigned long value;
410 int ret;
411
412 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
413 if (ret)
414 return ret;
415 *valuep = value;
416
417 return 0;
418}
419
420int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
421{
422 unsigned long value;
423 int ret;
424
425 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
426 if (ret)
427 return ret;
428 *valuep = value;
429
430 return 0;
431}
432
Simon Glass319dba12016-03-06 19:27:52 -0700433int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
434{
435 u8 val;
436 int ret;
437
438 ret = dm_pci_read_config8(dev, offset, &val);
439 if (ret)
440 return ret;
441 val &= ~clr;
442 val |= set;
443
444 return dm_pci_write_config8(dev, offset, val);
445}
446
447int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
448{
449 u16 val;
450 int ret;
451
452 ret = dm_pci_read_config16(dev, offset, &val);
453 if (ret)
454 return ret;
455 val &= ~clr;
456 val |= set;
457
458 return dm_pci_write_config16(dev, offset, val);
459}
460
461int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
462{
463 u32 val;
464 int ret;
465
466 ret = dm_pci_read_config32(dev, offset, &val);
467 if (ret)
468 return ret;
469 val &= ~clr;
470 val |= set;
471
472 return dm_pci_write_config32(dev, offset, val);
473}
474
Bin Mengbbbcb522015-10-01 00:36:02 -0700475static void set_vga_bridge_bits(struct udevice *dev)
476{
477 struct udevice *parent = dev->parent;
478 u16 bc;
479
480 while (parent->seq != 0) {
481 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
482 bc |= PCI_BRIDGE_CTL_VGA;
483 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
484 parent = parent->parent;
485 }
486}
487
Simon Glassff3e0772015-03-05 12:25:25 -0700488int pci_auto_config_devices(struct udevice *bus)
489{
490 struct pci_controller *hose = bus->uclass_priv;
Bin Mengbbbcb522015-10-01 00:36:02 -0700491 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -0700492 unsigned int sub_bus;
493 struct udevice *dev;
494 int ret;
495
496 sub_bus = bus->seq;
497 debug("%s: start\n", __func__);
498 pciauto_config_init(hose);
499 for (ret = device_find_first_child(bus, &dev);
500 !ret && dev;
501 ret = device_find_next_child(&dev)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700502 unsigned int max_bus;
Simon Glass4d214552015-09-08 17:52:47 -0600503 int ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700504
Simon Glassff3e0772015-03-05 12:25:25 -0700505 debug("%s: device %s\n", __func__, dev->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700506 ret = dm_pciauto_config_device(dev);
Simon Glass4d214552015-09-08 17:52:47 -0600507 if (ret < 0)
508 return ret;
509 max_bus = ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700510 sub_bus = max(sub_bus, max_bus);
Bin Mengbbbcb522015-10-01 00:36:02 -0700511
512 pplat = dev_get_parent_platdata(dev);
513 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
514 set_vga_bridge_bits(dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700515 }
516 debug("%s: done\n", __func__);
517
518 return sub_bus;
519}
520
Simon Glass5e23b8b2015-11-29 13:17:49 -0700521int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassff3e0772015-03-05 12:25:25 -0700522{
Simon Glassff3e0772015-03-05 12:25:25 -0700523 int sub_bus;
524 int ret;
525
526 debug("%s\n", __func__);
Simon Glassff3e0772015-03-05 12:25:25 -0700527
528 sub_bus = pci_get_bus_max() + 1;
529 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700530 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700531
532 ret = device_probe(bus);
533 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600534 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassff3e0772015-03-05 12:25:25 -0700535 ret);
536 return ret;
537 }
538 if (sub_bus != bus->seq) {
539 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
540 __func__, bus->name, bus->seq, sub_bus);
541 return -EPIPE;
542 }
543 sub_bus = pci_get_bus_max();
Simon Glass5e23b8b2015-11-29 13:17:49 -0700544 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700545
546 return sub_bus;
547}
548
Simon Glassaba92962015-07-06 16:47:44 -0600549/**
550 * pci_match_one_device - Tell if a PCI device structure has a matching
551 * PCI device id structure
552 * @id: single PCI device id structure to match
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800553 * @find: the PCI device id structure to match against
Simon Glassaba92962015-07-06 16:47:44 -0600554 *
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800555 * Returns true if the finding pci_device_id structure matched or false if
556 * there is no match.
Simon Glassaba92962015-07-06 16:47:44 -0600557 */
558static bool pci_match_one_id(const struct pci_device_id *id,
559 const struct pci_device_id *find)
560{
561 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
562 (id->device == PCI_ANY_ID || id->device == find->device) &&
563 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
564 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
565 !((id->class ^ find->class) & id->class_mask))
566 return true;
567
568 return false;
569}
570
571/**
572 * pci_find_and_bind_driver() - Find and bind the right PCI driver
573 *
574 * This only looks at certain fields in the descriptor.
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600575 *
576 * @parent: Parent bus
577 * @find_id: Specification of the driver to find
578 * @bdf: Bus/device/function addreess - see PCI_BDF()
579 * @devp: Returns a pointer to the device created
580 * @return 0 if OK, -EPERM if the device is not needed before relocation and
581 * therefore was not created, other -ve value on error
Simon Glassaba92962015-07-06 16:47:44 -0600582 */
583static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600584 struct pci_device_id *find_id,
585 pci_dev_t bdf, struct udevice **devp)
Simon Glassaba92962015-07-06 16:47:44 -0600586{
587 struct pci_driver_entry *start, *entry;
588 const char *drv;
589 int n_ents;
590 int ret;
591 char name[30], *str;
Bin Meng08fc7b82015-08-20 06:40:17 -0700592 bool bridge;
Simon Glassaba92962015-07-06 16:47:44 -0600593
594 *devp = NULL;
595
596 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
597 find_id->vendor, find_id->device);
598 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
599 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
600 for (entry = start; entry != start + n_ents; entry++) {
601 const struct pci_device_id *id;
602 struct udevice *dev;
603 const struct driver *drv;
604
605 for (id = entry->match;
606 id->vendor || id->subvendor || id->class_mask;
607 id++) {
608 if (!pci_match_one_id(id, find_id))
609 continue;
610
611 drv = entry->driver;
Bin Meng08fc7b82015-08-20 06:40:17 -0700612
613 /*
614 * In the pre-relocation phase, we only bind devices
615 * whose driver has the DM_FLAG_PRE_RELOC set, to save
616 * precious memory space as on some platforms as that
617 * space is pretty limited (ie: using Cache As RAM).
618 */
619 if (!(gd->flags & GD_FLG_RELOC) &&
620 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600621 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700622
Simon Glassaba92962015-07-06 16:47:44 -0600623 /*
624 * We could pass the descriptor to the driver as
625 * platdata (instead of NULL) and allow its bind()
626 * method to return -ENOENT if it doesn't support this
627 * device. That way we could continue the search to
628 * find another driver. For now this doesn't seem
629 * necesssary, so just bind the first match.
630 */
631 ret = device_bind(parent, drv, drv->name, NULL, -1,
632 &dev);
633 if (ret)
634 goto error;
635 debug("%s: Match found: %s\n", __func__, drv->name);
636 dev->driver_data = find_id->driver_data;
637 *devp = dev;
638 return 0;
639 }
640 }
641
Bin Meng08fc7b82015-08-20 06:40:17 -0700642 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
643 /*
644 * In the pre-relocation phase, we only bind bridge devices to save
645 * precious memory space as on some platforms as that space is pretty
646 * limited (ie: using Cache As RAM).
647 */
648 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600649 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700650
Simon Glassaba92962015-07-06 16:47:44 -0600651 /* Bind a generic driver so that the device can be used */
Bin Meng4d8615c2015-07-19 00:20:04 +0800652 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
653 PCI_FUNC(bdf));
Simon Glassaba92962015-07-06 16:47:44 -0600654 str = strdup(name);
655 if (!str)
656 return -ENOMEM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700657 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
658
Simon Glassaba92962015-07-06 16:47:44 -0600659 ret = device_bind_driver(parent, drv, str, devp);
660 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600661 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
xypron.glpk@gmx.dec42640c2017-05-08 20:40:16 +0200662 free(str);
Simon Glassaba92962015-07-06 16:47:44 -0600663 return ret;
664 }
665 debug("%s: No match found: bound generic driver instead\n", __func__);
666
667 return 0;
668
669error:
670 debug("%s: No match found: error %d\n", __func__, ret);
671 return ret;
672}
673
Simon Glassff3e0772015-03-05 12:25:25 -0700674int pci_bind_bus_devices(struct udevice *bus)
675{
676 ulong vendor, device;
677 ulong header_type;
Bin Meng4d8615c2015-07-19 00:20:04 +0800678 pci_dev_t bdf, end;
Simon Glassff3e0772015-03-05 12:25:25 -0700679 bool found_multi;
680 int ret;
681
682 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800683 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
684 PCI_MAX_PCI_FUNCTIONS - 1);
Yoshinori Sato6d9f5b02016-04-25 15:41:01 +0900685 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
Bin Meng4d8615c2015-07-19 00:20:04 +0800686 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700687 struct pci_child_platdata *pplat;
688 struct udevice *dev;
689 ulong class;
690
Bin Meng4d8615c2015-07-19 00:20:04 +0800691 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassff3e0772015-03-05 12:25:25 -0700692 continue;
693 /* Check only the first access, we don't expect problems */
Bin Meng4d8615c2015-07-19 00:20:04 +0800694 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
Simon Glassff3e0772015-03-05 12:25:25 -0700695 &header_type, PCI_SIZE_8);
696 if (ret)
697 goto error;
Bin Meng4d8615c2015-07-19 00:20:04 +0800698 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
Simon Glassff3e0772015-03-05 12:25:25 -0700699 PCI_SIZE_16);
700 if (vendor == 0xffff || vendor == 0x0000)
701 continue;
702
Bin Meng4d8615c2015-07-19 00:20:04 +0800703 if (!PCI_FUNC(bdf))
Simon Glassff3e0772015-03-05 12:25:25 -0700704 found_multi = header_type & 0x80;
705
706 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
Bin Meng4d8615c2015-07-19 00:20:04 +0800707 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
708 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassff3e0772015-03-05 12:25:25 -0700709 PCI_SIZE_16);
Bin Meng4d8615c2015-07-19 00:20:04 +0800710 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glassaba92962015-07-06 16:47:44 -0600711 PCI_SIZE_32);
712 class >>= 8;
Simon Glassff3e0772015-03-05 12:25:25 -0700713
714 /* Find this device in the device tree */
Bin Meng4d8615c2015-07-19 00:20:04 +0800715 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700716
Simon Glass8bd42522015-11-29 13:18:09 -0700717 /* If nothing in the device tree, bind a device */
Simon Glassff3e0772015-03-05 12:25:25 -0700718 if (ret == -ENODEV) {
Simon Glassaba92962015-07-06 16:47:44 -0600719 struct pci_device_id find_id;
720 ulong val;
Simon Glassff3e0772015-03-05 12:25:25 -0700721
Simon Glassaba92962015-07-06 16:47:44 -0600722 memset(&find_id, '\0', sizeof(find_id));
723 find_id.vendor = vendor;
724 find_id.device = device;
725 find_id.class = class;
726 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng4d8615c2015-07-19 00:20:04 +0800727 pci_bus_read_config(bus, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600728 PCI_SUBSYSTEM_VENDOR_ID,
729 &val, PCI_SIZE_32);
730 find_id.subvendor = val & 0xffff;
731 find_id.subdevice = val >> 16;
732 }
Bin Meng4d8615c2015-07-19 00:20:04 +0800733 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600734 &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700735 }
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600736 if (ret == -EPERM)
737 continue;
738 else if (ret)
Simon Glassff3e0772015-03-05 12:25:25 -0700739 return ret;
740
741 /* Update the platform data */
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600742 pplat = dev_get_parent_platdata(dev);
743 pplat->devfn = PCI_MASK_BUS(bdf);
744 pplat->vendor = vendor;
745 pplat->device = device;
746 pplat->class = class;
Simon Glassff3e0772015-03-05 12:25:25 -0700747 }
748
749 return 0;
750error:
751 printf("Cannot read bus configuration: %d\n", ret);
752
753 return ret;
754}
755
Simon Glassbf501592017-05-18 20:09:51 -0600756static int decode_regions(struct pci_controller *hose, ofnode parent_node,
757 ofnode node)
Simon Glassff3e0772015-03-05 12:25:25 -0700758{
759 int pci_addr_cells, addr_cells, size_cells;
Simon Glass2084c5a2015-11-19 20:26:57 -0700760 phys_addr_t base = 0, size;
Simon Glassff3e0772015-03-05 12:25:25 -0700761 int cells_per_record;
762 const u32 *prop;
763 int len;
764 int i;
765
Masahiro Yamada61e51ba2017-06-22 16:54:05 +0900766 prop = ofnode_get_property(node, "ranges", &len);
Simon Glassff3e0772015-03-05 12:25:25 -0700767 if (!prop)
768 return -EINVAL;
Simon Glass878d68c2017-06-12 06:21:31 -0600769 pci_addr_cells = ofnode_read_simple_addr_cells(node);
770 addr_cells = ofnode_read_simple_addr_cells(parent_node);
771 size_cells = ofnode_read_simple_size_cells(node);
Simon Glassff3e0772015-03-05 12:25:25 -0700772
773 /* PCI addresses are always 3-cells */
774 len /= sizeof(u32);
775 cells_per_record = pci_addr_cells + addr_cells + size_cells;
776 hose->region_count = 0;
777 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
778 cells_per_record);
779 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
780 u64 pci_addr, addr, size;
781 int space_code;
782 u32 flags;
783 int type;
Simon Glass9526d832015-11-19 20:26:58 -0700784 int pos;
Simon Glassff3e0772015-03-05 12:25:25 -0700785
786 if (len < cells_per_record)
787 break;
788 flags = fdt32_to_cpu(prop[0]);
789 space_code = (flags >> 24) & 3;
790 pci_addr = fdtdec_get_number(prop + 1, 2);
791 prop += pci_addr_cells;
792 addr = fdtdec_get_number(prop, addr_cells);
793 prop += addr_cells;
794 size = fdtdec_get_number(prop, size_cells);
795 prop += size_cells;
796 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
797 ", size=%" PRIx64 ", space_code=%d\n", __func__,
798 hose->region_count, pci_addr, addr, size, space_code);
799 if (space_code & 2) {
800 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
801 PCI_REGION_MEM;
802 } else if (space_code & 1) {
803 type = PCI_REGION_IO;
804 } else {
805 continue;
806 }
Simon Glass9526d832015-11-19 20:26:58 -0700807 pos = -1;
808 for (i = 0; i < hose->region_count; i++) {
809 if (hose->regions[i].flags == type)
810 pos = i;
811 }
812 if (pos == -1)
813 pos = hose->region_count++;
814 debug(" - type=%d, pos=%d\n", type, pos);
815 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassff3e0772015-03-05 12:25:25 -0700816 }
817
818 /* Add a region for our local memory */
Simon Glass2084c5a2015-11-19 20:26:57 -0700819 size = gd->ram_size;
820#ifdef CONFIG_SYS_SDRAM_BASE
821 base = CONFIG_SYS_SDRAM_BASE;
822#endif
823 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
824 size = gd->pci_ram_top - base;
825 pci_set_region(hose->regions + hose->region_count++, base, base,
826 size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Simon Glassff3e0772015-03-05 12:25:25 -0700827
828 return 0;
829}
830
831static int pci_uclass_pre_probe(struct udevice *bus)
832{
833 struct pci_controller *hose;
834 int ret;
835
836 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
837 bus->parent->name);
838 hose = bus->uclass_priv;
839
840 /* For bridges, use the top-level PCI controller */
Paul Burton65f62b12016-09-08 07:47:32 +0100841 if (!device_is_on_pci_bus(bus)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700842 hose->ctlr = bus;
Simon Glassbf501592017-05-18 20:09:51 -0600843 ret = decode_regions(hose, dev_ofnode(bus->parent),
844 dev_ofnode(bus));
Simon Glassff3e0772015-03-05 12:25:25 -0700845 if (ret) {
846 debug("%s: Cannot decode regions\n", __func__);
847 return ret;
848 }
849 } else {
850 struct pci_controller *parent_hose;
851
852 parent_hose = dev_get_uclass_priv(bus->parent);
853 hose->ctlr = parent_hose->bus;
854 }
855 hose->bus = bus;
856 hose->first_busno = bus->seq;
857 hose->last_busno = bus->seq;
858
859 return 0;
860}
861
862static int pci_uclass_post_probe(struct udevice *bus)
863{
864 int ret;
865
Simon Glassff3e0772015-03-05 12:25:25 -0700866 debug("%s: probing bus %d\n", __func__, bus->seq);
867 ret = pci_bind_bus_devices(bus);
868 if (ret)
869 return ret;
870
871#ifdef CONFIG_PCI_PNP
872 ret = pci_auto_config_devices(bus);
Simon Glass4d214552015-09-08 17:52:47 -0600873 if (ret < 0)
874 return ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700875#endif
876
Bin Meng348b7442015-08-20 06:40:23 -0700877#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
878 /*
879 * Per Intel FSP specification, we should call FSP notify API to
880 * inform FSP that PCI enumeration has been done so that FSP will
881 * do any necessary initialization as required by the chipset's
882 * BIOS Writer's Guide (BWG).
883 *
884 * Unfortunately we have to put this call here as with driver model,
885 * the enumeration is all done on a lazy basis as needed, so until
886 * something is touched on PCI it won't happen.
887 *
888 * Note we only call this 1) after U-Boot is relocated, and 2)
889 * root bus has finished probing.
890 */
Simon Glass4d214552015-09-08 17:52:47 -0600891 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
Bin Meng348b7442015-08-20 06:40:23 -0700892 ret = fsp_init_phase_pci();
Simon Glass4d214552015-09-08 17:52:47 -0600893 if (ret)
894 return ret;
895 }
Bin Meng348b7442015-08-20 06:40:23 -0700896#endif
897
Simon Glass4d214552015-09-08 17:52:47 -0600898 return 0;
Simon Glassff3e0772015-03-05 12:25:25 -0700899}
900
901static int pci_uclass_child_post_bind(struct udevice *dev)
902{
903 struct pci_child_platdata *pplat;
904 struct fdt_pci_addr addr;
905 int ret;
906
Simon Glassbf501592017-05-18 20:09:51 -0600907 if (!dev_of_valid(dev))
Simon Glassff3e0772015-03-05 12:25:25 -0700908 return 0;
909
910 /*
911 * We could read vendor, device, class if available. But for now we
912 * just check the address.
913 */
914 pplat = dev_get_parent_platdata(dev);
Simon Glassbf501592017-05-18 20:09:51 -0600915 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
916 &addr);
Simon Glassff3e0772015-03-05 12:25:25 -0700917
918 if (ret) {
919 if (ret != -ENOENT)
920 return -EINVAL;
921 } else {
Bin Mengdce54dd2015-08-20 06:40:26 -0700922 /* extract the devfn from fdt_pci_addr */
923 pplat->devfn = addr.phys_hi & 0xff00;
Simon Glassff3e0772015-03-05 12:25:25 -0700924 }
925
926 return 0;
927}
928
Bin Meng4d8615c2015-07-19 00:20:04 +0800929static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
930 uint offset, ulong *valuep,
931 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -0700932{
933 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -0700934
935 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
936}
937
Bin Meng4d8615c2015-07-19 00:20:04 +0800938static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
939 uint offset, ulong value,
940 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -0700941{
942 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -0700943
944 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
945}
946
Simon Glass76c3fbc2015-08-10 07:05:04 -0600947static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
948{
949 struct udevice *dev;
950 int ret = 0;
951
952 /*
953 * Scan through all the PCI controllers. On x86 there will only be one
954 * but that is not necessarily true on other hardware.
955 */
956 do {
957 device_find_first_child(bus, &dev);
958 if (dev) {
959 *devp = dev;
960 return 0;
961 }
962 ret = uclass_next_device(&bus);
963 if (ret)
964 return ret;
965 } while (bus);
966
967 return 0;
968}
969
970int pci_find_next_device(struct udevice **devp)
971{
972 struct udevice *child = *devp;
973 struct udevice *bus = child->parent;
974 int ret;
975
976 /* First try all the siblings */
977 *devp = NULL;
978 while (child) {
979 device_find_next_child(&child);
980 if (child) {
981 *devp = child;
982 return 0;
983 }
984 }
985
986 /* We ran out of siblings. Try the next bus */
987 ret = uclass_next_device(&bus);
988 if (ret)
989 return ret;
990
991 return bus ? skip_to_next_device(bus, devp) : 0;
992}
993
994int pci_find_first_device(struct udevice **devp)
995{
996 struct udevice *bus;
997 int ret;
998
999 *devp = NULL;
1000 ret = uclass_first_device(UCLASS_PCI, &bus);
1001 if (ret)
1002 return ret;
1003
1004 return skip_to_next_device(bus, devp);
1005}
1006
Simon Glass9289db62015-11-19 20:26:59 -07001007ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1008{
1009 switch (size) {
1010 case PCI_SIZE_8:
1011 return (value >> ((offset & 3) * 8)) & 0xff;
1012 case PCI_SIZE_16:
1013 return (value >> ((offset & 2) * 8)) & 0xffff;
1014 default:
1015 return value;
1016 }
1017}
1018
1019ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1020 enum pci_size_t size)
1021{
1022 uint off_mask;
1023 uint val_mask, shift;
1024 ulong ldata, mask;
1025
1026 switch (size) {
1027 case PCI_SIZE_8:
1028 off_mask = 3;
1029 val_mask = 0xff;
1030 break;
1031 case PCI_SIZE_16:
1032 off_mask = 2;
1033 val_mask = 0xffff;
1034 break;
1035 default:
1036 return value;
1037 }
1038 shift = (offset & off_mask) * 8;
1039 ldata = (value & val_mask) << shift;
1040 mask = val_mask << shift;
1041 value = (old & ~mask) | ldata;
1042
1043 return value;
1044}
1045
Simon Glassf9260332015-11-19 20:27:01 -07001046int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1047 struct pci_region **memp, struct pci_region **prefp)
1048{
1049 struct udevice *bus = pci_get_controller(dev);
1050 struct pci_controller *hose = dev_get_uclass_priv(bus);
1051 int i;
1052
1053 *iop = NULL;
1054 *memp = NULL;
1055 *prefp = NULL;
1056 for (i = 0; i < hose->region_count; i++) {
1057 switch (hose->regions[i].flags) {
1058 case PCI_REGION_IO:
1059 if (!*iop || (*iop)->size < hose->regions[i].size)
1060 *iop = hose->regions + i;
1061 break;
1062 case PCI_REGION_MEM:
1063 if (!*memp || (*memp)->size < hose->regions[i].size)
1064 *memp = hose->regions + i;
1065 break;
1066 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1067 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1068 *prefp = hose->regions + i;
1069 break;
1070 }
1071 }
1072
1073 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1074}
1075
Simon Glassbab17cf2015-11-29 13:17:53 -07001076u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1077{
1078 u32 addr;
1079 int bar;
1080
1081 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1082 dm_pci_read_config32(dev, bar, &addr);
1083 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1084 return addr & PCI_BASE_ADDRESS_IO_MASK;
1085 else
1086 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1087}
1088
Simon Glass9d731c82016-01-18 20:19:15 -07001089void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1090{
1091 int bar;
1092
1093 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1094 dm_pci_write_config32(dev, bar, addr);
1095}
1096
Simon Glass21d1fe72015-11-29 13:18:03 -07001097static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1098 pci_addr_t bus_addr, unsigned long flags,
1099 unsigned long skip_mask, phys_addr_t *pa)
1100{
1101 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1102 struct pci_region *res;
1103 int i;
1104
1105 for (i = 0; i < hose->region_count; i++) {
1106 res = &hose->regions[i];
1107
1108 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1109 continue;
1110
1111 if (res->flags & skip_mask)
1112 continue;
1113
1114 if (bus_addr >= res->bus_start &&
1115 (bus_addr - res->bus_start) < res->size) {
1116 *pa = (bus_addr - res->bus_start + res->phys_start);
1117 return 0;
1118 }
1119 }
1120
1121 return 1;
1122}
1123
1124phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1125 unsigned long flags)
1126{
1127 phys_addr_t phys_addr = 0;
1128 struct udevice *ctlr;
1129 int ret;
1130
1131 /* The root controller has the region information */
1132 ctlr = pci_get_controller(dev);
1133
1134 /*
1135 * if PCI_REGION_MEM is set we do a two pass search with preference
1136 * on matches that don't have PCI_REGION_SYS_MEMORY set
1137 */
1138 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1139 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1140 flags, PCI_REGION_SYS_MEMORY,
1141 &phys_addr);
1142 if (!ret)
1143 return phys_addr;
1144 }
1145
1146 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1147
1148 if (ret)
1149 puts("pci_hose_bus_to_phys: invalid physical address\n");
1150
1151 return phys_addr;
1152}
1153
1154int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1155 unsigned long flags, unsigned long skip_mask,
1156 pci_addr_t *ba)
1157{
1158 struct pci_region *res;
1159 struct udevice *ctlr;
1160 pci_addr_t bus_addr;
1161 int i;
1162 struct pci_controller *hose;
1163
1164 /* The root controller has the region information */
1165 ctlr = pci_get_controller(dev);
1166 hose = dev_get_uclass_priv(ctlr);
1167
1168 for (i = 0; i < hose->region_count; i++) {
1169 res = &hose->regions[i];
1170
1171 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1172 continue;
1173
1174 if (res->flags & skip_mask)
1175 continue;
1176
1177 bus_addr = phys_addr - res->phys_start + res->bus_start;
1178
1179 if (bus_addr >= res->bus_start &&
1180 (bus_addr - res->bus_start) < res->size) {
1181 *ba = bus_addr;
1182 return 0;
1183 }
1184 }
1185
1186 return 1;
1187}
1188
1189pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1190 unsigned long flags)
1191{
1192 pci_addr_t bus_addr = 0;
1193 int ret;
1194
1195 /*
1196 * if PCI_REGION_MEM is set we do a two pass search with preference
1197 * on matches that don't have PCI_REGION_SYS_MEMORY set
1198 */
1199 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1200 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1201 PCI_REGION_SYS_MEMORY, &bus_addr);
1202 if (!ret)
1203 return bus_addr;
1204 }
1205
1206 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1207
1208 if (ret)
1209 puts("pci_hose_phys_to_bus: invalid physical address\n");
1210
1211 return bus_addr;
1212}
1213
1214void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1215{
1216 pci_addr_t pci_bus_addr;
1217 u32 bar_response;
1218
1219 /* read BAR address */
1220 dm_pci_read_config32(dev, bar, &bar_response);
1221 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1222
1223 /*
1224 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1225 * isn't actualy used on any platform because u-boot assumes a static
1226 * linear mapping. In the future, this could read the BAR size
1227 * and pass that as the size if needed.
1228 */
1229 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1230}
1231
Simon Glassff3e0772015-03-05 12:25:25 -07001232UCLASS_DRIVER(pci) = {
1233 .id = UCLASS_PCI,
1234 .name = "pci",
Simon Glass2bb02e42015-05-10 21:08:06 -06001235 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glass91195482016-07-05 17:10:10 -06001236 .post_bind = dm_scan_fdt_dev,
Simon Glassff3e0772015-03-05 12:25:25 -07001237 .pre_probe = pci_uclass_pre_probe,
1238 .post_probe = pci_uclass_post_probe,
1239 .child_post_bind = pci_uclass_child_post_bind,
1240 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1241 .per_child_platdata_auto_alloc_size =
1242 sizeof(struct pci_child_platdata),
1243};
1244
1245static const struct dm_pci_ops pci_bridge_ops = {
1246 .read_config = pci_bridge_read_config,
1247 .write_config = pci_bridge_write_config,
1248};
1249
1250static const struct udevice_id pci_bridge_ids[] = {
1251 { .compatible = "pci-bridge" },
1252 { }
1253};
1254
1255U_BOOT_DRIVER(pci_bridge_drv) = {
1256 .name = "pci_bridge_drv",
1257 .id = UCLASS_PCI,
1258 .of_match = pci_bridge_ids,
1259 .ops = &pci_bridge_ops,
1260};
1261
1262UCLASS_DRIVER(pci_generic) = {
1263 .id = UCLASS_PCI_GENERIC,
1264 .name = "pci_generic",
1265};
1266
1267static const struct udevice_id pci_generic_ids[] = {
1268 { .compatible = "pci-generic" },
1269 { }
1270};
1271
1272U_BOOT_DRIVER(pci_generic_drv) = {
1273 .name = "pci_generic_drv",
1274 .id = UCLASS_PCI_GENERIC,
1275 .of_match = pci_generic_ids,
1276};
Stephen Warrene578b922016-01-26 11:10:11 -07001277
1278void pci_init(void)
1279{
1280 struct udevice *bus;
1281
1282 /*
1283 * Enumerate all known controller devices. Enumeration has the side-
1284 * effect of probing them, so PCIe devices will be enumerated too.
1285 */
1286 for (uclass_first_device(UCLASS_PCI, &bus);
1287 bus;
1288 uclass_next_device(&bus)) {
1289 ;
1290 }
1291}